`timescale 1 ns / 1 ps

module trigger_top#
	(
		parameter				CLK_PERIOD	= 10
	)
	(
		input					clk						,
		input					rst_n					,
		
		input					trigger_reset			,
		
		input		[32-1:0]	trigger_in_int			,
		input		[32-1:0]	trigger_in_ext			,

		output		[32-1:0]	m_trigger_tdata			,
		output					m_trigger_tvalid		,
		input					m_trigger_tready		,

		output	reg				error_overflow
	);
	
	//*****************************************************************************
	// localparam definition
	//*****************************************************************************
	localparam 	CLKS		= 10	 					;
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	wire	[32-1:0]		trigger_in_ext_t			;
	
	wire					trigger_1_tvalid			;
	wire	[32-1:0]		trigger_1_tdata				;
	wire					trigger_2_tvalid			;
	wire	[32-1:0]		trigger_2_tdata				;

	reg						trigger_1_tvalid_r			;
	reg		[32-1:0]		trigger_1_tdata_r			;
	reg						trigger_2_tvalid_r			;
	reg		[32-1:0]		trigger_2_tdata_r			;
	reg						trigger_2_tvalid_rr			;
	reg		[32-1:0]		trigger_2_tdata_rr			;

	reg		[32-1:0]		trigger_collect_tdata		;
	reg						trigger_collect_tvalid		;
	wire					trigger_collect_tready		;
	
	reg		[ 8-1:0]		clk_cnt						;
	reg						s_axis_aresetn				;

	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	debouncing# 
		(
			.CLK_PERIOD			( CLK_PERIOD			),
			.DATA_WIDTH			( 32					),
			.DELAY1_US			( 30					),
			.DELAY2_US			( 50					)
		)
	u_debouncing_ext
		(
			.clk				( clk					),
			.rst_n				( rst_n					),

			.data_in			( trigger_in_ext		),
			.data_out			( trigger_in_ext_t		)
		);
		
	trigger_detection u_trigger_detection_int
		(
			.clk				( clk					),
			.rst_n				( rst_n					),

			.trigger_in			( trigger_in_int		),

			.trigger_tdata		( trigger_1_tdata		),
			.trigger_tvalid		( trigger_1_tvalid		)
		);
		
	trigger_detection u_trigger_detection_ext
		(
			.clk				( clk					),
			.rst_n				( rst_n					),

			.trigger_in			( trigger_in_ext_t		),

			.trigger_tdata		( trigger_2_tdata		),
			.trigger_tvalid		( trigger_2_tvalid		)
		);
		
	axis_data_fifo_w32_d16 u_trigger_fifo
		(
			.s_axis_aresetn		( s_axis_aresetn		),
			.s_axis_aclk		( clk					),

			.s_axis_tvalid		( trigger_collect_tvalid),
			.s_axis_tready		( trigger_collect_tready),
			.s_axis_tdata		( trigger_collect_tdata	),

			.m_axis_tvalid		( m_trigger_tvalid		),
			.m_axis_tready		( m_trigger_tready		),
			.m_axis_tdata		( m_trigger_tdata		)
		);
	
	//*****************************************************************************
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			trigger_1_tvalid_r <= 1'b0;
			trigger_1_tdata_r  <= 0;
			trigger_2_tvalid_r <= 1'b0;
			trigger_2_tdata_r  <= 0;
		end else begin
			trigger_1_tvalid_r <= trigger_1_tvalid;
			trigger_1_tdata_r  <= trigger_1_tdata;
			trigger_2_tvalid_r <= trigger_2_tvalid;
			trigger_2_tdata_r  <= trigger_2_tdata;
		end
	end

	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			trigger_2_tvalid_rr <= 1'b0;
			trigger_2_tdata_rr  <= 0;
		end else if (trigger_1_tvalid_r && trigger_2_tvalid_r) begin
			trigger_2_tvalid_rr <= trigger_2_tvalid_r;
			trigger_2_tdata_rr  <= trigger_2_tdata_r;
		end else begin
			trigger_2_tvalid_rr <= 1'b0;
			trigger_2_tdata_rr  <= 0;
		end
	end

	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			trigger_collect_tvalid <= 1'b0;
			trigger_collect_tdata  <= 0;
		end else if (trigger_1_tvalid_r || trigger_2_tvalid_r || trigger_2_tvalid_rr) begin
			trigger_collect_tvalid <= 1'b1;
			trigger_collect_tdata  <= trigger_1_tvalid_r? trigger_1_tdata_r:
							(trigger_2_tvalid_r? trigger_2_tdata_r:
							(trigger_2_tvalid_rr? trigger_2_tdata_rr:
							trigger_collect_tdata));
		end else
			trigger_collect_tvalid <= 1'b0;
	end
	
	//trigger clear
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			clk_cnt <= 0;
		else if (clk_cnt != CLKS)
			clk_cnt = clk_cnt + 1'b1;
		else if (trigger_reset)
			clk_cnt <= 0;
	end

	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			s_axis_aresetn <= 1'b1;
		else if (clk_cnt != CLKS)
			s_axis_aresetn <= 1'b0;
		else
			s_axis_aresetn <= 1'b1;
	end

	//error: trigger overflow
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			error_overflow <= 1'b0;
		else if (trigger_collect_tvalid && ~trigger_collect_tready)
			error_overflow <= 1'b1;
		else
			error_overflow <= 1'b0;
	end
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	
	
endmodule