`timescale 1ns/1ps
 
module trans_timer_tb();

	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	parameter 		T_CLK 		= 20;		//ns
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg							clk				;
	reg							rst_n			;
	
	reg							enable			;
	reg		[32-1:0]			update_period	;
	
	wire						update			;
	wire						trans			;
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	always #( T_CLK/2.0 )  clk = !clk;
	
	initial begin
		Initial();
		#100 rst_n = 0;
		#100 rst_n = 1;
		
		#500
		@ ( posedge clk ) enable <= 1'b1;
		
		#1_000
		@ ( posedge clk ) enable <= 1'b0;
		#500
		@ ( posedge clk ) update_period	<= (300)/20;
		@ ( posedge clk ) enable <= 1'b1;
		
		#1_000
		@ ( posedge clk ) enable <= 1'b0;
		#500
		@ ( posedge clk ) update_period	<= (320)/20;
		@ ( posedge clk ) enable <= 1'b1;
		
		#1_000
		@ ( posedge clk ) enable <= 1'b0;
		#500
		@ ( posedge clk ) update_period	<= (340)/20;
		@ ( posedge clk ) enable <= 1'b1;
		
	end
	
	//*****************************************************************************
	// Task
	//*****************************************************************************
	task Initial;
		begin
			clk				<= 1'b0		;
			rst_n			<= 1'b0		;
			
			enable			<= 1'b0		;
			update_period	<= (160)/20;
		end
	endtask	
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	trans_timer# 
		(
			.CLK_PERIOD		( T_CLK			),
			.TRANS_PERIOD	( 160			)
		)
	DUT
		(
			.clk			( clk 			),
			.rst_n			( rst_n 		),
			
			.enable			( enable 		),
			.update_period	( update_period	),
			
			.update			( update   		),
			.trans			( trans   		)
		);
	
	
endmodule