`timescale 1 ns / 1 ps

module stim_monitor#
	(
		parameter		CLK_PERIOD			= 10	,
		parameter		CHECK_PERIOD_MS		= 1000		// <=1000
	)
	(
		input					clk					,
		input					rst_n				,
		
		input		[64-1:0]	stim_monitor_in		,

		output		[64-1:0]	stim_monitor_rt		,
		output	reg	[64-1:0]	stim_monitor_latch
	);
	
	//*****************************************************************************
	// localparam definition
	//*****************************************************************************
	localparam 	CLKS_OF_MS		= 1000*1000/CLK_PERIOD;
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg		[20-1:0]			clk_cnt			;
	reg							pulse_ms		;
	reg		[12-1:0]			latch_period	;

	wire	[64-1:0]			monitor_in_map	;
	reg		[64-1:0]			monitor_latch	;
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	
	
	//*****************************************************************************
	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n )
			clk_cnt <= 0;
		else if ( clk_cnt == CLKS_OF_MS - 1 )
			clk_cnt <= 0;
		else
			clk_cnt <= clk_cnt + 1'b1;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n )
			pulse_ms <= 1'b0;
		else if ( clk_cnt == CLKS_OF_MS - 1 )
			pulse_ms <= 1'b1;
		else
			pulse_ms <= 1'b0;
	end

	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n )
			latch_period <= 0;
		else if ( pulse_ms ) begin
			if ( latch_period == CHECK_PERIOD_MS - 1 )
				latch_period <= 0;
			else
				latch_period <= latch_period + 1'b1;
		end

	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n )
			monitor_latch <= 0;
		else if ( pulse_ms && (latch_period == CHECK_PERIOD_MS - 1) )
			monitor_latch <= 0;
		else
			monitor_latch = monitor_latch | monitor_in_map;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n )
			stim_monitor_latch <= 0;
		else if ( pulse_ms && (latch_period == CHECK_PERIOD_MS - 1) )
			stim_monitor_latch <= monitor_latch;
	end
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	assign monitor_in_map[ 0] = stim_monitor_in[55];
	assign monitor_in_map[ 1] = stim_monitor_in[56];
	assign monitor_in_map[ 2] = stim_monitor_in[54];
	assign monitor_in_map[ 3] = stim_monitor_in[57];
	assign monitor_in_map[ 4] = stim_monitor_in[34];
	assign monitor_in_map[ 5] = stim_monitor_in[35];
	assign monitor_in_map[ 6] = stim_monitor_in[32];
	assign monitor_in_map[ 7] = stim_monitor_in[52];
	assign monitor_in_map[ 8] = stim_monitor_in[38];
	assign monitor_in_map[ 9] = stim_monitor_in[10];
	assign monitor_in_map[10] = stim_monitor_in[11];
	assign monitor_in_map[11] = stim_monitor_in[58];
	assign monitor_in_map[12] = stim_monitor_in[59];
	assign monitor_in_map[13] = stim_monitor_in[ 9];
	assign monitor_in_map[14] = stim_monitor_in[15];
	assign monitor_in_map[15] = stim_monitor_in[13];
	assign monitor_in_map[16] = stim_monitor_in[30];
	assign monitor_in_map[17] = stim_monitor_in[19];
	assign monitor_in_map[18] = stim_monitor_in[48];
	assign monitor_in_map[19] = stim_monitor_in[61];
	assign monitor_in_map[20] = stim_monitor_in[49];
	assign monitor_in_map[21] = stim_monitor_in[37];
	assign monitor_in_map[22] = stim_monitor_in[60];
	assign monitor_in_map[23] = stim_monitor_in[ 8];
	assign monitor_in_map[24] = stim_monitor_in[36];
	assign monitor_in_map[25] = stim_monitor_in[53];
	assign monitor_in_map[26] = stim_monitor_in[33];
	assign monitor_in_map[27] = stim_monitor_in[63];
	assign monitor_in_map[28] = stim_monitor_in[51];
	assign monitor_in_map[29] = stim_monitor_in[62];
	assign monitor_in_map[30] = stim_monitor_in[39];
	assign monitor_in_map[31] = stim_monitor_in[50];
	assign monitor_in_map[32] = stim_monitor_in[28];
	assign monitor_in_map[33] = stim_monitor_in[18];
	assign monitor_in_map[34] = stim_monitor_in[29];
	assign monitor_in_map[35] = stim_monitor_in[27];
	assign monitor_in_map[36] = stim_monitor_in[17];
	assign monitor_in_map[37] = stim_monitor_in[31];
	assign monitor_in_map[38] = stim_monitor_in[26];
	assign monitor_in_map[39] = stim_monitor_in[16];
	assign monitor_in_map[40] = stim_monitor_in[24];
	assign monitor_in_map[41] = stim_monitor_in[25];
	assign monitor_in_map[42] = stim_monitor_in[22];
	assign monitor_in_map[43] = stim_monitor_in[46];
	assign monitor_in_map[44] = stim_monitor_in[44];
	assign monitor_in_map[45] = stim_monitor_in[23];
	assign monitor_in_map[46] = stim_monitor_in[20];
	assign monitor_in_map[47] = stim_monitor_in[21];
	assign monitor_in_map[48] = stim_monitor_in[ 6];
	assign monitor_in_map[49] = stim_monitor_in[ 3];
	assign monitor_in_map[50] = stim_monitor_in[ 4];
	assign monitor_in_map[51] = stim_monitor_in[43];
	assign monitor_in_map[52] = stim_monitor_in[ 2];
	assign monitor_in_map[53] = stim_monitor_in[42];
	assign monitor_in_map[54] = stim_monitor_in[14];
	assign monitor_in_map[55] = stim_monitor_in[40];
	assign monitor_in_map[56] = stim_monitor_in[12];
	assign monitor_in_map[57] = stim_monitor_in[41];
	assign monitor_in_map[58] = stim_monitor_in[ 0];
	assign monitor_in_map[59] = stim_monitor_in[ 1];
	assign monitor_in_map[60] = stim_monitor_in[47];
	assign monitor_in_map[61] = stim_monitor_in[45];
	assign monitor_in_map[62] = stim_monitor_in[ 7];
	assign monitor_in_map[63] = stim_monitor_in[ 5];

	assign stim_monitor_rt = monitor_in_map;
	
endmodule