`timescale 1 ns / 1 ps

module eeg_top#
	(
		parameter		CLK_PERIOD			= 10			,

		parameter		CHIPSET_QTY			= 4				,//8
		parameter		CHIPSET_CH_QTY		= 8				,
		parameter		SPIS_QTY			= 2				,//4
		parameter		SPI_SLAVE_QTY		= 2				,

		parameter 		SPI_CLK_DIV			= 3				,
		parameter 		SPI_DATA_WIDTH		= 8			    ,
		parameter		SPI_TRANS_PERIOD	= 2000				//Unit: ns
	)
	(
		input							clk					,
		input							rst_n				,
		
		input	[13-1:0]				bram_addr			,
		input							bram_clk			,
		input	[32-1:0]				bram_din			,
		output	[32-1:0]				bram_dout			,
		input							bram_en				,
		input							bram_rst			,
		input	[ 4-1:0]				bram_we				,
		
		output							interrupt			,
		
		output	[32-1:0]				axis_record_tdata	,
		output							axis_record_tlast	,
		input							axis_record_tready	,
		output							axis_record_tvalid	,
	
		output	[CHIPSET_QTY-1:0]		cs					,
		output	[   SPIS_QTY-1:0]		sclk				,
		output	[   SPIS_QTY-1:0]		mosi				,
		input	[   SPIS_QTY-1:0]		miso				,
		input	[   SPIS_QTY-1:0]		drdy				,
		output	[   SPIS_QTY-1:0]		start				,

		output	[ 4-1:0]				debug_sig
	);
	
	//*****************************************************************************
	// localparam definition
	//*****************************************************************************
	
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	wire	[32-1:0]				eeg_er							;
	wire	[32-1:0]				eeg_cr							;
	wire	[32-1:0]				eeg_sr							;
	wire	[32*SPIS_QTY-1:0]		eeg_tr_array					;
	wire	[32*SPIS_QTY-1:0]		eeg_rr_array					;
	wire							eeg_sr_r_evt					;

	wire	[SPI_SLAVE_QTY-1:0]		cs_w[SPIS_QTY-1:0]				;

	wire							send_enable[SPIS_QTY-1:0]		;
	wire	[ 8-1:0]				send_cs_n[SPIS_QTY-1:0]			;
	wire	[ 8-1:0]				send_length[SPIS_QTY-1:0]		;
	wire	[32-1:0]				send_data_array[SPIS_QTY-1:0]	;
	wire	[32-1:0]				recv_data_array[SPIS_QTY-1:0]	;
	wire							recv_data_en_array[SPIS_QTY-1:0];

	wire	[ 8-1:0]				t_cs_n[SPIS_QTY-1:0]			;
	wire	[ 8-1:0]				t_tdata[SPIS_QTY-1:0]			;
	wire							t_tlast[SPIS_QTY-1:0]			;
	wire							t_tready[SPIS_QTY-1:0]			;
	wire							t_tvalid[SPIS_QTY-1:0]			;

	wire	[ 8-1:0]				r_tdata[SPIS_QTY-1:0]			;
	wire							r_tlast[SPIS_QTY-1:0]			;
	wire							r_tvalid[SPIS_QTY-1:0]			;

	wire							cnv_start[SPIS_QTY-1:0]			;
	wire							cnv_drdy[SPIS_QTY-1:0]			;
	wire							upload_round[SPIS_QTY-1:0]		;
					
	//------------------------------------------ record stream rx
	wire	[32-1:0]				cnv_res_tdata[SPIS_QTY-1:0]		;
	wire							cnv_res_tlast[SPIS_QTY-1:0]		;
	wire							cnv_res_tready[SPIS_QTY-1:0]	;
	wire							cnv_res_tvalid[SPIS_QTY-1:0]	;

	wire	[32*SPIS_QTY-1:0]		cnv_res_tdata_array				;
	wire	[   SPIS_QTY-1:0]		cnv_res_tlast_array				;
	wire	[   SPIS_QTY-1:0]		cnv_res_tready_array			;
	wire	[   SPIS_QTY-1:0]		cnv_res_tvalid_array			;

	wire							record_enable					;

	genvar	i;
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	eeg_config# 
		(
			.SPIS_QTY			( 2						),//4
			.SPI_DATA_WIDTH		( 8						)
		)
	u_eeg_config
		(
			.clk				 ( clk					     ),
			.rst_n				 ( rst_n					 ),
			
			.bram_addr			 ( bram_addr				 ),
			.bram_clk			 ( bram_clk				     ),
			.bram_din			 ( bram_din				     ),
			.bram_dout			 ( bram_dout				 ),
			.bram_en			 ( bram_en				     ),
			.bram_rst			 ( bram_rst				     ),
			.bram_we			 ( bram_we				     ),
			
			//eeg
			.eeg_er				 ( eeg_er				     ),
			.eeg_cr				 ( eeg_cr				     ),
			.eeg_sr				 ( eeg_sr				     ),
			.eeg_tr_array		 ( eeg_tr_array			     ),
			.eeg_rr_array		 ( eeg_rr_array			     ),

			.eeg_sr_r_evt		 ( eeg_sr_r_evt			     )
		);
		
	generate
		for(i=0;i<SPIS_QTY;i=i+1) begin : transmit_arrange
			ads1299_arrange# 
				(
					.CLK_PERIOD				( 10					),
					.SPI_DATA_WIDTH			( 8						),
					.SPI_TRANS_PERIOD		( SPI_TRANS_PERIOD		)
				)
			u_ads1299_arrange
				(
					.clk					( clk					),
					.rst_n					( rst_n					),
					
					.send_cs_n				( send_cs_n[i]			),
					.send_enable			( send_enable[i]		),
					.send_length			( send_length[i]		),
					.send_data_array		( send_data_array[i]	),
					.recv_data_en			( recv_data_en_array[i]	),
					.recv_data_array		( recv_data_array[i]	),

					.t_cs_n					( t_cs_n[i]				),
					.t_tdata				( t_tdata[i] 			),
					.t_tlast				( t_tlast[i] 			),
					.t_tready				( t_tready[i]			),
					.t_tvalid				( t_tvalid[i]			),

					.r_tdata				( r_tdata[i]  			),
					.r_tlast				( r_tlast[i] 			),
					.r_tvalid				( r_tvalid[i]			),
					
					.rdatac_enable			( record_enable			),
					.cnv_start				( cnv_start[i]			),
					.cnv_drdy				( cnv_drdy[0]			),
					.upload_round			( upload_round[i]		)
				);
		end
	endgenerate

	generate
		for(i=0;i<SPIS_QTY;i=i+1) begin : trans_if
			ads1299_if# 
				(
					.SPI_CLK_DIV			( SPI_CLK_DIV			),
					.SPI_DATA_WIDTH			( SPI_DATA_WIDTH		),
					.SPI_SLAVE_QTY			( SPI_SLAVE_QTY			)
				)
			u_ads1299_if
				(
					.clk					( clk					),
					.rst_n					( rst_n					),
					
					.upload_enable			( record_enable			),
					.upload_round			( upload_round[i]		),

					//------------------------------------------ spi direct communication
					.t_cs_n					( t_cs_n[i] 			),
					.t_tdata				( t_tdata[i] 			),
					.t_tlast				( t_tlast[i] 			),
					.t_tready				( t_tready[i]			),
					.t_tvalid				( t_tvalid[i]			),

					.r_tdata				( r_tdata[i]  			),
					.r_tlast				( r_tlast[i] 			),
					.r_tvalid				( r_tvalid[i]			),
					
					//------------------------------------------ record stream rx
					.cnv_res_tdata			( cnv_res_tdata[i]		),
					.cnv_res_tlast			( cnv_res_tlast[i]		),
					.cnv_res_tready			( cnv_res_tready[i]		),
					.cnv_res_tvalid			( cnv_res_tvalid[i]		),
					
					//------------------------------------------ device spi
					.cs						( cs_w[i]				),
					.sclk					( sclk[i]				),
					.mosi					( mosi[i]				),
					.miso					( miso[i]				)
				);
		end
	endgenerate
		
	eeg_upload# 
		(
			.CLK_PERIOD				( CLK_PERIOD			),
			.CHIPSET_QTY			( SPIS_QTY				),
			.CH_OF_CHIPSET			( CHIPSET_CH_QTY*SPI_SLAVE_QTY	)
		)
	u_eeg_upload
		(
			.clk					( clk					),
			.rst_n					( rst_n					),

			.trans_round			( upload_round[0]		),
			
			.cnv_res_tdata_array	( cnv_res_tdata_array	),
			.cnv_res_tlast_array	( cnv_res_tlast_array	),
			.cnv_res_tready_array	( cnv_res_tready_array	),
			.cnv_res_tvalid_array	( cnv_res_tvalid_array	),
			
			.axi_str_rxd_tdata		( axis_record_tdata		),
			.axi_str_rxd_tlast		( axis_record_tlast		),
			.axi_str_rxd_tready		( axis_record_tready	),
			.axi_str_rxd_tvalid		( axis_record_tvalid	)
		);
	
	//*****************************************************************************
	// Procedural blocks
	//*****************************************************************************
	
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	assign record_enable = eeg_cr[31];

	assign start = {cnv_start[0],cnv_start[0]};

	generate
		for(i=0;i<SPIS_QTY;i=i+1) begin : mapping
			assign send_enable[i] 	= eeg_er[i];

			assign send_cs_n[i] 	= {6'd0, eeg_cr[4*i+1:4*i+0]};
			assign send_length[i] 	= {6'd0, eeg_cr[4*i+3:4*i+2]};

			assign send_data_array[i] = eeg_tr_array[32*i+31:32*i];
			assign eeg_rr_array[32*i+31:32*i] = recv_data_array[i];

			assign cs[SPI_SLAVE_QTY*(i+1)-1 : SPI_SLAVE_QTY*i] = cs_w[i];
			assign cnv_drdy[i] = drdy[i];
			
			assign cnv_res_tdata_array[32*i+31 : 32*i] 	= cnv_res_tdata[i];
			assign cnv_res_tlast_array[i]				= cnv_res_tlast[i];
			assign cnv_res_tvalid_array[i]				= cnv_res_tvalid[i];
			assign cnv_res_tready[i] = cnv_res_tready_array[i];
		end
	endgenerate

	assign interrupt = 1'b0;

	assign debug_sig[0] = record_enable;
	assign debug_sig[1] = 1'b0;
	assign debug_sig[2] = 1'b0;
	assign debug_sig[3] = 1'b0;
	
endmodule