# Details

Date : 2024-03-26 15:29:43

Directory d:\\projects\\vivadoPrj\\c64_pro\\c64_pro.srcs\\sources_1\\rtl

Total : 55 files,  8710 codes, 1239 comments, 1945 blanks, all 11894 lines

[Summary](results.md) / Details / [Diff Summary](diff.md) / [Diff Details](diff-details.md)

## Files
| filename | language | code | comment | blank | total |
| :--- | :--- | ---: | ---: | ---: | ---: |
| [accel/accel_top.v](/accel/accel_top.v) | Verilog | 117 | 13 | 36 | 166 |
| [accel/lis2dw12.v](/accel/lis2dw12.v) | Verilog | 197 | 10 | 31 | 238 |
| [c64pro_top.v](/c64pro_top.v) | Verilog | 364 | 44 | 78 | 486 |
| [eeg/ads1299_arrange.v](/eeg/ads1299_arrange.v) | Verilog | 195 | 16 | 31 | 242 |
| [eeg/ads1299_if.v](/eeg/ads1299_if.v) | Verilog | 149 | 18 | 27 | 194 |
| [eeg/ads1299_mod.v](/eeg/ads1299_mod.v) | Verilog | 113 | 13 | 29 | 155 |
| [eeg/ads1299_spi - backup.v](/eeg/ads1299_spi%20-%20backup.v) | Verilog | 186 | 12 | 29 | 227 |
| [eeg/ads1299_spi.v](/eeg/ads1299_spi.v) | Verilog | 218 | 10 | 35 | 263 |
| [eeg/ads1299_spi_tb.v](/eeg/ads1299_spi_tb.v) | Verilog | 79 | 16 | 21 | 116 |
| [eeg/eeg_config.v](/eeg/eeg_config.v) | Verilog | 118 | 16 | 32 | 166 |
| [eeg/eeg_top.v](/eeg/eeg_top.v) | Verilog | 204 | 21 | 52 | 277 |
| [eeg/eeg_top_tb.v](/eeg/eeg_top_tb.v) | Verilog | 158 | 88 | 40 | 286 |
| [eeg/eeg_upload.v](/eeg/eeg_upload.v) | Verilog | 147 | 13 | 29 | 189 |
| [emg/emg_config.v](/emg/emg_config.v) | Verilog | 81 | 14 | 25 | 120 |
| [emg/emg_top.v](/emg/emg_top.v) | Verilog | 44 | 17 | 17 | 78 |
| [led_ctrl.v](/led_ctrl.v) | Verilog | 58 | 10 | 12 | 80 |
| [led_ctrl_tb.v](/led_ctrl_tb.v) | Verilog | 34 | 19 | 17 | 70 |
| [pl_top.v](/pl_top.v) | Verilog | 320 | 35 | 70 | 425 |
| [pl_top_tb.v](/pl_top_tb.v) | Verilog | 505 | 77 | 116 | 698 |
| [rhs2116/cnv_res_collect.v](/rhs2116/cnv_res_collect.v) | Verilog | 180 | 14 | 30 | 224 |
| [rhs2116/cnv_res_collect_tb.v](/rhs2116/cnv_res_collect_tb.v) | Verilog | 119 | 20 | 33 | 172 |
| [rhs2116/dds_stim_16ch_tb.v](/rhs2116/dds_stim_16ch_tb.v) | Verilog | 74 | 16 | 21 | 111 |
| [rhs2116/dds_stim_16ch_tb.vhd](/rhs2116/dds_stim_16ch_tb.vhd) | VHDL | 307 | 135 | 49 | 491 |
| [rhs2116/rhs2116_mod.v](/rhs2116/rhs2116_mod.v) | Verilog | 84 | 7 | 19 | 110 |
| [rhs2116/rhs2116_top.v](/rhs2116/rhs2116_top.v) | Verilog | 337 | 27 | 86 | 450 |
| [rhs2116/rhs2116_top_tb.v](/rhs2116/rhs2116_top_tb.v) | Verilog | 367 | 26 | 83 | 476 |
| [rhs2116/sine_gen.v](/rhs2116/sine_gen.v) | Verilog | 154 | 22 | 31 | 207 |
| [rhs2116/sine_gen_tb.v](/rhs2116/sine_gen_tb.v) | Verilog | 129 | 18 | 42 | 189 |
| [rhs2116/stim_event_collect.v](/rhs2116/stim_event_collect.v) | Verilog | 74 | 10 | 14 | 98 |
| [rhs2116/stim_monitor.v](/rhs2116/stim_monitor.v) | Verilog | 105 | 13 | 14 | 132 |
| [rhs2116/trans_arrange.v](/rhs2116/trans_arrange.v) | Verilog | 174 | 18 | 31 | 223 |
| [rhs2116/trans_arrange_tb.v](/rhs2116/trans_arrange_tb.v) | Verilog | 268 | 19 | 62 | 349 |
| [rhs2116/trans_distribute.v](/rhs2116/trans_distribute.v) | Verilog | 120 | 13 | 26 | 159 |
| [rhs2116/trans_distribute_tb.v](/rhs2116/trans_distribute_tb.v) | Verilog | 114 | 16 | 24 | 154 |
| [rhs2116/trans_timer.v](/rhs2116/trans_timer.v) | Verilog | 60 | 10 | 15 | 85 |
| [rhs2116/trans_timer_tb.v](/rhs2116/trans_timer_tb.v) | Verilog | 55 | 15 | 19 | 89 |
| [rhs2116/transmit_config.v](/rhs2116/transmit_config.v) | Verilog | 351 | 82 | 74 | 507 |
| [rhs2116/transmit_config_tb.v](/rhs2116/transmit_config_tb.v) | Verilog | 321 | 36 | 101 | 458 |
| [rhs2116/transmit_if.v](/rhs2116/transmit_if.v) | Verilog | 268 | 25 | 46 | 339 |
| [rhs2116/transmit_if_tb.v](/rhs2116/transmit_if_tb.v) | Verilog | 172 | 39 | 58 | 269 |
| [switch/adg1414_if.v](/switch/adg1414_if.v) | Verilog | 136 | 13 | 25 | 174 |
| [switch/adg1414_if_tb.v](/switch/adg1414_if_tb.v) | Verilog | 56 | 15 | 17 | 88 |
| [switch/channel_switch.v](/switch/channel_switch.v) | Verilog | 169 | 25 | 30 | 224 |
| [switch/channel_switch_tb.v](/switch/channel_switch_tb.v) | Verilog | 52 | 16 | 17 | 85 |
| [trigger/trigger_detection.v](/trigger/trigger_detection.v) | Verilog | 21 | 1 | 7 | 29 |
| [trigger/trigger_top.v](/trigger/trigger_top.v) | Verilog | 137 | 15 | 32 | 184 |
| [trigger/trigger_top_tb.v](/trigger/trigger_top_tb.v) | Verilog | 45 | 15 | 16 | 76 |
| [upload/upload_config.v](/upload/upload_config.v) | Verilog | 96 | 14 | 29 | 139 |
| [upload/upload_sort.v](/upload/upload_sort.v) | Verilog | 141 | 12 | 27 | 180 |
| [upload/upload_top.v](/upload/upload_top.v) | Verilog | 254 | 15 | 45 | 314 |
| [utils/breath_gen.v](/utils/breath_gen.v) | Verilog | 123 | 13 | 25 | 161 |
| [utils/debouncing.v](/utils/debouncing.v) | Verilog | 93 | 10 | 15 | 118 |
| [utils/pwm_gen.v](/utils/pwm_gen.v) | Verilog | 40 | 4 | 9 | 53 |
| [utils/spi_full_duplex_master.v](/utils/spi_full_duplex_master.v) | Verilog | 148 | 12 | 25 | 185 |
| [utils/spi_full_duplex_master_tb.v](/utils/spi_full_duplex_master_tb.v) | Verilog | 79 | 16 | 21 | 116 |

[Summary](results.md) / Details / [Diff Summary](diff.md) / [Diff Details](diff-details.md)