Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 | Date : Fri Sep 4 15:41:15 2026 | Host : DESKTOP-VN054CM running 64-bit major release (build 9200) | Command : report_methodology -file c64pro_top_methodology_drc_routed.rpt -pb c64pro_top_methodology_drc_routed.pb -rpx c64pro_top_methodology_drc_routed.rpx | Design : c64pro_top | Device : xc7z020clg400-2 | Speed File : -2 | Design State : Fully Routed -------------------------------------------------------------------------------------------------------------------------------------------------------------------- Report Methodology Table of Contents ----------------- 1. REPORT SUMMARY 2. REPORT DETAILS 1. REPORT SUMMARY ----------------- Netlist: netlist Floorplan: design_1 Design limits: Max violations: Violations found: 97 +-----------+----------+-------------------------------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+----------+-------------------------------------------------+------------+ | LUTAR-1 | Warning | LUT drives async reset alert | 4 | | PDRC-190 | Warning | Suboptimally placed synchronized register chain | 13 | | TIMING-18 | Warning | Missing input or output delay | 79 | | ULMTCS-1 | Warning | Control Sets use limits recommend reduction | 1 | +-----------+----------+-------------------------------------------------+------------+ 2. REPORT DETAILS ----------------- LUTAR-1#1 Warning LUT drives async reset alert LUT cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst/ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/PRE, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/PRE dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#2 Warning LUT drives async reset alert LUT cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst/ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/PRE, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/PRE dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#3 Warning LUT drives async reset alert LUT cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst/ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/PRE, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/PRE dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#4 Warning LUT drives async reset alert LUT cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst/ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/PRE, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/PRE dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: PDRC-190#1 Warning Suboptimally placed synchronized register chain The FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0] in site SLICE_X111Y57 is part of a synchronized register chain that is suboptimally placed as the load FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0] is not placed in the same (SLICE) site. Related violations: PDRC-190#2 Warning Suboptimally placed synchronized register chain The FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1] in site SLICE_X113Y53 is part of a synchronized register chain that is suboptimally placed as the load FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1] is not placed in the same (SLICE) site. Related violations: PDRC-190#3 Warning Suboptimally placed synchronized register chain The FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[2] in site SLICE_X112Y55 is part of a synchronized register chain that is suboptimally placed as the load FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[2] is not placed in the same (SLICE) site. Related violations: PDRC-190#4 Warning Suboptimally placed synchronized register chain The FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3] in site SLICE_X110Y53 is part of a synchronized register chain that is suboptimally placed as the load FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3] is not placed in the same (SLICE) site. Related violations: PDRC-190#5 Warning Suboptimally placed synchronized register chain The FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0] in site SLICE_X109Y52 is part of a synchronized register chain that is suboptimally placed as the load FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0] is not placed in the same (SLICE) site. Related violations: PDRC-190#6 Warning Suboptimally placed synchronized register chain The FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1] in site SLICE_X111Y55 is part of a synchronized register chain that is suboptimally placed as the load FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1] is not placed in the same (SLICE) site. Related violations: PDRC-190#7 Warning Suboptimally placed synchronized register chain The FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2] in site SLICE_X108Y52 is part of a synchronized register chain that is suboptimally placed as the load FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2] is not placed in the same (SLICE) site. Related violations: PDRC-190#8 Warning Suboptimally placed synchronized register chain The FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[3] in site SLICE_X110Y55 is part of a synchronized register chain that is suboptimally placed as the load FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[3] is not placed in the same (SLICE) site. Related violations: PDRC-190#9 Warning Suboptimally placed synchronized register chain The FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0] in site SLICE_X110Y58 is part of a synchronized register chain that is suboptimally placed as the load FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0] is not placed in the same (SLICE) site. Related violations: PDRC-190#10 Warning Suboptimally placed synchronized register chain The FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1] in site SLICE_X108Y56 is part of a synchronized register chain that is suboptimally placed as the load FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1] is not placed in the same (SLICE) site. Related violations: PDRC-190#11 Warning Suboptimally placed synchronized register chain The FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2] in site SLICE_X109Y56 is part of a synchronized register chain that is suboptimally placed as the load FDRE cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2] is not placed in the same (SLICE) site. Related violations: PDRC-190#12 Warning Suboptimally placed synchronized register chain The FDRE cell u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg in site SLICE_X58Y118 is part of a synchronized register chain that is suboptimally placed as the load FDSE cell u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg is not placed in the same (SLICE) site. Related violations: PDRC-190#13 Warning Suboptimally placed synchronized register chain The FDRE cell u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg in site SLICE_X26Y18 is part of a synchronized register chain that is suboptimally placed as the load FDSE cell u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg is not placed in the same (SLICE) site. Related violations: TIMING-18#1 Warning Missing input or output delay An input delay is missing on ad7689_spi_miso relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#2 Warning Missing input or output delay An input delay is missing on ad7689_spi_mosi relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#3 Warning Missing input or output delay An input delay is missing on chann_en[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#4 Warning Missing input or output delay An input delay is missing on chann_en[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#5 Warning Missing input or output delay An input delay is missing on chann_sel[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#6 Warning Missing input or output delay An input delay is missing on chann_sel[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#7 Warning Missing input or output delay An input delay is missing on chann_sel[2] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#8 Warning Missing input or output delay An input delay is missing on chann_sel[3] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#9 Warning Missing input or output delay An input delay is missing on eeg_ads1299_drdy_n[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#10 Warning Missing input or output delay An input delay is missing on eeg_ads1299_drdy_n[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#11 Warning Missing input or output delay An input delay is missing on eeg_ads1299_spi_miso[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#12 Warning Missing input or output delay An input delay is missing on eeg_ads1299_spi_miso[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#13 Warning Missing input or output delay An input delay is missing on elec_mux_in[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#14 Warning Missing input or output delay An input delay is missing on elec_mux_in[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#15 Warning Missing input or output delay An input delay is missing on elec_mux_in[2] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#16 Warning Missing input or output delay An input delay is missing on elec_mux_in[3] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#17 Warning Missing input or output delay An input delay is missing on emg_ads1299_drdy_n relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#18 Warning Missing input or output delay An input delay is missing on emg_ads1299_spi_miso relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#19 Warning Missing input or output delay An input delay is missing on gpio[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#20 Warning Missing input or output delay An input delay is missing on gpio[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#21 Warning Missing input or output delay An input delay is missing on gpio[2] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#22 Warning Missing input or output delay An input delay is missing on rst_ad5941 relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#23 Warning Missing input or output delay An input delay is missing on stim_spi_miso relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#24 Warning Missing input or output delay An input delay is missing on stim_spi_mosi relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#25 Warning Missing input or output delay An input delay is missing on z_io relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#26 Warning Missing input or output delay An input delay is missing on zcheck_spi_miso relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#27 Warning Missing input or output delay An input delay is missing on zcheck_spi_mosi relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#28 Warning Missing input or output delay An output delay is missing on ad7689_cnv relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#29 Warning Missing input or output delay An output delay is missing on ad7689_spi_miso relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#30 Warning Missing input or output delay An output delay is missing on ad7689_spi_mosi relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#31 Warning Missing input or output delay An output delay is missing on ad7689_spi_sclk relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#32 Warning Missing input or output delay An output delay is missing on chann_en[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#33 Warning Missing input or output delay An output delay is missing on chann_en[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#34 Warning Missing input or output delay An output delay is missing on chann_sel[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#35 Warning Missing input or output delay An output delay is missing on chann_sel[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#36 Warning Missing input or output delay An output delay is missing on chann_sel[2] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#37 Warning Missing input or output delay An output delay is missing on chann_sel[3] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#38 Warning Missing input or output delay An output delay is missing on eeg_ads1299_spi_cs[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#39 Warning Missing input or output delay An output delay is missing on eeg_ads1299_spi_cs[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#40 Warning Missing input or output delay An output delay is missing on eeg_ads1299_spi_cs[2] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#41 Warning Missing input or output delay An output delay is missing on eeg_ads1299_spi_cs[3] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#42 Warning Missing input or output delay An output delay is missing on eeg_ads1299_spi_mosi[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#43 Warning Missing input or output delay An output delay is missing on eeg_ads1299_spi_mosi[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#44 Warning Missing input or output delay An output delay is missing on eeg_ads1299_spi_sclk[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#45 Warning Missing input or output delay An output delay is missing on eeg_ads1299_spi_sclk[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#46 Warning Missing input or output delay An output delay is missing on eeg_ads1299_start[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#47 Warning Missing input or output delay An output delay is missing on eeg_ads1299_start[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#48 Warning Missing input or output delay An output delay is missing on elec_mux_in[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#49 Warning Missing input or output delay An output delay is missing on elec_mux_in[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#50 Warning Missing input or output delay An output delay is missing on elec_mux_in[2] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#51 Warning Missing input or output delay An output delay is missing on elec_mux_in[3] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#52 Warning Missing input or output delay An output delay is missing on emg_ads1299_spi_cs relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#53 Warning Missing input or output delay An output delay is missing on emg_ads1299_spi_mosi relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#54 Warning Missing input or output delay An output delay is missing on emg_ads1299_spi_sclk relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#55 Warning Missing input or output delay An output delay is missing on emg_ads1299_start relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#56 Warning Missing input or output delay An output delay is missing on gpio[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#57 Warning Missing input or output delay An output delay is missing on gpio[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#58 Warning Missing input or output delay An output delay is missing on gpio[2] relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#59 Warning Missing input or output delay An output delay is missing on led_rsv relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#60 Warning Missing input or output delay An output delay is missing on led_state relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#61 Warning Missing input or output delay An output delay is missing on led_stim relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#62 Warning Missing input or output delay An output delay is missing on led_usb relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#63 Warning Missing input or output delay An output delay is missing on mux_pwr_en relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#64 Warning Missing input or output delay An output delay is missing on pudc relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#65 Warning Missing input or output delay An output delay is missing on rec_pwr_en relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#66 Warning Missing input or output delay An output delay is missing on ref_sw relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#67 Warning Missing input or output delay An output delay is missing on ref_sw_en relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#68 Warning Missing input or output delay An output delay is missing on rst_ad5941 relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#69 Warning Missing input or output delay An output delay is missing on stim_clk400k relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#70 Warning Missing input or output delay An output delay is missing on stim_pwr_en relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#71 Warning Missing input or output delay An output delay is missing on stim_spi_cs relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#72 Warning Missing input or output delay An output delay is missing on stim_spi_miso relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#73 Warning Missing input or output delay An output delay is missing on stim_spi_mosi relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#74 Warning Missing input or output delay An output delay is missing on stim_spi_sclk relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#75 Warning Missing input or output delay An output delay is missing on z_io relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#76 Warning Missing input or output delay An output delay is missing on zcheck_spi_cs relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#77 Warning Missing input or output delay An output delay is missing on zcheck_spi_miso relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#78 Warning Missing input or output delay An output delay is missing on zcheck_spi_mosi relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: TIMING-18#79 Warning Missing input or output delay An output delay is missing on zcheck_spi_sclk relative to the rising and/or falling clock edge(s) of clk_fpga_0. Related violations: ULMTCS-1#1 Warning Control Sets use limits recommend reduction This design uses 1907 control sets (vs. available limit of 13300, determined by 1 control set per CLB). This exceeds the control set use guideline of 7.5 percent. This is at a level where reduction is RECOMMENDED (see UG949). Use report_control_sets to get more details. Related violations: