*** Running vivado with args -log fifo_generator_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_generator_0.tcl ****** Vivado v2023.1 (64-bit) **** SW Build 3865809 on Sun May 7 15:05:29 MDT 2023 **** IP Build 3864474 on Sun May 7 20:36:21 MDT 2023 **** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source fifo_generator_0.tcl -notrace create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1467.941 ; gain = 161.305 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: fifo_generator_0 Command: synth_design -top fifo_generator_0 -part xc7z020clg400-2 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Device 21-403] Loading part xc7z020clg400-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 34276 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 2323.387 ; gain = 409.086 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'fifo_generator_0' [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/fifo_generator_0/synth/fifo_generator_0.vhd:75] Parameter C_COMMON_CLOCK bound to: 0 - type: integer Parameter C_SELECT_XPM bound to: 0 - type: integer Parameter C_COUNT_TYPE bound to: 0 - type: integer Parameter C_DATA_COUNT_WIDTH bound to: 13 - type: integer Parameter C_DEFAULT_VALUE bound to: BlankString - type: string Parameter C_DIN_WIDTH bound to: 9 - type: integer Parameter C_DOUT_RST_VAL bound to: 0 - type: string Parameter C_DOUT_WIDTH bound to: 9 - type: integer Parameter C_ENABLE_RLOCS bound to: 0 - type: integer Parameter C_FAMILY bound to: zynq - type: string Parameter C_FULL_FLAGS_RST_VAL bound to: 1 - type: integer Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer Parameter C_HAS_BACKUP bound to: 0 - type: integer Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_INT_CLK bound to: 0 - type: integer Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer Parameter C_HAS_OVERFLOW bound to: 0 - type: integer Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_RD_RST bound to: 0 - type: integer Parameter C_HAS_RST bound to: 1 - type: integer Parameter C_HAS_SRST bound to: 0 - type: integer Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer Parameter C_HAS_VALID bound to: 0 - type: integer Parameter C_HAS_WR_ACK bound to: 0 - type: integer Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_WR_RST bound to: 0 - type: integer Parameter C_IMPLEMENTATION_TYPE bound to: 2 - type: integer Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer Parameter C_MEMORY_TYPE bound to: 1 - type: integer Parameter C_MIF_FILE_NAME bound to: BlankString - type: string Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer Parameter C_OVERFLOW_LOW bound to: 0 - type: integer Parameter C_PRELOAD_LATENCY bound to: 1 - type: integer Parameter C_PRELOAD_REGS bound to: 0 - type: integer Parameter C_PRIM_FIFO_TYPE bound to: 8kx4 - type: string Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 2 - type: integer Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 3 - type: integer Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 8189 - type: integer Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 8188 - type: integer Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer Parameter C_RD_DATA_COUNT_WIDTH bound to: 13 - type: integer Parameter C_RD_DEPTH bound to: 8192 - type: integer Parameter C_RD_FREQ bound to: 1 - type: integer Parameter C_RD_PNTR_WIDTH bound to: 13 - type: integer Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer Parameter C_USE_DOUT_RST bound to: 1 - type: integer Parameter C_USE_ECC bound to: 0 - type: integer Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer Parameter C_VALID_LOW bound to: 0 - type: integer Parameter C_WR_ACK_LOW bound to: 0 - type: integer Parameter C_WR_DATA_COUNT_WIDTH bound to: 13 - type: integer Parameter C_WR_DEPTH bound to: 8192 - type: integer Parameter C_WR_FREQ bound to: 1 - type: integer Parameter C_WR_PNTR_WIDTH bound to: 13 - type: integer Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer Parameter C_MSGON_VAL bound to: 1 - type: integer Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer Parameter C_EN_SAFETY_CKT bound to: 1 - type: integer Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer Parameter C_INTERFACE_TYPE bound to: 0 - type: integer Parameter C_AXI_TYPE bound to: 1 - type: integer Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer Parameter C_HAS_MASTER_CE bound to: 0 - type: integer Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer Parameter C_HAS_AXI_ID bound to: 0 - type: integer Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer Parameter C_HAS_AXIS_TID bound to: 0 - type: integer Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer Parameter C_WACH_TYPE bound to: 0 - type: integer Parameter C_WDCH_TYPE bound to: 0 - type: integer Parameter C_WRCH_TYPE bound to: 0 - type: integer Parameter C_RACH_TYPE bound to: 0 - type: integer Parameter C_RDCH_TYPE bound to: 0 - type: integer Parameter C_AXIS_TYPE bound to: 0 - type: integer Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string Parameter C_USE_ECC_WACH bound to: 0 - type: integer Parameter C_USE_ECC_WDCH bound to: 0 - type: integer Parameter C_USE_ECC_WRCH bound to: 0 - type: integer Parameter C_USE_ECC_RACH bound to: 0 - type: integer Parameter C_USE_ECC_RDCH bound to: 0 - type: integer Parameter C_USE_ECC_AXIS bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer INFO: [Synth 8-3491] module 'fifo_generator_v13_2_8' declared at 'd:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/fifo_generator_0/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38604' bound to instance 'U0' of component 'fifo_generator_v13_2_8' [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/fifo_generator_0/synth/fifo_generator_0.vhd:545] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1058] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (0#1) [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1058] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (0#1) [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (0#1) [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-256] done synthesizing module 'fifo_generator_0' (0#1) [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/fifo_generator_0/synth/fifo_generator_0.vhd:75] WARNING: [Synth 8-7129] Port ALMOST_FULL_I in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_I in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port ALMOST_EMPTY_I in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_EMPTY_I in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_ACK_I in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port VALID_I in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port OVERFLOW_I in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port UNDERFLOW_I in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[13] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[12] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[11] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[10] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[9] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[8] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[7] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[6] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[5] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[4] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[3] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[2] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[1] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DATA_COUNT_I[0] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[13] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[12] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[11] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[10] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[9] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[8] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[7] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[6] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[5] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[4] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[3] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[2] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[1] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[0] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[13] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[12] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[11] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[10] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[9] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[8] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[7] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[6] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[5] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[4] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[3] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[2] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[1] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[0] in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port SBITERR_I in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port DBITERR_I in module output_blk is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_RST in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port RST_FULL_FF in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port SAFETY_CKT_WR_RST in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[12] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[11] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[10] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[9] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[8] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[7] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[6] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[5] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[4] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[3] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[2] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[1] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[0] in module wr_status_flags_as is either unconnected or has no load WARNING: [Synth 8-7129] Port RST in module wr_bin_cntr is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_EN_INTO_LOGIC in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_RST_INTO_LOGIC in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port RD_EN in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port SRST_FULL_FF in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port WR_RST_BUSY in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port EMPTY in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port RAM_RD_EN in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port ALMOST_EMPTY in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[12] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[11] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[10] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[9] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[8] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[7] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[6] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[5] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[4] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[3] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[2] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[1] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[0] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[12] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[11] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[10] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[9] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[8] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[7] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[6] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[5] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[4] in module wr_logic is either unconnected or has no load WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[3] in module wr_logic is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:39 ; elapsed = 00:00:49 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 2673.344 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 30 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_ooc.xdc] for cell 'U0' Finished Parsing XDC File [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_ooc.xdc] for cell 'U0' Parsing XDC File [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'U0' Finished Parsing XDC File [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'U0' Parsing XDC File [D:/Project/A64/pl/a64_v0/c64_pro.runs/fifo_generator_0_synth_1/dont_touch.xdc] Finished Parsing XDC File [D:/Project/A64/pl/a64_v0/c64_pro.runs/fifo_generator_0_synth_1/dont_touch.xdc] Parsing XDC File [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'U0' Finished Parsing XDC File [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'U0' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_generator_0_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_generator_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_generator_0_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_generator_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-1714] 6 XPM XDC files have been applied to the design. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2673.344 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.076 . Memory (MB): peak = 2673.344 ; gain = 0.000 INFO: [Designutils 20-5008] Incremental synthesis strategy off --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:54 ; elapsed = 00:01:07 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:54 ; elapsed = 00:01:07 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file D:/Project/A64/pl/a64_v0/c64_pro.runs/fifo_generator_0_synth_1/dont_touch.xdc, line 9). Applied set_property KEEP_HIERARCHY = SOFT for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst . (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:54 ; elapsed = 00:01:07 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:55 ; elapsed = 00:01:08 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 2 2 Input 1 Bit XORs := 80 +---Registers : 13 Bit Registers := 11 5 Bit Registers := 8 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 29 +---Muxes : 2 Input 9 Bit Muxes := 2 2 Input 1 Bit Muxes := 7 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:58 ; elapsed = 00:01:12 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:07 ; elapsed = 00:01:22 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:07 ; elapsed = 00:01:22 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:01:08 ; elapsed = 00:01:22 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:01:16 ; elapsed = 00:01:30 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:01:16 ; elapsed = 00:01:30 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:16 ; elapsed = 00:01:30 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:01:16 ; elapsed = 00:01:30 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:01:16 ; elapsed = 00:01:30 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:01:16 ; elapsed = 00:01:30 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |fifo_generator_v13_2_8 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[4] | 4 | 2 | NO | NO | YES | 2 | 0 | +-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |CARRY4 | 8| |2 |LUT1 | 15| |3 |LUT2 | 40| |4 |LUT3 | 16| |5 |LUT4 | 32| |6 |LUT5 | 8| |7 |LUT6 | 5| |8 |MUXCY | 28| |9 |RAMB36E1 | 2| |10 |SRL16E | 2| |11 |FDRE | 209| |12 |FDSE | 8| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:01:16 ; elapsed = 00:01:30 . Memory (MB): peak = 2673.344 ; gain = 759.043 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 494 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:32 ; elapsed = 00:01:25 . Memory (MB): peak = 2673.344 ; gain = 759.043 Synthesis Optimization Complete : Time (s): cpu = 00:01:16 ; elapsed = 00:01:31 . Memory (MB): peak = 2673.344 ; gain = 759.043 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 2673.344 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 38 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2673.344 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 8 instances were transformed. (MUXCY,XORCY) => CARRY4: 8 instances Synth Design complete | Checksum: bb3f1412 INFO: [Common 17-83] Releasing license: Synthesis 31 Infos, 101 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:24 ; elapsed = 00:01:42 . Memory (MB): peak = 2673.344 ; gain = 1165.836 INFO: [Common 17-1381] The checkpoint 'D:/Project/A64/pl/a64_v0/c64_pro.runs/fifo_generator_0_synth_1/fifo_generator_0.dcp' has been generated. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP fifo_generator_0, cache-ID = 10365997fb02e097 INFO: [Coretcl 2-1174] Renamed 32 cell refs. INFO: [Common 17-1381] The checkpoint 'D:/Project/A64/pl/a64_v0/c64_pro.runs/fifo_generator_0_synth_1/fifo_generator_0.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file fifo_generator_0_utilization_synth.rpt -pb fifo_generator_0_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Oct 28 21:01:29 2025...