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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEELABORATESCRC">580d1a4f</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">69808f5bed507761</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">design_a9_1_smartconnect_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">9a15d5e9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">243</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
+127278
File diff suppressed because one or more lines are too long
+148959
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,145 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Jul 2 17:38:31 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_smartconnect_0_0_stub.v
|
||||
// Design : design_a9_1_smartconnect_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "bd_962a,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, S00_AXI_araddr, S00_AXI_arlen,
|
||||
S00_AXI_arsize, S00_AXI_arburst, S00_AXI_arlock, S00_AXI_arcache, S00_AXI_arprot,
|
||||
S00_AXI_arqos, S00_AXI_arvalid, S00_AXI_arready, S00_AXI_rdata, S00_AXI_rresp,
|
||||
S00_AXI_rlast, S00_AXI_rvalid, S00_AXI_rready, S01_AXI_awaddr, S01_AXI_awlen,
|
||||
S01_AXI_awsize, S01_AXI_awburst, S01_AXI_awlock, S01_AXI_awcache, S01_AXI_awprot,
|
||||
S01_AXI_awqos, S01_AXI_awvalid, S01_AXI_awready, S01_AXI_wdata, S01_AXI_wstrb,
|
||||
S01_AXI_wlast, S01_AXI_wvalid, S01_AXI_wready, S01_AXI_bresp, S01_AXI_bvalid,
|
||||
S01_AXI_bready, S02_AXI_awaddr, S02_AXI_awlen, S02_AXI_awsize, S02_AXI_awburst,
|
||||
S02_AXI_awlock, S02_AXI_awcache, S02_AXI_awprot, S02_AXI_awqos, S02_AXI_awvalid,
|
||||
S02_AXI_awready, S02_AXI_wdata, S02_AXI_wstrb, S02_AXI_wlast, S02_AXI_wvalid,
|
||||
S02_AXI_wready, S02_AXI_bresp, S02_AXI_bvalid, S02_AXI_bready, S03_AXI_awaddr,
|
||||
S03_AXI_awlen, S03_AXI_awsize, S03_AXI_awburst, S03_AXI_awlock, S03_AXI_awcache,
|
||||
S03_AXI_awprot, S03_AXI_awqos, S03_AXI_awvalid, S03_AXI_awready, S03_AXI_wdata,
|
||||
S03_AXI_wstrb, S03_AXI_wlast, S03_AXI_wvalid, S03_AXI_wready, S03_AXI_bresp,
|
||||
S03_AXI_bvalid, S03_AXI_bready, M00_AXI_awaddr, M00_AXI_awlen, M00_AXI_awsize,
|
||||
M00_AXI_awburst, M00_AXI_awlock, M00_AXI_awcache, M00_AXI_awprot, M00_AXI_awqos,
|
||||
M00_AXI_awvalid, M00_AXI_awready, M00_AXI_wdata, M00_AXI_wstrb, M00_AXI_wlast,
|
||||
M00_AXI_wvalid, M00_AXI_wready, M00_AXI_bresp, M00_AXI_bvalid, M00_AXI_bready,
|
||||
M00_AXI_araddr, M00_AXI_arlen, M00_AXI_arsize, M00_AXI_arburst, M00_AXI_arlock,
|
||||
M00_AXI_arcache, M00_AXI_arprot, M00_AXI_arqos, M00_AXI_arvalid, M00_AXI_arready,
|
||||
M00_AXI_rdata, M00_AXI_rresp, M00_AXI_rlast, M00_AXI_rvalid, M00_AXI_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aresetn,S00_AXI_araddr[31:0],S00_AXI_arlen[7:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[0:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rdata[31:0],S00_AXI_rresp[1:0],S00_AXI_rlast,S00_AXI_rvalid,S00_AXI_rready,S01_AXI_awaddr[31:0],S01_AXI_awlen[7:0],S01_AXI_awsize[2:0],S01_AXI_awburst[1:0],S01_AXI_awlock[0:0],S01_AXI_awcache[3:0],S01_AXI_awprot[2:0],S01_AXI_awqos[3:0],S01_AXI_awvalid,S01_AXI_awready,S01_AXI_wdata[31:0],S01_AXI_wstrb[3:0],S01_AXI_wlast,S01_AXI_wvalid,S01_AXI_wready,S01_AXI_bresp[1:0],S01_AXI_bvalid,S01_AXI_bready,S02_AXI_awaddr[31:0],S02_AXI_awlen[7:0],S02_AXI_awsize[2:0],S02_AXI_awburst[1:0],S02_AXI_awlock[0:0],S02_AXI_awcache[3:0],S02_AXI_awprot[2:0],S02_AXI_awqos[3:0],S02_AXI_awvalid,S02_AXI_awready,S02_AXI_wdata[31:0],S02_AXI_wstrb[3:0],S02_AXI_wlast,S02_AXI_wvalid,S02_AXI_wready,S02_AXI_bresp[1:0],S02_AXI_bvalid,S02_AXI_bready,S03_AXI_awaddr[31:0],S03_AXI_awlen[7:0],S03_AXI_awsize[2:0],S03_AXI_awburst[1:0],S03_AXI_awlock[0:0],S03_AXI_awcache[3:0],S03_AXI_awprot[2:0],S03_AXI_awqos[3:0],S03_AXI_awvalid,S03_AXI_awready,S03_AXI_wdata[31:0],S03_AXI_wstrb[3:0],S03_AXI_wlast,S03_AXI_wvalid,S03_AXI_wready,S03_AXI_bresp[1:0],S03_AXI_bvalid,S03_AXI_bready,M00_AXI_awaddr[31:0],M00_AXI_awlen[3:0],M00_AXI_awsize[2:0],M00_AXI_awburst[1:0],M00_AXI_awlock[1:0],M00_AXI_awcache[3:0],M00_AXI_awprot[2:0],M00_AXI_awqos[3:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wlast,M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[31:0],M00_AXI_arlen[3:0],M00_AXI_arsize[2:0],M00_AXI_arburst[1:0],M00_AXI_arlock[1:0],M00_AXI_arcache[3:0],M00_AXI_arprot[2:0],M00_AXI_arqos[3:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rlast,M00_AXI_rvalid,M00_AXI_rready" */
|
||||
/* synthesis syn_force_seq_prim="aclk" */;
|
||||
input aclk /* synthesis syn_isclock = 1 */;
|
||||
input aresetn;
|
||||
input [31:0]S00_AXI_araddr;
|
||||
input [7:0]S00_AXI_arlen;
|
||||
input [2:0]S00_AXI_arsize;
|
||||
input [1:0]S00_AXI_arburst;
|
||||
input [0:0]S00_AXI_arlock;
|
||||
input [3:0]S00_AXI_arcache;
|
||||
input [2:0]S00_AXI_arprot;
|
||||
input [3:0]S00_AXI_arqos;
|
||||
input S00_AXI_arvalid;
|
||||
output S00_AXI_arready;
|
||||
output [31:0]S00_AXI_rdata;
|
||||
output [1:0]S00_AXI_rresp;
|
||||
output S00_AXI_rlast;
|
||||
output S00_AXI_rvalid;
|
||||
input S00_AXI_rready;
|
||||
input [31:0]S01_AXI_awaddr;
|
||||
input [7:0]S01_AXI_awlen;
|
||||
input [2:0]S01_AXI_awsize;
|
||||
input [1:0]S01_AXI_awburst;
|
||||
input [0:0]S01_AXI_awlock;
|
||||
input [3:0]S01_AXI_awcache;
|
||||
input [2:0]S01_AXI_awprot;
|
||||
input [3:0]S01_AXI_awqos;
|
||||
input S01_AXI_awvalid;
|
||||
output S01_AXI_awready;
|
||||
input [31:0]S01_AXI_wdata;
|
||||
input [3:0]S01_AXI_wstrb;
|
||||
input S01_AXI_wlast;
|
||||
input S01_AXI_wvalid;
|
||||
output S01_AXI_wready;
|
||||
output [1:0]S01_AXI_bresp;
|
||||
output S01_AXI_bvalid;
|
||||
input S01_AXI_bready;
|
||||
input [31:0]S02_AXI_awaddr;
|
||||
input [7:0]S02_AXI_awlen;
|
||||
input [2:0]S02_AXI_awsize;
|
||||
input [1:0]S02_AXI_awburst;
|
||||
input [0:0]S02_AXI_awlock;
|
||||
input [3:0]S02_AXI_awcache;
|
||||
input [2:0]S02_AXI_awprot;
|
||||
input [3:0]S02_AXI_awqos;
|
||||
input S02_AXI_awvalid;
|
||||
output S02_AXI_awready;
|
||||
input [31:0]S02_AXI_wdata;
|
||||
input [3:0]S02_AXI_wstrb;
|
||||
input S02_AXI_wlast;
|
||||
input S02_AXI_wvalid;
|
||||
output S02_AXI_wready;
|
||||
output [1:0]S02_AXI_bresp;
|
||||
output S02_AXI_bvalid;
|
||||
input S02_AXI_bready;
|
||||
input [31:0]S03_AXI_awaddr;
|
||||
input [7:0]S03_AXI_awlen;
|
||||
input [2:0]S03_AXI_awsize;
|
||||
input [1:0]S03_AXI_awburst;
|
||||
input [0:0]S03_AXI_awlock;
|
||||
input [3:0]S03_AXI_awcache;
|
||||
input [2:0]S03_AXI_awprot;
|
||||
input [3:0]S03_AXI_awqos;
|
||||
input S03_AXI_awvalid;
|
||||
output S03_AXI_awready;
|
||||
input [31:0]S03_AXI_wdata;
|
||||
input [3:0]S03_AXI_wstrb;
|
||||
input S03_AXI_wlast;
|
||||
input S03_AXI_wvalid;
|
||||
output S03_AXI_wready;
|
||||
output [1:0]S03_AXI_bresp;
|
||||
output S03_AXI_bvalid;
|
||||
input S03_AXI_bready;
|
||||
output [31:0]M00_AXI_awaddr;
|
||||
output [3:0]M00_AXI_awlen;
|
||||
output [2:0]M00_AXI_awsize;
|
||||
output [1:0]M00_AXI_awburst;
|
||||
output [1:0]M00_AXI_awlock;
|
||||
output [3:0]M00_AXI_awcache;
|
||||
output [2:0]M00_AXI_awprot;
|
||||
output [3:0]M00_AXI_awqos;
|
||||
output M00_AXI_awvalid;
|
||||
input M00_AXI_awready;
|
||||
output [31:0]M00_AXI_wdata;
|
||||
output [3:0]M00_AXI_wstrb;
|
||||
output M00_AXI_wlast;
|
||||
output M00_AXI_wvalid;
|
||||
input M00_AXI_wready;
|
||||
input [1:0]M00_AXI_bresp;
|
||||
input M00_AXI_bvalid;
|
||||
output M00_AXI_bready;
|
||||
output [31:0]M00_AXI_araddr;
|
||||
output [3:0]M00_AXI_arlen;
|
||||
output [2:0]M00_AXI_arsize;
|
||||
output [1:0]M00_AXI_arburst;
|
||||
output [1:0]M00_AXI_arlock;
|
||||
output [3:0]M00_AXI_arcache;
|
||||
output [2:0]M00_AXI_arprot;
|
||||
output [3:0]M00_AXI_arqos;
|
||||
output M00_AXI_arvalid;
|
||||
input M00_AXI_arready;
|
||||
input [31:0]M00_AXI_rdata;
|
||||
input [1:0]M00_AXI_rresp;
|
||||
input M00_AXI_rlast;
|
||||
input M00_AXI_rvalid;
|
||||
output M00_AXI_rready;
|
||||
endmodule
|
||||
@@ -0,0 +1,134 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Thu Jul 2 17:38:31 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_smartconnect_0_0_stub.vhdl
|
||||
-- Design : design_a9_1_smartconnect_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_arvalid : in STD_LOGIC;
|
||||
S00_AXI_arready : out STD_LOGIC;
|
||||
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_rlast : out STD_LOGIC;
|
||||
S00_AXI_rvalid : out STD_LOGIC;
|
||||
S00_AXI_rready : in STD_LOGIC;
|
||||
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S01_AXI_awvalid : in STD_LOGIC;
|
||||
S01_AXI_awready : out STD_LOGIC;
|
||||
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S01_AXI_wlast : in STD_LOGIC;
|
||||
S01_AXI_wvalid : in STD_LOGIC;
|
||||
S01_AXI_wready : out STD_LOGIC;
|
||||
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S01_AXI_bvalid : out STD_LOGIC;
|
||||
S01_AXI_bready : in STD_LOGIC;
|
||||
S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S02_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S02_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S02_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S02_AXI_awvalid : in STD_LOGIC;
|
||||
S02_AXI_awready : out STD_LOGIC;
|
||||
S02_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S02_AXI_wlast : in STD_LOGIC;
|
||||
S02_AXI_wvalid : in STD_LOGIC;
|
||||
S02_AXI_wready : out STD_LOGIC;
|
||||
S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S02_AXI_bvalid : out STD_LOGIC;
|
||||
S02_AXI_bready : in STD_LOGIC;
|
||||
S03_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S03_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S03_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S03_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S03_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S03_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S03_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S03_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S03_AXI_awvalid : in STD_LOGIC;
|
||||
S03_AXI_awready : out STD_LOGIC;
|
||||
S03_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S03_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S03_AXI_wlast : in STD_LOGIC;
|
||||
S03_AXI_wvalid : in STD_LOGIC;
|
||||
S03_AXI_wready : out STD_LOGIC;
|
||||
S03_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S03_AXI_bvalid : out STD_LOGIC;
|
||||
S03_AXI_bready : in STD_LOGIC;
|
||||
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_awvalid : out STD_LOGIC;
|
||||
M00_AXI_awready : in STD_LOGIC;
|
||||
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_wlast : out STD_LOGIC;
|
||||
M00_AXI_wvalid : out STD_LOGIC;
|
||||
M00_AXI_wready : in STD_LOGIC;
|
||||
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_bvalid : in STD_LOGIC;
|
||||
M00_AXI_bready : out STD_LOGIC;
|
||||
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_arvalid : out STD_LOGIC;
|
||||
M00_AXI_arready : in STD_LOGIC;
|
||||
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_rlast : in STD_LOGIC;
|
||||
M00_AXI_rvalid : in STD_LOGIC;
|
||||
M00_AXI_rready : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,S00_AXI_araddr[31:0],S00_AXI_arlen[7:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[0:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rdata[31:0],S00_AXI_rresp[1:0],S00_AXI_rlast,S00_AXI_rvalid,S00_AXI_rready,S01_AXI_awaddr[31:0],S01_AXI_awlen[7:0],S01_AXI_awsize[2:0],S01_AXI_awburst[1:0],S01_AXI_awlock[0:0],S01_AXI_awcache[3:0],S01_AXI_awprot[2:0],S01_AXI_awqos[3:0],S01_AXI_awvalid,S01_AXI_awready,S01_AXI_wdata[31:0],S01_AXI_wstrb[3:0],S01_AXI_wlast,S01_AXI_wvalid,S01_AXI_wready,S01_AXI_bresp[1:0],S01_AXI_bvalid,S01_AXI_bready,S02_AXI_awaddr[31:0],S02_AXI_awlen[7:0],S02_AXI_awsize[2:0],S02_AXI_awburst[1:0],S02_AXI_awlock[0:0],S02_AXI_awcache[3:0],S02_AXI_awprot[2:0],S02_AXI_awqos[3:0],S02_AXI_awvalid,S02_AXI_awready,S02_AXI_wdata[31:0],S02_AXI_wstrb[3:0],S02_AXI_wlast,S02_AXI_wvalid,S02_AXI_wready,S02_AXI_bresp[1:0],S02_AXI_bvalid,S02_AXI_bready,S03_AXI_awaddr[31:0],S03_AXI_awlen[7:0],S03_AXI_awsize[2:0],S03_AXI_awburst[1:0],S03_AXI_awlock[0:0],S03_AXI_awcache[3:0],S03_AXI_awprot[2:0],S03_AXI_awqos[3:0],S03_AXI_awvalid,S03_AXI_awready,S03_AXI_wdata[31:0],S03_AXI_wstrb[3:0],S03_AXI_wlast,S03_AXI_wvalid,S03_AXI_wready,S03_AXI_bresp[1:0],S03_AXI_bvalid,S03_AXI_bready,M00_AXI_awaddr[31:0],M00_AXI_awlen[3:0],M00_AXI_awsize[2:0],M00_AXI_awburst[1:0],M00_AXI_awlock[1:0],M00_AXI_awcache[3:0],M00_AXI_awprot[2:0],M00_AXI_awqos[3:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wlast,M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[31:0],M00_AXI_arlen[3:0],M00_AXI_arsize[2:0],M00_AXI_arburst[1:0],M00_AXI_arlock[1:0],M00_AXI_arcache[3:0],M00_AXI_arprot[2:0],M00_AXI_arqos[3:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rlast,M00_AXI_rvalid,M00_AXI_rready";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "bd_962a,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:1
|
||||
Timestamp: Mon Jul 06 05:11:01 UTC 2026
|
||||
Reference in New Issue
Block a user