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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Oct 28 21:00:59 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ axis_data_fifo_w8_d128_stub.v
|
||||
// Design : axis_data_fifo_w8_d128
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axis_data_fifo_v2_0_10_top,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axis_aresetn, s_axis_aclk, s_axis_tvalid,
|
||||
s_axis_tready, s_axis_tdata, s_axis_tlast, m_axis_tvalid, m_axis_tready, m_axis_tdata,
|
||||
m_axis_tlast)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[7:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tlast" */
|
||||
/* synthesis syn_force_seq_prim="s_axis_aclk" */;
|
||||
input s_axis_aresetn;
|
||||
input s_axis_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axis_tvalid;
|
||||
output s_axis_tready;
|
||||
input [7:0]s_axis_tdata;
|
||||
input s_axis_tlast;
|
||||
output m_axis_tvalid;
|
||||
input m_axis_tready;
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||||
output [7:0]m_axis_tdata;
|
||||
output m_axis_tlast;
|
||||
endmodule
|
||||
@@ -0,0 +1,40 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Oct 28 21:00:59 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ axis_data_fifo_w8_d128_stub.vhdl
|
||||
-- Design : axis_data_fifo_w8_d128
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
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||||
s_axis_aresetn : in STD_LOGIC;
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||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axis_tlast : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
m_axis_tlast : out STD_LOGIC
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||||
);
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||||
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||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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||||
attribute syn_black_box : boolean;
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||||
attribute black_box_pad_pin : string;
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||||
attribute syn_black_box of stub : architecture is true;
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||||
attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[7:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tlast";
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||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axis_data_fifo_v2_0_10_top,Vivado 2023.1";
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||||
begin
|
||||
end;
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||||
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@@ -0,0 +1,82 @@
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||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Jan 19 20:18:21 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
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||||
// Design : u_ila_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
|
||||
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
|
||||
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
|
||||
probe51, probe52, probe53, probe54)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[7:0],probe1[7:0],probe2[11:0],probe3[7:0],probe4[11:0],probe5[7:0],probe6[31:0],probe7[31:0],probe8[31:0],probe9[31:0],probe10[7:0],probe11[23:0],probe12[1:0],probe13[0:0],probe14[7:0],probe15[15:0],probe16[7:0],probe17[15:0],probe18[3:0],probe19[0:0],probe20[0:0],probe21[0:0],probe22[0:0],probe23[0:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0]" */
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||||
/* synthesis syn_force_seq_prim="clk" */;
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||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [7:0]probe0;
|
||||
input [7:0]probe1;
|
||||
input [11:0]probe2;
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||||
input [7:0]probe3;
|
||||
input [11:0]probe4;
|
||||
input [7:0]probe5;
|
||||
input [31:0]probe6;
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||||
input [31:0]probe7;
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||||
input [31:0]probe8;
|
||||
input [31:0]probe9;
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||||
input [7:0]probe10;
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||||
input [23:0]probe11;
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||||
input [1:0]probe12;
|
||||
input [0:0]probe13;
|
||||
input [7:0]probe14;
|
||||
input [15:0]probe15;
|
||||
input [7:0]probe16;
|
||||
input [15:0]probe17;
|
||||
input [3:0]probe18;
|
||||
input [0:0]probe19;
|
||||
input [0:0]probe20;
|
||||
input [0:0]probe21;
|
||||
input [0:0]probe22;
|
||||
input [0:0]probe23;
|
||||
input [0:0]probe24;
|
||||
input [0:0]probe25;
|
||||
input [0:0]probe26;
|
||||
input [0:0]probe27;
|
||||
input [0:0]probe28;
|
||||
input [0:0]probe29;
|
||||
input [0:0]probe30;
|
||||
input [0:0]probe31;
|
||||
input [0:0]probe32;
|
||||
input [0:0]probe33;
|
||||
input [0:0]probe34;
|
||||
input [0:0]probe35;
|
||||
input [0:0]probe36;
|
||||
input [0:0]probe37;
|
||||
input [0:0]probe38;
|
||||
input [0:0]probe39;
|
||||
input [0:0]probe40;
|
||||
input [0:0]probe41;
|
||||
input [0:0]probe42;
|
||||
input [0:0]probe43;
|
||||
input [0:0]probe44;
|
||||
input [0:0]probe45;
|
||||
input [0:0]probe46;
|
||||
input [0:0]probe47;
|
||||
input [0:0]probe48;
|
||||
input [0:0]probe49;
|
||||
input [0:0]probe50;
|
||||
input [0:0]probe51;
|
||||
input [0:0]probe52;
|
||||
input [0:0]probe53;
|
||||
input [0:0]probe54;
|
||||
endmodule
|
||||
@@ -0,0 +1,86 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Jan 19 20:18:21 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
|
||||
-- Design : u_ila_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 23 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[7:0],probe1[7:0],probe2[11:0],probe3[7:0],probe4[11:0],probe5[7:0],probe6[31:0],probe7[31:0],probe8[31:0],probe9[31:0],probe10[7:0],probe11[23:0],probe12[1:0],probe13[0:0],probe14[7:0],probe15[15:0],probe16[7:0],probe17[15:0],probe18[3:0],probe19[0:0],probe20[0:0],probe21[0:0],probe22[0:0],probe23[0:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,63 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>5c244d4a57339dad</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_a9_1_axis_data_fifo_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axis_data_fifo" spirit:version="2.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN_CONV_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_axis_data_fifo_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_DEPTH">8192</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MEMORY_TYPE">auto</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MODE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_AEMPTY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_AFULL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ECC_ERR_INJECT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_PROG_EMPTY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_PROG_FULL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TLAST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_ACLK_ASYNC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROG_EMPTY_THRESH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROG_FULL_THRESH">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">5c244d4a57339dad</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">79870778</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">71</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
+4698
File diff suppressed because it is too large
Load Diff
+5736
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,33 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Nov 20 15:11:56 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axis_data_fifo_0_0_stub.v
|
||||
// Design : design_a9_1_axis_data_fifo_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axis_data_fifo_v2_0_10_top,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axis_aresetn, s_axis_aclk, s_axis_tvalid,
|
||||
s_axis_tready, s_axis_tdata, s_axis_tlast, m_axis_tvalid, m_axis_tready, m_axis_tdata,
|
||||
m_axis_tlast)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0],m_axis_tlast" */
|
||||
/* synthesis syn_force_seq_prim="s_axis_aclk" */;
|
||||
input s_axis_aresetn;
|
||||
input s_axis_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axis_tvalid;
|
||||
output s_axis_tready;
|
||||
input [31:0]s_axis_tdata;
|
||||
input s_axis_tlast;
|
||||
output m_axis_tvalid;
|
||||
input m_axis_tready;
|
||||
output [31:0]m_axis_tdata;
|
||||
output m_axis_tlast;
|
||||
endmodule
|
||||
@@ -0,0 +1,40 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Thu Nov 20 15:11:56 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axis_data_fifo_0_0_stub.vhdl
|
||||
-- Design : design_a9_1_axis_data_fifo_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
s_axis_aresetn : in STD_LOGIC;
|
||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axis_tlast : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_tlast : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0],m_axis_tlast";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axis_data_fifo_v2_0_10_top,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:1
|
||||
Timestamp: Wed Jun 24 05:51:52 UTC 2026
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@@ -0,0 +1,82 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Dec 24 14:39:02 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
|
||||
// Design : u_ila_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
|
||||
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
|
||||
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
|
||||
probe51, probe52, probe53, probe54)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[31:0],probe1[31:0],probe2[7:0],probe3[7:0],probe4[15:0],probe5[31:0],probe6[0:0],probe7[23:0],probe8[15:0],probe9[23:0],probe10[7:0],probe11[1:0],probe12[31:0],probe13[7:0],probe14[8:0],probe15[15:0],probe16[7:0],probe17[8:0],probe18[7:0],probe19[15:0],probe20[15:0],probe21[7:0],probe22[15:0],probe23[7:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [31:0]probe0;
|
||||
input [31:0]probe1;
|
||||
input [7:0]probe2;
|
||||
input [7:0]probe3;
|
||||
input [15:0]probe4;
|
||||
input [31:0]probe5;
|
||||
input [0:0]probe6;
|
||||
input [23:0]probe7;
|
||||
input [15:0]probe8;
|
||||
input [23:0]probe9;
|
||||
input [7:0]probe10;
|
||||
input [1:0]probe11;
|
||||
input [31:0]probe12;
|
||||
input [7:0]probe13;
|
||||
input [8:0]probe14;
|
||||
input [15:0]probe15;
|
||||
input [7:0]probe16;
|
||||
input [8:0]probe17;
|
||||
input [7:0]probe18;
|
||||
input [15:0]probe19;
|
||||
input [15:0]probe20;
|
||||
input [7:0]probe21;
|
||||
input [15:0]probe22;
|
||||
input [7:0]probe23;
|
||||
input [0:0]probe24;
|
||||
input [0:0]probe25;
|
||||
input [0:0]probe26;
|
||||
input [0:0]probe27;
|
||||
input [0:0]probe28;
|
||||
input [0:0]probe29;
|
||||
input [0:0]probe30;
|
||||
input [0:0]probe31;
|
||||
input [0:0]probe32;
|
||||
input [0:0]probe33;
|
||||
input [0:0]probe34;
|
||||
input [0:0]probe35;
|
||||
input [0:0]probe36;
|
||||
input [0:0]probe37;
|
||||
input [0:0]probe38;
|
||||
input [0:0]probe39;
|
||||
input [0:0]probe40;
|
||||
input [0:0]probe41;
|
||||
input [0:0]probe42;
|
||||
input [0:0]probe43;
|
||||
input [0:0]probe44;
|
||||
input [0:0]probe45;
|
||||
input [0:0]probe46;
|
||||
input [0:0]probe47;
|
||||
input [0:0]probe48;
|
||||
input [0:0]probe49;
|
||||
input [0:0]probe50;
|
||||
input [0:0]probe51;
|
||||
input [0:0]probe52;
|
||||
input [0:0]probe53;
|
||||
input [0:0]probe54;
|
||||
endmodule
|
||||
@@ -0,0 +1,86 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Dec 24 14:39:02 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
|
||||
-- Design : u_ila_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 23 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 23 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[31:0],probe1[31:0],probe2[7:0],probe3[7:0],probe4[15:0],probe5[31:0],probe6[0:0],probe7[23:0],probe8[15:0],probe9[23:0],probe10[7:0],probe11[1:0],probe12[31:0],probe13[7:0],probe14[8:0],probe15[15:0],probe16[7:0],probe17[8:0],probe18[7:0],probe19[15:0],probe20[15:0],probe21[7:0],probe22[15:0],probe23[7:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,51 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
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||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>ipcache</spirit:library>
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<spirit:name>5f539025ae89bc95</spirit:name>
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<spirit:version>0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>design_a9_1_axi_bram_ctrl_0_0</spirit:instanceName>
|
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_bram_ctrl" spirit:version="4.1"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.FREQ_HZ">1e+08</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">1e+08</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BMG_INSTANCE">EXTERNAL</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_axi_bram_ctrl_0_0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC_ONOFF_RESET_VALUE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FAULT_INJECT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_DEPTH">2048</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_CMD_OPTIMIZATION">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINGLE_PORT_BRAM">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_ECC">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">5f539025ae89bc95</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">425dc4e2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">67</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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</spirit:configurableElementValues>
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</spirit:componentInstance>
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</spirit:componentInstances>
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</spirit:design>
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Binary file not shown.
+1140
File diff suppressed because it is too large
Load Diff
+1119
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,54 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Nov 20 15:11:53 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_bram_ctrl_0_0_stub.v
|
||||
// Design : design_a9_1_axi_bram_ctrl_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_bram_ctrl,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
|
||||
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot,
|
||||
s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready,
|
||||
bram_rst_a, bram_clk_a, bram_en_a, bram_we_a, bram_addr_a, bram_wrdata_a, bram_rddata_a)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[12:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[12:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,bram_rst_a,bram_en_a,bram_we_a[3:0],bram_addr_a[12:0],bram_wrdata_a[31:0],bram_rddata_a[31:0]" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */
|
||||
/* synthesis syn_force_seq_prim="bram_clk_a" */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [12:0]s_axi_awaddr;
|
||||
input [2:0]s_axi_awprot;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [12:0]s_axi_araddr;
|
||||
input [2:0]s_axi_arprot;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output bram_rst_a;
|
||||
output bram_clk_a /* synthesis syn_isclock = 1 */;
|
||||
output bram_en_a;
|
||||
output [3:0]bram_we_a;
|
||||
output [12:0]bram_addr_a;
|
||||
output [31:0]bram_wrdata_a;
|
||||
input [31:0]bram_rddata_a;
|
||||
endmodule
|
||||
@@ -0,0 +1,58 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Thu Nov 20 15:11:53 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_bram_ctrl_0_0_stub.vhdl
|
||||
-- Design : design_a9_1_axi_bram_ctrl_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
bram_rst_a : out STD_LOGIC;
|
||||
bram_clk_a : out STD_LOGIC;
|
||||
bram_en_a : out STD_LOGIC;
|
||||
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[12:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[12:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[12:0],bram_wrdata_a[31:0],bram_rddata_a[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_bram_ctrl,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:14
|
||||
Timestamp: Wed Jun 24 05:51:52 UTC 2026
|
||||
@@ -0,0 +1,63 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:name>5fa990a4cbc1262d</spirit:name>
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<spirit:version>0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>design_a9_1_axis_data_fifo_2_0</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axis_data_fifo" spirit:version="2.0"/>
|
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.FREQ_HZ">100000000</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN_CONV_MODE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MEMORY_TYPE">auto</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_AEMPTY">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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</spirit:configurableElementValues>
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</spirit:componentInstance>
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</spirit:componentInstances>
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</spirit:design>
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Binary file not shown.
+11820
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Load Diff
+13329
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Load Diff
@@ -0,0 +1,36 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Jul 2 17:35:33 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axis_data_fifo_2_0_stub.v
|
||||
// Design : design_a9_1_axis_data_fifo_2_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axis_data_fifo_v2_0_10_top,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axis_aresetn, s_axis_aclk, s_axis_tvalid,
|
||||
s_axis_tready, s_axis_tdata, s_axis_tkeep, s_axis_tlast, m_axis_tvalid, m_axis_tready,
|
||||
m_axis_tdata, m_axis_tkeep, m_axis_tlast, prog_full)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],s_axis_tkeep[3:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0],m_axis_tkeep[3:0],m_axis_tlast,prog_full" */
|
||||
/* synthesis syn_force_seq_prim="s_axis_aclk" */;
|
||||
input s_axis_aresetn;
|
||||
input s_axis_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axis_tvalid;
|
||||
output s_axis_tready;
|
||||
input [31:0]s_axis_tdata;
|
||||
input [3:0]s_axis_tkeep;
|
||||
input s_axis_tlast;
|
||||
output m_axis_tvalid;
|
||||
input m_axis_tready;
|
||||
output [31:0]m_axis_tdata;
|
||||
output [3:0]m_axis_tkeep;
|
||||
output m_axis_tlast;
|
||||
output prog_full;
|
||||
endmodule
|
||||
@@ -0,0 +1,43 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Thu Jul 2 17:35:33 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axis_data_fifo_2_0_stub.vhdl
|
||||
-- Design : design_a9_1_axis_data_fifo_2_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
s_axis_aresetn : in STD_LOGIC;
|
||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axis_tlast : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axis_tlast : out STD_LOGIC;
|
||||
prog_full : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],s_axis_tkeep[3:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0],m_axis_tkeep[3:0],m_axis_tlast,prog_full";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axis_data_fifo_v2_0_10_top,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:1
|
||||
Timestamp: Thu Jul 02 09:35:53 UTC 2026
|
||||
Reference in New Issue
Block a user