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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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// Date : Wed Nov 12 16:47:20 2025
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// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_smartconnect_0_0_stub.v
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// Design : design_a9_1_smartconnect_0_0
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z020clg400-2
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* X_CORE_INFO = "bd_962a,Vivado 2023.1" *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, S00_AXI_araddr, S00_AXI_arlen,
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S00_AXI_arsize, S00_AXI_arburst, S00_AXI_arlock, S00_AXI_arcache, S00_AXI_arprot,
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S00_AXI_arqos, S00_AXI_arvalid, S00_AXI_arready, S00_AXI_rdata, S00_AXI_rresp,
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S00_AXI_rlast, S00_AXI_rvalid, S00_AXI_rready, S01_AXI_awaddr, S01_AXI_awlen,
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S01_AXI_awsize, S01_AXI_awburst, S01_AXI_awlock, S01_AXI_awcache, S01_AXI_awprot,
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S01_AXI_awqos, S01_AXI_awvalid, S01_AXI_awready, S01_AXI_wdata, S01_AXI_wstrb,
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S01_AXI_wlast, S01_AXI_wvalid, S01_AXI_wready, S01_AXI_bresp, S01_AXI_bvalid,
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S01_AXI_bready, M00_AXI_awaddr, M00_AXI_awlen, M00_AXI_awsize, M00_AXI_awburst,
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M00_AXI_awlock, M00_AXI_awcache, M00_AXI_awprot, M00_AXI_awqos, M00_AXI_awvalid,
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M00_AXI_awready, M00_AXI_wdata, M00_AXI_wstrb, M00_AXI_wlast, M00_AXI_wvalid,
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M00_AXI_wready, M00_AXI_bresp, M00_AXI_bvalid, M00_AXI_bready, M00_AXI_araddr,
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M00_AXI_arlen, M00_AXI_arsize, M00_AXI_arburst, M00_AXI_arlock, M00_AXI_arcache,
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M00_AXI_arprot, M00_AXI_arqos, M00_AXI_arvalid, M00_AXI_arready, M00_AXI_rdata,
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M00_AXI_rresp, M00_AXI_rlast, M00_AXI_rvalid, M00_AXI_rready)
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/* synthesis syn_black_box black_box_pad_pin="aresetn,S00_AXI_araddr[31:0],S00_AXI_arlen[7:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[0:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rdata[31:0],S00_AXI_rresp[1:0],S00_AXI_rlast,S00_AXI_rvalid,S00_AXI_rready,S01_AXI_awaddr[31:0],S01_AXI_awlen[7:0],S01_AXI_awsize[2:0],S01_AXI_awburst[1:0],S01_AXI_awlock[0:0],S01_AXI_awcache[3:0],S01_AXI_awprot[2:0],S01_AXI_awqos[3:0],S01_AXI_awvalid,S01_AXI_awready,S01_AXI_wdata[31:0],S01_AXI_wstrb[3:0],S01_AXI_wlast,S01_AXI_wvalid,S01_AXI_wready,S01_AXI_bresp[1:0],S01_AXI_bvalid,S01_AXI_bready,M00_AXI_awaddr[31:0],M00_AXI_awlen[3:0],M00_AXI_awsize[2:0],M00_AXI_awburst[1:0],M00_AXI_awlock[1:0],M00_AXI_awcache[3:0],M00_AXI_awprot[2:0],M00_AXI_awqos[3:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wlast,M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[31:0],M00_AXI_arlen[3:0],M00_AXI_arsize[2:0],M00_AXI_arburst[1:0],M00_AXI_arlock[1:0],M00_AXI_arcache[3:0],M00_AXI_arprot[2:0],M00_AXI_arqos[3:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rlast,M00_AXI_rvalid,M00_AXI_rready" */
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/* synthesis syn_force_seq_prim="aclk" */;
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input aclk /* synthesis syn_isclock = 1 */;
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input aresetn;
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input [31:0]S00_AXI_araddr;
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input [7:0]S00_AXI_arlen;
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input [2:0]S00_AXI_arsize;
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input [1:0]S00_AXI_arburst;
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input [0:0]S00_AXI_arlock;
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input [3:0]S00_AXI_arcache;
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input [2:0]S00_AXI_arprot;
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input [3:0]S00_AXI_arqos;
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input S00_AXI_arvalid;
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output S00_AXI_arready;
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output [31:0]S00_AXI_rdata;
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output [1:0]S00_AXI_rresp;
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output S00_AXI_rlast;
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output S00_AXI_rvalid;
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input S00_AXI_rready;
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input [31:0]S01_AXI_awaddr;
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input [7:0]S01_AXI_awlen;
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input [2:0]S01_AXI_awsize;
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input [1:0]S01_AXI_awburst;
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input [0:0]S01_AXI_awlock;
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input [3:0]S01_AXI_awcache;
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input [2:0]S01_AXI_awprot;
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input [3:0]S01_AXI_awqos;
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input S01_AXI_awvalid;
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output S01_AXI_awready;
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input [31:0]S01_AXI_wdata;
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input [3:0]S01_AXI_wstrb;
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input S01_AXI_wlast;
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input S01_AXI_wvalid;
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output S01_AXI_wready;
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output [1:0]S01_AXI_bresp;
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output S01_AXI_bvalid;
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input S01_AXI_bready;
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output [31:0]M00_AXI_awaddr;
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output [3:0]M00_AXI_awlen;
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output [2:0]M00_AXI_awsize;
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output [1:0]M00_AXI_awburst;
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output [1:0]M00_AXI_awlock;
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output [3:0]M00_AXI_awcache;
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output [2:0]M00_AXI_awprot;
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output [3:0]M00_AXI_awqos;
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output M00_AXI_awvalid;
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input M00_AXI_awready;
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output [31:0]M00_AXI_wdata;
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output [3:0]M00_AXI_wstrb;
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output M00_AXI_wlast;
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output M00_AXI_wvalid;
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input M00_AXI_wready;
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input [1:0]M00_AXI_bresp;
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input M00_AXI_bvalid;
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output M00_AXI_bready;
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output [31:0]M00_AXI_araddr;
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output [3:0]M00_AXI_arlen;
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output [2:0]M00_AXI_arsize;
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output [1:0]M00_AXI_arburst;
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output [1:0]M00_AXI_arlock;
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output [3:0]M00_AXI_arcache;
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output [2:0]M00_AXI_arprot;
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output [3:0]M00_AXI_arqos;
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output M00_AXI_arvalid;
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input M00_AXI_arready;
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input [31:0]M00_AXI_rdata;
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input [1:0]M00_AXI_rresp;
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input M00_AXI_rlast;
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input M00_AXI_rvalid;
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output M00_AXI_rready;
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endmodule
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@@ -0,0 +1,98 @@
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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-- Date : Wed Nov 12 16:47:20 2025
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-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_smartconnect_0_0_stub.vhdl
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-- Design : design_a9_1_smartconnect_0_0
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7z020clg400-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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Port (
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aclk : in STD_LOGIC;
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aresetn : in STD_LOGIC;
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S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
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S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
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S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
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S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
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S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
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S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
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S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
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S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
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S00_AXI_arvalid : in STD_LOGIC;
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S00_AXI_arready : out STD_LOGIC;
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S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
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S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
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S00_AXI_rlast : out STD_LOGIC;
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S00_AXI_rvalid : out STD_LOGIC;
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S00_AXI_rready : in STD_LOGIC;
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S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
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S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
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S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
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S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
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S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
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S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
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S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
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S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
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S01_AXI_awvalid : in STD_LOGIC;
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S01_AXI_awready : out STD_LOGIC;
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S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
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S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
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S01_AXI_wlast : in STD_LOGIC;
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S01_AXI_wvalid : in STD_LOGIC;
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S01_AXI_wready : out STD_LOGIC;
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S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
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S01_AXI_bvalid : out STD_LOGIC;
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S01_AXI_bready : in STD_LOGIC;
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M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
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M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
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M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
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M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
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M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
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M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
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M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
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M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
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M00_AXI_awvalid : out STD_LOGIC;
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M00_AXI_awready : in STD_LOGIC;
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M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
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M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
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M00_AXI_wlast : out STD_LOGIC;
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M00_AXI_wvalid : out STD_LOGIC;
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M00_AXI_wready : in STD_LOGIC;
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M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
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M00_AXI_bvalid : in STD_LOGIC;
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M00_AXI_bready : out STD_LOGIC;
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M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
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M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
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M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
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M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
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M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
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M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
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M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
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M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
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M00_AXI_arvalid : out STD_LOGIC;
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M00_AXI_arready : in STD_LOGIC;
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M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
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M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
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M00_AXI_rlast : in STD_LOGIC;
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M00_AXI_rvalid : in STD_LOGIC;
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M00_AXI_rready : out STD_LOGIC
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);
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end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,S00_AXI_araddr[31:0],S00_AXI_arlen[7:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[0:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rdata[31:0],S00_AXI_rresp[1:0],S00_AXI_rlast,S00_AXI_rvalid,S00_AXI_rready,S01_AXI_awaddr[31:0],S01_AXI_awlen[7:0],S01_AXI_awsize[2:0],S01_AXI_awburst[1:0],S01_AXI_awlock[0:0],S01_AXI_awcache[3:0],S01_AXI_awprot[2:0],S01_AXI_awqos[3:0],S01_AXI_awvalid,S01_AXI_awready,S01_AXI_wdata[31:0],S01_AXI_wstrb[3:0],S01_AXI_wlast,S01_AXI_wvalid,S01_AXI_wready,S01_AXI_bresp[1:0],S01_AXI_bvalid,S01_AXI_bready,M00_AXI_awaddr[31:0],M00_AXI_awlen[3:0],M00_AXI_awsize[2:0],M00_AXI_awburst[1:0],M00_AXI_awlock[1:0],M00_AXI_awcache[3:0],M00_AXI_awprot[2:0],M00_AXI_awqos[3:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wlast,M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[31:0],M00_AXI_arlen[3:0],M00_AXI_arsize[2:0],M00_AXI_arburst[1:0],M00_AXI_arlock[1:0],M00_AXI_arcache[3:0],M00_AXI_arprot[2:0],M00_AXI_arqos[3:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rlast,M00_AXI_rvalid,M00_AXI_rready";
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attribute X_CORE_INFO : string;
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attribute X_CORE_INFO of stub : architecture is "bd_962a,Vivado 2023.1";
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begin
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end;
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@@ -0,0 +1,2 @@
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NumberHits:7
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Timestamp: Wed Dec 24 06:16:02 UTC 2025
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