sync chunk 9/12

c64_pro.cache/ip/2023.1/f/b/fb7e50cc1c8b5084/u_ila_0_stub.v

@@ -0,0 +1,89 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Wed Jun 24 16:42:05 2026
+// Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
+// Design      : u_ila_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "ila,Vivado 2023.1" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
+  probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, 
+  probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28, 
+  probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39, 
+  probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50, 
+  probe51, probe52, probe53, probe54, probe55, probe56, probe57, probe58, probe59, probe60, probe61)
+/* synthesis syn_black_box black_box_pad_pin="probe0[31:0],probe1[31:0],probe2[1:0],probe3[7:0],probe4[7:0],probe5[15:0],probe6[15:0],probe7[7:0],probe8[0:0],probe9[7:0],probe10[15:0],probe11[1:0],probe12[7:0],probe13[7:0],probe14[15:0],probe15[15:0],probe16[8:0],probe17[15:0],probe18[8:0],probe19[7:0],probe20[15:0],probe21[15:0],probe22[7:0],probe23[7:0],probe24[7:0],probe25[12:0],probe26[31:0],probe27[3:0],probe28[31:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0]" */
+/* synthesis syn_force_seq_prim="clk" */;
+  input clk /* synthesis syn_isclock = 1 */;
+  input [31:0]probe0;
+  input [31:0]probe1;
+  input [1:0]probe2;
+  input [7:0]probe3;
+  input [7:0]probe4;
+  input [15:0]probe5;
+  input [15:0]probe6;
+  input [7:0]probe7;
+  input [0:0]probe8;
+  input [7:0]probe9;
+  input [15:0]probe10;
+  input [1:0]probe11;
+  input [7:0]probe12;
+  input [7:0]probe13;
+  input [15:0]probe14;
+  input [15:0]probe15;
+  input [8:0]probe16;
+  input [15:0]probe17;
+  input [8:0]probe18;
+  input [7:0]probe19;
+  input [15:0]probe20;
+  input [15:0]probe21;
+  input [7:0]probe22;
+  input [7:0]probe23;
+  input [7:0]probe24;
+  input [12:0]probe25;
+  input [31:0]probe26;
+  input [3:0]probe27;
+  input [31:0]probe28;
+  input [0:0]probe29;
+  input [0:0]probe30;
+  input [0:0]probe31;
+  input [0:0]probe32;
+  input [0:0]probe33;
+  input [0:0]probe34;
+  input [0:0]probe35;
+  input [0:0]probe36;
+  input [0:0]probe37;
+  input [0:0]probe38;
+  input [0:0]probe39;
+  input [0:0]probe40;
+  input [0:0]probe41;
+  input [0:0]probe42;
+  input [0:0]probe43;
+  input [0:0]probe44;
+  input [0:0]probe45;
+  input [0:0]probe46;
+  input [0:0]probe47;
+  input [0:0]probe48;
+  input [0:0]probe49;
+  input [0:0]probe50;
+  input [0:0]probe51;
+  input [0:0]probe52;
+  input [0:0]probe53;
+  input [0:0]probe54;
+  input [0:0]probe55;
+  input [0:0]probe56;
+  input [0:0]probe57;
+  input [0:0]probe58;
+  input [0:0]probe59;
+  input [0:0]probe60;
+  input [0:0]probe61;
+endmodule

c64_pro.cache/ip/2023.1/f/b/fb7e50cc1c8b5084/u_ila_0_stub.vhdl

@@ -0,0 +1,93 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+-- Date        : Wed Jun 24 16:42:05 2026
+-- Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
+-- Design      : u_ila_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z020clg400-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+  Port ( 
+    clk : in STD_LOGIC;
+    probe0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe5 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe6 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe7 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe9 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe11 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe12 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe13 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe14 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe15 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe16 : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    probe17 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe18 : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    probe19 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe20 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe21 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe22 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe23 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe24 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe25 : in STD_LOGIC_VECTOR ( 12 downto 0 );
+    probe26 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe27 : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    probe28 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe54 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe55 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe56 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe57 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe58 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe59 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe60 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe61 : in STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,probe0[31:0],probe1[31:0],probe2[1:0],probe3[7:0],probe4[7:0],probe5[15:0],probe6[15:0],probe7[7:0],probe8[0:0],probe9[7:0],probe10[15:0],probe11[1:0],probe12[7:0],probe13[7:0],probe14[15:0],probe15[15:0],probe16[8:0],probe17[15:0],probe18[8:0],probe19[7:0],probe20[15:0],probe21[15:0],probe22[7:0],probe23[7:0],probe24[7:0],probe25[12:0],probe26[31:0],probe27[3:0],probe28[31:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
+begin
+end;

c64_pro.cache/sim/ssm.db

@@ -2,43 +2,100 @@
 #                            DONOT REMOVE THIS FILE
 # Unified simulation database file for selected simulation model for IP
 #
-# File: ssm.db (Fri Mar 29 13:04:39 2024)
+# File: ssm.db (Wed Jun 24 17:45:27 2026)
 #
 # This file is generated by the unified simulation automation and contains the
 # selected simulation model information for the IP/BD instances.
 #                            DONOT REMOVE THIS FILE
 ################################################################################
-axis_data_fifo_w32_d16,rtl
 axis_data_fifo_w32_d32,rtl
 axis_data_fifo_w8_d128,rtl
-dds_stim_16ch,rtl
+c_add_s16_s32,rtl
+design_a9_1_CHANN_EN_0,rtl
+design_a9_1_CHANN_EN_1,rtl
+design_a9_1_CHANN_EN_2,rtl
+design_a9_1_CHANN_SEL_0,rtl
+design_a9_1_STIM_SPI_0,rtl
+design_a9_1_ZCHECK_SPI_0,rtl
+design_a9_1_Z_IO_0,rtl
 design_a9_1_axi_bram_ctrl_0_0,rtl
 design_a9_1_axi_bram_ctrl_1_0,rtl
 design_a9_1_axi_bram_ctrl_2_0,rtl
 design_a9_1_axi_bram_ctrl_3_0,rtl
+design_a9_1_axi_bram_ctrl_3_1,rtl
 design_a9_1_axi_bram_ctrl_4_0,rtl
+design_a9_1_axi_bram_ctrl_5_0,rtl
+design_a9_1_axi_bram_ctrl_6_0,rtl
 design_a9_1_axi_dma_0_0,rtl
 design_a9_1_axi_dma_1_0,rtl
+design_a9_1_axi_dma_1_1,rtl
+design_a9_1_axi_dma_2_0,rtl
 design_a9_1_axi_gpio_0_0,rtl
-design_a9_1_axi_iic_0_0,rtl
+design_a9_1_axi_gpio_1_0,rtl
-design_a9_1_axi_iic_1_0,rtl
+design_a9_1_axi_quad_spi_0_0,rtl
 design_a9_1_axi_smc_0,rtl
 design_a9_1_axis_data_fifo_0_0,rtl
 design_a9_1_axis_data_fifo_1_0,rtl
+design_a9_1_axis_data_fifo_1_1,rtl
+design_a9_1_axis_data_fifo_2_0,rtl
 design_a9_1_processing_system7_0_0,rtl
 design_a9_1_rst_ps7_0_50M_0,rtl
 design_a9_1_smartconnect_0_0,rtl
 design_a9_1_xlconcat_0_0,rtl
-mult_gen_au8_bu9_p8,rtl
+fifo_generator_0,rtl
+fifo_generator_1,rtl
+vio_cur_flt_state,rtl
 bd_6e35_arinsw_0,rtl
+bd_6e35_arinsw_1,rtl
+bd_6e35_arinsw_2,rtl
+bd_6e35_arinsw_3,rtl
+bd_6e35_arinsw_4,rtl
+bd_6e35_arinsw_5,rtl
+bd_6e35_arinsw_6,rtl
+bd_6e35_arinsw_7,rtl
+bd_6e35_arinsw_8,rtl
 bd_6e35_arni_0,rtl
-bd_6e35_aroutsw_0,rtl
+bd_6e35_arni_1,rtl
+bd_6e35_arni_2,rtl
+bd_6e35_arni_3,rtl
+bd_6e35_arni_4,rtl
+bd_6e35_arni_5,rtl
+bd_6e35_arni_6,rtl
+bd_6e35_arni_7,rtl
 bd_6e35_awinsw_0,rtl
+bd_6e35_awinsw_1,rtl
+bd_6e35_awinsw_2,rtl
+bd_6e35_awinsw_3,rtl
+bd_6e35_awinsw_4,rtl
+bd_6e35_awinsw_5,rtl
+bd_6e35_awinsw_6,rtl
+bd_6e35_awinsw_7,rtl
+bd_6e35_awinsw_8,rtl
 bd_6e35_awni_0,rtl
-bd_6e35_awoutsw_0,rtl
+bd_6e35_awni_1,rtl
+bd_6e35_awni_2,rtl
+bd_6e35_awni_3,rtl
+bd_6e35_awni_4,rtl
+bd_6e35_awni_5,rtl
+bd_6e35_awni_6,rtl
+bd_6e35_awni_7,rtl
 bd_6e35_binsw_0,rtl
+bd_6e35_binsw_1,rtl
+bd_6e35_binsw_2,rtl
+bd_6e35_binsw_3,rtl
+bd_6e35_binsw_4,rtl
+bd_6e35_binsw_5,rtl
+bd_6e35_binsw_6,rtl
+bd_6e35_binsw_7,rtl
+bd_6e35_binsw_8,rtl
 bd_6e35_bni_0,rtl
-bd_6e35_boutsw_0,rtl
+bd_6e35_bni_1,rtl
+bd_6e35_bni_2,rtl
+bd_6e35_bni_3,rtl
+bd_6e35_bni_4,rtl
+bd_6e35_bni_5,rtl
+bd_6e35_bni_6,rtl
+bd_6e35_bni_7,rtl
 bd_6e35_m00arn_0,rtl
 bd_6e35_m00awn_0,rtl
 bd_6e35_m00bn_0,rtl
@@ -109,11 +166,109 @@ bd_6e35_m09e_0,rtl
 bd_6e35_m09rn_0,rtl
 bd_6e35_m09s2a_0,rtl
 bd_6e35_m09wn_0,rtl
+bd_6e35_m10arn_0,rtl
+bd_6e35_m10awn_0,rtl
+bd_6e35_m10bn_0,rtl
+bd_6e35_m10e_0,rtl
+bd_6e35_m10rn_0,rtl
+bd_6e35_m10s2a_0,rtl
+bd_6e35_m10wn_0,rtl
+bd_6e35_m11arn_0,rtl
+bd_6e35_m11awn_0,rtl
+bd_6e35_m11bn_0,rtl
+bd_6e35_m11e_0,rtl
+bd_6e35_m11rn_0,rtl
+bd_6e35_m11s2a_0,rtl
+bd_6e35_m11wn_0,rtl
+bd_6e35_m12arn_0,rtl
+bd_6e35_m12awn_0,rtl
+bd_6e35_m12bn_0,rtl
+bd_6e35_m12e_0,rtl
+bd_6e35_m12rn_0,rtl
+bd_6e35_m12s2a_0,rtl
+bd_6e35_m12wn_0,rtl
+bd_6e35_m13arn_0,rtl
+bd_6e35_m13awn_0,rtl
+bd_6e35_m13bn_0,rtl
+bd_6e35_m13e_0,rtl
+bd_6e35_m13rn_0,rtl
+bd_6e35_m13s2a_0,rtl
+bd_6e35_m13wn_0,rtl
+bd_6e35_m14arn_0,rtl
+bd_6e35_m14awn_0,rtl
+bd_6e35_m14bn_0,rtl
+bd_6e35_m14e_0,rtl
+bd_6e35_m14rn_0,rtl
+bd_6e35_m14s2a_0,rtl
+bd_6e35_m14wn_0,rtl
+bd_6e35_m15arn_0,rtl
+bd_6e35_m15awn_0,rtl
+bd_6e35_m15bn_0,rtl
+bd_6e35_m15e_0,rtl
+bd_6e35_m15rn_0,rtl
+bd_6e35_m15s2a_0,rtl
+bd_6e35_m15wn_0,rtl
+bd_6e35_m16arn_0,rtl
+bd_6e35_m16awn_0,rtl
+bd_6e35_m16bn_0,rtl
+bd_6e35_m16e_0,rtl
+bd_6e35_m16rn_0,rtl
+bd_6e35_m16s2a_0,rtl
+bd_6e35_m16wn_0,rtl
+bd_6e35_m17arn_0,rtl
+bd_6e35_m17awn_0,rtl
+bd_6e35_m17bn_0,rtl
+bd_6e35_m17e_0,rtl
+bd_6e35_m17rn_0,rtl
+bd_6e35_m17s2a_0,rtl
+bd_6e35_m17wn_0,rtl
+bd_6e35_m18arn_0,rtl
+bd_6e35_m18awn_0,rtl
+bd_6e35_m18bn_0,rtl
+bd_6e35_m18e_0,rtl
+bd_6e35_m18rn_0,rtl
+bd_6e35_m18s2a_0,rtl
+bd_6e35_m18wn_0,rtl
+bd_6e35_m19arn_0,rtl
+bd_6e35_m19awn_0,rtl
+bd_6e35_m19bn_0,rtl
+bd_6e35_m19e_0,rtl
+bd_6e35_m19rn_0,rtl
+bd_6e35_m19s2a_0,rtl
+bd_6e35_m19wn_0,rtl
+bd_6e35_m20arn_0,rtl
+bd_6e35_m20awn_0,rtl
+bd_6e35_m20bn_0,rtl
+bd_6e35_m20e_0,rtl
+bd_6e35_m20rn_0,rtl
+bd_6e35_m20s2a_0,rtl
+bd_6e35_m20wn_0,rtl
+bd_6e35_m21arn_0,rtl
+bd_6e35_m21awn_0,rtl
+bd_6e35_m21bn_0,rtl
+bd_6e35_m21e_0,rtl
+bd_6e35_m21rn_0,rtl
+bd_6e35_m21s2a_0,rtl
+bd_6e35_m21wn_0,rtl
 bd_6e35_one_0,rtl
 bd_6e35_psr_aclk_0,rtl
 bd_6e35_rinsw_0,rtl
+bd_6e35_rinsw_1,rtl
+bd_6e35_rinsw_2,rtl
+bd_6e35_rinsw_3,rtl
+bd_6e35_rinsw_4,rtl
+bd_6e35_rinsw_5,rtl
+bd_6e35_rinsw_6,rtl
+bd_6e35_rinsw_7,rtl
+bd_6e35_rinsw_8,rtl
 bd_6e35_rni_0,rtl
-bd_6e35_routsw_0,rtl
+bd_6e35_rni_1,rtl
+bd_6e35_rni_2,rtl
+bd_6e35_rni_3,rtl
+bd_6e35_rni_4,rtl
+bd_6e35_rni_5,rtl
+bd_6e35_rni_6,rtl
+bd_6e35_rni_7,rtl
 bd_6e35_s00a2s_0,rtl
 bd_6e35_s00mmu_0,rtl
 bd_6e35_s00sic_0,rtl
@@ -124,8 +279,22 @@ bd_6e35_sbn_0,rtl
 bd_6e35_srn_0,rtl
 bd_6e35_swn_0,rtl
 bd_6e35_winsw_0,rtl
+bd_6e35_winsw_1,rtl
+bd_6e35_winsw_2,rtl
+bd_6e35_winsw_3,rtl
+bd_6e35_winsw_4,rtl
+bd_6e35_winsw_5,rtl
+bd_6e35_winsw_6,rtl
+bd_6e35_winsw_7,rtl
+bd_6e35_winsw_8,rtl
 bd_6e35_wni_0,rtl
-bd_6e35_woutsw_0,rtl
+bd_6e35_wni_1,rtl
+bd_6e35_wni_2,rtl
+bd_6e35_wni_3,rtl
+bd_6e35_wni_4,rtl
+bd_6e35_wni_5,rtl
+bd_6e35_wni_6,rtl
+bd_6e35_wni_7,rtl
 bd_962a_arsw_0,rtl
 bd_962a_awsw_0,rtl
 bd_962a_bsw_0,rtl
@@ -147,9 +316,23 @@ bd_962a_s01a2s_0,rtl
 bd_962a_s01mmu_0,rtl
 bd_962a_s01sic_0,rtl
 bd_962a_s01tr_0,rtl
+bd_962a_s02a2s_0,rtl
+bd_962a_s02mmu_0,rtl
+bd_962a_s02sic_0,rtl
+bd_962a_s02tr_0,rtl
+bd_962a_s03a2s_0,rtl
+bd_962a_s03mmu_0,rtl
+bd_962a_s03sic_0,rtl
+bd_962a_s03tr_0,rtl
 bd_962a_sarn_0,rtl
 bd_962a_sawn_0,rtl
+bd_962a_sawn_1,rtl
+bd_962a_sawn_2,rtl
 bd_962a_sbn_0,rtl
+bd_962a_sbn_1,rtl
+bd_962a_sbn_2,rtl
 bd_962a_srn_0,rtl
 bd_962a_swn_0,rtl
+bd_962a_swn_1,rtl
+bd_962a_swn_2,rtl
 bd_962a_wsw_0,rtl

c64_pro.cache/wt/project.wpc

@@ -1,4 +1,4 @@
 version:1
-57656254616c6b5472616e736d697373696f6e417474656d70746564:343
+57656254616c6b5472616e736d697373696f6e417474656d70746564:377
-6d6f64655f636f756e7465727c4755494d6f6465:242
+6d6f64655f636f756e7465727c4755494d6f6465:320
 eof:

c64_pro.cache/wt/synthesis.wdf

@@ -1,5 +1,5 @@
 version:1
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303130636c673430302d32:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303230636c673430302d32:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:63363470726f5f746f70:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
@@ -42,7 +42,7 @@ version:1
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a353873:00:00
+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30333a343173:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323738372e3637324d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323932372e3439324d42:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313239312e3931344d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313238312e3235384d42:00:00
-eof:2994962430
+eof:2555888587

c64_pro.cache/wt/webtalk_pa.xml

@@ -3,10 +3,10 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Sun Aug  4 13:38:06 2024">
+<application name="pa" timeStamp="Fri Sep  4 15:23:20 2026">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="49fe14c92914459aaee0d1ade43fb90b" type="ProjectID"/>
-<property name="ProjectIteration" value="424" type="ProjectIteration"/>
+<property name="ProjectIteration" value="469" type="ProjectIteration"/>
 </section>
 <section name="PlanAhead Usage" visible="true">
 <item name="Project Data">

c64_pro.cache/wt/xsim.wdf

@@ -0,0 +1,4 @@
+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
+eof:241934075

c64_pro.gen/sources_1/bd/design_a9_1/design_a9_1.bda

@@ -225,6 +225,42 @@
                 "TU": "memory"
             },
             "V5": {
+                "VT": "AC",
+                "BA": "0x00000000",
+                "HA": "0x1FFFFFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data_S2MM",
+                "MX": "/axi_dma_2",
+                "MI": "M_AXI_S2MM",
+                "MS": "SEG_processing_system7_0_HP0_DDR_LOWOCM",
+                "MV": "xilinx.com:ip:axi_dma:7.1",
+                "SX": "/processing_system7_0",
+                "SI": "S_AXI_HP0",
+                "SS": "HP0_DDR_LOWOCM",
+                "SV": "xilinx.com:ip:processing_system7:5.5",
+                "TM": "both",
+                "TU": "memory"
+            },
+            "V6": {
+                "VT": "AC",
+                "BA": "0x00000000",
+                "HA": "0x1FFFFFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data_S2MM",
+                "MX": "/axi_dma_3",
+                "MI": "M_AXI_S2MM",
+                "MS": "SEG_processing_system7_0_HP0_DDR_LOWOCM",
+                "MV": "xilinx.com:ip:axi_dma:7.1",
+                "SX": "/processing_system7_0",
+                "SI": "S_AXI_HP0",
+                "SS": "HP0_DDR_LOWOCM",
+                "SV": "xilinx.com:ip:processing_system7:5.5",
+                "TM": "both",
+                "TU": "memory"
+            },
+            "V7": {
                 "VT": "AC",
                 "BA": "0x40000000",
                 "HA": "0x40001FFF",
@@ -242,7 +278,7 @@
                 "TM": "both",
                 "TU": "memory"
             },
-            "V6": {
+            "V8": {
                 "VT": "AC",
                 "BA": "0x40400000",
                 "HA": "0x4040FFFF",
@@ -260,7 +296,7 @@
                 "TM": "both",
                 "TU": "register"
             },
-            "V7": {
+            "V9": {
                 "VT": "AC",
                 "BA": "0x40410000",
                 "HA": "0x4041FFFF",
@@ -278,7 +314,43 @@
                 "TM": "both",
                 "TU": "register"
             },
-            "V8": {
+            "V10": {
+                "VT": "AC",
+                "BA": "0x40420000",
+                "HA": "0x4042FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/processing_system7_0",
+                "MI": "M_AXI_GP0",
+                "MS": "SEG_axi_dma_2_Reg",
+                "MV": "xilinx.com:ip:processing_system7:5.5",
+                "SX": "/axi_dma_2",
+                "SI": "S_AXI_LITE",
+                "SS": "Reg",
+                "SV": "xilinx.com:ip:axi_dma:7.1",
+                "TM": "both",
+                "TU": "register"
+            },
+            "V11": {
+                "VT": "AC",
+                "BA": "0x40430000",
+                "HA": "0x4043FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/processing_system7_0",
+                "MI": "M_AXI_GP0",
+                "MS": "SEG_axi_dma_3_Reg",
+                "MV": "xilinx.com:ip:processing_system7:5.5",
+                "SX": "/axi_dma_3",
+                "SI": "S_AXI_LITE",
+                "SS": "Reg",
+                "SV": "xilinx.com:ip:axi_dma:7.1",
+                "TM": "both",
+                "TU": "register"
+            },
+            "V12": {
                 "VT": "AC",
                 "BA": "0x41200000",
                 "HA": "0x4120FFFF",
@@ -296,43 +368,169 @@
                 "TM": "both",
                 "TU": "register"
             },
-            "V9": {
+            "V13": {
                 "VT": "AC",
-                "BA": "0x41600000",
+                "BA": "0x41210000",
-                "HA": "0x4160FFFF",
+                "HA": "0x4121FFFF",
                 "BP": "C_BASEADDR",
                 "HP": "C_HIGHADDR",
                 "MA": "Data",
                 "MX": "/processing_system7_0",
                 "MI": "M_AXI_GP0",
-                "MS": "SEG_axi_iic_0_Reg",
+                "MS": "SEG_CHANN_EN_Reg",
                 "MV": "xilinx.com:ip:processing_system7:5.5",
-                "SX": "/axi_iic_0",
+                "SX": "/CHANN_EN",
                 "SI": "S_AXI",
                 "SS": "Reg",
-                "SV": "xilinx.com:ip:axi_iic:2.1",
+                "SV": "xilinx.com:ip:axi_gpio:2.0",
                 "TM": "both",
                 "TU": "register"
             },
-            "V10": {
+            "V14": {
                 "VT": "AC",
-                "BA": "0x41610000",
+                "BA": "0x41220000",
-                "HA": "0x4161FFFF",
+                "HA": "0x4122FFFF",
                 "BP": "C_BASEADDR",
                 "HP": "C_HIGHADDR",
                 "MA": "Data",
                 "MX": "/processing_system7_0",
                 "MI": "M_AXI_GP0",
-                "MS": "SEG_axi_iic_1_Reg",
+                "MS": "SEG_CHANN_SEL_Reg",
                 "MV": "xilinx.com:ip:processing_system7:5.5",
-                "SX": "/axi_iic_1",
+                "SX": "/CHANN_SEL",
                 "SI": "S_AXI",
                 "SS": "Reg",
-                "SV": "xilinx.com:ip:axi_iic:2.1",
+                "SV": "xilinx.com:ip:axi_gpio:2.0",
                 "TM": "both",
                 "TU": "register"
             },
-            "V11": {
+            "V15": {
+                "VT": "AC",
+                "BA": "0x41230000",
+                "HA": "0x4123FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/processing_system7_0",
+                "MI": "M_AXI_GP0",
+                "MS": "SEG_RST_AD5941_Reg",
+                "MV": "xilinx.com:ip:processing_system7:5.5",
+                "SX": "/RST_AD5941",
+                "SI": "S_AXI",
+                "SS": "Reg",
+                "SV": "xilinx.com:ip:axi_gpio:2.0",
+                "TM": "both",
+                "TU": "register"
+            },
+            "V16": {
+                "VT": "AC",
+                "BA": "0x41240000",
+                "HA": "0x4124FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/processing_system7_0",
+                "MI": "M_AXI_GP0",
+                "MS": "SEG_Z_IO_Reg",
+                "MV": "xilinx.com:ip:processing_system7:5.5",
+                "SX": "/Z_IO",
+                "SI": "S_AXI",
+                "SS": "Reg",
+                "SV": "xilinx.com:ip:axi_gpio:2.0",
+                "TM": "both",
+                "TU": "register"
+            },
+            "V17": {
+                "VT": "AC",
+                "BA": "0x41250000",
+                "HA": "0x4125FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/processing_system7_0",
+                "MI": "M_AXI_GP0",
+                "MS": "SEG_GPIO_Reg",
+                "MV": "xilinx.com:ip:processing_system7:5.5",
+                "SX": "/GPIO",
+                "SI": "S_AXI",
+                "SS": "Reg",
+                "SV": "xilinx.com:ip:axi_gpio:2.0",
+                "TM": "both",
+                "TU": "register"
+            },
+            "V18": {
+                "VT": "AC",
+                "BA": "0x41260000",
+                "HA": "0x4126FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/processing_system7_0",
+                "MI": "M_AXI_GP0",
+                "MS": "SEG_ELEC_MUX_IN_Reg",
+                "MV": "xilinx.com:ip:processing_system7:5.5",
+                "SX": "/ELEC_MUX_IN",
+                "SI": "S_AXI",
+                "SS": "Reg",
+                "SV": "xilinx.com:ip:axi_gpio:2.0",
+                "TM": "both",
+                "TU": "register"
+            },
+            "V19": {
+                "VT": "AC",
+                "BA": "0x41E00000",
+                "HA": "0x41E0FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/processing_system7_0",
+                "MI": "M_AXI_GP0",
+                "MS": "SEG_STIM_SPI_Reg",
+                "MV": "xilinx.com:ip:processing_system7:5.5",
+                "SX": "/STIM_SPI",
+                "SI": "AXI_LITE",
+                "SS": "Reg",
+                "SV": "xilinx.com:ip:axi_quad_spi:3.2",
+                "TM": "both",
+                "TU": "register"
+            },
+            "V20": {
+                "VT": "AC",
+                "BA": "0x41E10000",
+                "HA": "0x41E1FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/processing_system7_0",
+                "MI": "M_AXI_GP0",
+                "MS": "SEG_CUR_SPI_Reg",
+                "MV": "xilinx.com:ip:processing_system7:5.5",
+                "SX": "/CUR_SPI",
+                "SI": "AXI_LITE",
+                "SS": "Reg",
+                "SV": "xilinx.com:ip:axi_quad_spi:3.2",
+                "TM": "both",
+                "TU": "register"
+            },
+            "V21": {
+                "VT": "AC",
+                "BA": "0x41E20000",
+                "HA": "0x41E2FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/processing_system7_0",
+                "MI": "M_AXI_GP0",
+                "MS": "SEG_ZCHECK_SPI_Reg",
+                "MV": "xilinx.com:ip:processing_system7:5.5",
+                "SX": "/ZCHECK_SPI",
+                "SI": "AXI_LITE",
+                "SS": "Reg",
+                "SV": "xilinx.com:ip:axi_quad_spi:3.2",
+                "TM": "both",
+                "TU": "register"
+            },
+            "V22": {
                 "VT": "AC",
                 "BA": "0x42000000",
                 "HA": "0x42001FFF",
@@ -350,7 +548,7 @@
                 "TM": "both",
                 "TU": "memory"
             },
-            "V12": {
+            "V23": {
                 "VT": "AC",
                 "BA": "0x44000000",
                 "HA": "0x44001FFF",
@@ -368,7 +566,7 @@
                 "TM": "both",
                 "TU": "memory"
             },
-            "V13": {
+            "V24": {
                 "VT": "AC",
                 "BA": "0x46000000",
                 "HA": "0x46001FFF",
@@ -386,7 +584,7 @@
                 "TM": "both",
                 "TU": "memory"
             },
-            "V14": {
+            "V25": {
                 "VT": "AC",
                 "BA": "0x48000000",
                 "HA": "0x48001FFF",
@@ -403,6 +601,60 @@
                 "SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
                 "TM": "both",
                 "TU": "memory"
+            },
+            "V26": {
+                "VT": "AC",
+                "BA": "0x4A000000",
+                "HA": "0x4A001FFF",
+                "BP": "C_S_AXI_BASEADDR",
+                "HP": "C_S_AXI_HIGHADDR",
+                "MA": "Data",
+                "MX": "/processing_system7_0",
+                "MI": "M_AXI_GP0",
+                "MS": "SEG_axi_bram_ctrl_5_Mem0",
+                "MV": "xilinx.com:ip:processing_system7:5.5",
+                "SX": "/axi_bram_ctrl_5",
+                "SI": "S_AXI",
+                "SS": "Mem0",
+                "SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
+                "TM": "both",
+                "TU": "memory"
+            },
+            "V27": {
+                "VT": "AC",
+                "BA": "0x4C000000",
+                "HA": "0x4C001FFF",
+                "BP": "C_S_AXI_BASEADDR",
+                "HP": "C_S_AXI_HIGHADDR",
+                "MA": "Data",
+                "MX": "/processing_system7_0",
+                "MI": "M_AXI_GP0",
+                "MS": "SEG_axi_bram_ctrl_6_Mem0",
+                "MV": "xilinx.com:ip:processing_system7:5.5",
+                "SX": "/axi_bram_ctrl_6",
+                "SI": "S_AXI",
+                "SS": "Mem0",
+                "SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
+                "TM": "both",
+                "TU": "memory"
+            },
+            "V28": {
+                "VT": "AC",
+                "BA": "0x4E000000",
+                "HA": "0x4E001FFF",
+                "BP": "C_S_AXI_BASEADDR",
+                "HP": "C_S_AXI_HIGHADDR",
+                "MA": "Data",
+                "MX": "/processing_system7_0",
+                "MI": "M_AXI_GP0",
+                "MS": "SEG_axi_bram_ctrl_7_Mem0",
+                "MV": "xilinx.com:ip:processing_system7:5.5",
+                "SX": "/axi_bram_ctrl_7",
+                "SI": "S_AXI",
+                "SS": "Mem0",
+                "SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
+                "TM": "both",
+                "TU": "memory"
             }
         },
         "edges": [
@@ -473,6 +725,76 @@
                 "src": "V14",
                 "trg": "V2",
                 "EH": "2"
+            },
+            {
+                "src": "V15",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V16",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V17",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V18",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V19",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V20",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V21",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V22",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V23",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V24",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V25",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V26",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V27",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V28",
+                "trg": "V2",
+                "EH": "2"
             }
         ]
     }

c64_pro.gen/sources_1/bd/design_a9_1/design_a9_1.bxml

@@ -2,10 +2,10 @@
 <Root MajorVersion="0" MinorVersion="40">
   <CompositeFile CompositeFileTopName="design_a9_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
     <Description>Composite Fileset</Description>
-    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1714397435"/>
+    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1787204488"/>
-    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1714397435"/>
+    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1787204488"/>
-    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1714397435"/>
+    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1787204488"/>
-    <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1714397435"/>
+    <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1787204488"/>
     <FileCollection Name="SOURCES" Type="SOURCES">
       <File Name="synth\design_a9_1.v" Type="Verilog">
         <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>

c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v

@@ -2,8 +2,8 @@
 //Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 //--------------------------------------------------------------------------------
 //Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
-//Date        : Mon Apr 29 21:29:57 2024
+//Date        : Thu Aug 20 13:40:13 2026
-//Host        : 840-5CG14025H4 running 64-bit major release  (build 9200)
+//Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
 //Command     : generate_target design_a9_1_wrapper.bd
 //Design      : design_a9_1_wrapper
 //Purpose     : IP block netlist
@@ -11,7 +11,9 @@
 `timescale 1 ps / 1 ps
 
 module design_a9_1_wrapper
-   (DDR_addr,
+   (CHANN_EN_tri_io,
+    CHANN_SEL_tri_io,
+    DDR_addr,
     DDR_ba,
     DDR_cas_n,
     DDR_ck_n,
@@ -32,6 +34,15 @@ module design_a9_1_wrapper
     FIXED_IO_ps_clk,
     FIXED_IO_ps_porb,
     FIXED_IO_ps_srstb,
+    RST_AD5941_tri_io,
+    Z_IO_tri_io,
+    bram_cur_addr,
+    bram_cur_clk,
+    bram_cur_din,
+    bram_cur_dout,
+    bram_cur_en,
+    bram_cur_rst,
+    bram_cur_we,
     bram_eeg_addr,
     bram_eeg_clk,
     bram_eeg_din,
@@ -46,6 +57,13 @@ module design_a9_1_wrapper
     bram_emg_en,
     bram_emg_rst,
     bram_emg_we,
+    bram_imp_addr,
+    bram_imp_clk,
+    bram_imp_din,
+    bram_imp_dout,
+    bram_imp_en,
+    bram_imp_rst,
+    bram_imp_we,
     bram_mems_addr,
     bram_mems_clk,
     bram_mems_din,
@@ -57,6 +75,13 @@ module design_a9_1_wrapper
     bram_msg_clk,
     bram_msg_din,
     bram_msg_dout,
+    bram_msg_emg_addr,
+    bram_msg_emg_clk,
+    bram_msg_emg_din,
+    bram_msg_emg_dout,
+    bram_msg_emg_en,
+    bram_msg_emg_rst,
+    bram_msg_emg_we,
     bram_msg_en,
     bram_msg_rst,
     bram_msg_we,
@@ -68,12 +93,14 @@ module design_a9_1_wrapper
     bram_stim_rst,
     bram_stim_we,
     clk,
+    cur_spi_io0_io,
+    cur_spi_io1_io,
+    cur_spi_sck_io,
+    cur_spi_ss_io,
+    elec_mux_in_tri_io,
     gpio0_0_tri_i,
     gpio0_1_tri_o,
-    iic0_scl_io,
+    gpio0_tri_io,
-    iic0_sda_io,
-    iic1_scl_io,
-    iic1_sda_io,
     int0,
     int1,
     int2,
@@ -83,12 +110,34 @@ module design_a9_1_wrapper
     m_axis_stim_tready,
     m_axis_stim_tvalid,
     rst_n,
+    s_axis_record1_tdata,
+    s_axis_record1_tkeep,
+    s_axis_record1_tlast,
+    s_axis_record1_tready,
+    s_axis_record1_tvalid,
+    s_axis_record2_tdata,
+    s_axis_record2_tkeep,
+    s_axis_record2_tlast,
+    s_axis_record2_tready,
+    s_axis_record2_tvalid,
     s_axis_record_tdata,
     s_axis_record_tfull,
+    s_axis_record_tfull1,
+    s_axis_record_tfull2,
     s_axis_record_tkeep,
     s_axis_record_tlast,
     s_axis_record_tready,
-    s_axis_record_tvalid);
+    s_axis_record_tvalid,
+    stim_spi_io0_io,
+    stim_spi_io1_io,
+    stim_spi_sck_io,
+    stim_spi_ss_io,
+    zcheck_spi_io0_io,
+    zcheck_spi_io1_io,
+    zcheck_spi_sck_io,
+    zcheck_spi_ss_io);
+  inout [1:0]CHANN_EN_tri_io;
+  inout [3:0]CHANN_SEL_tri_io;
   inout [14:0]DDR_addr;
   inout [2:0]DDR_ba;
   inout DDR_cas_n;
@@ -110,6 +159,15 @@ module design_a9_1_wrapper
   inout FIXED_IO_ps_clk;
   inout FIXED_IO_ps_porb;
   inout FIXED_IO_ps_srstb;
+  inout [0:0]RST_AD5941_tri_io;
+  inout [0:0]Z_IO_tri_io;
+  output [12:0]bram_cur_addr;
+  output bram_cur_clk;
+  output [31:0]bram_cur_din;
+  input [31:0]bram_cur_dout;
+  output bram_cur_en;
+  output bram_cur_rst;
+  output [3:0]bram_cur_we;
   output [12:0]bram_eeg_addr;
   output bram_eeg_clk;
   output [31:0]bram_eeg_din;
@@ -124,6 +182,13 @@ module design_a9_1_wrapper
   output bram_emg_en;
   output bram_emg_rst;
   output [3:0]bram_emg_we;
+  output [12:0]bram_imp_addr;
+  output bram_imp_clk;
+  output [31:0]bram_imp_din;
+  input [31:0]bram_imp_dout;
+  output bram_imp_en;
+  output bram_imp_rst;
+  output [3:0]bram_imp_we;
   output [12:0]bram_mems_addr;
   output bram_mems_clk;
   output [31:0]bram_mems_din;
@@ -135,6 +200,13 @@ module design_a9_1_wrapper
   output bram_msg_clk;
   output [31:0]bram_msg_din;
   input [31:0]bram_msg_dout;
+  output [12:0]bram_msg_emg_addr;
+  output bram_msg_emg_clk;
+  output [31:0]bram_msg_emg_din;
+  input [31:0]bram_msg_emg_dout;
+  output bram_msg_emg_en;
+  output bram_msg_emg_rst;
+  output [3:0]bram_msg_emg_we;
   output bram_msg_en;
   output bram_msg_rst;
   output [3:0]bram_msg_we;
@@ -146,12 +218,14 @@ module design_a9_1_wrapper
   output bram_stim_rst;
   output [3:0]bram_stim_we;
   output clk;
+  inout cur_spi_io0_io;
+  inout cur_spi_io1_io;
+  inout cur_spi_sck_io;
+  inout [0:0]cur_spi_ss_io;
+  inout [3:0]elec_mux_in_tri_io;
   input [7:0]gpio0_0_tri_i;
   output [31:0]gpio0_1_tri_o;
-  inout iic0_scl_io;
+  inout [2:0]gpio0_tri_io;
-  inout iic0_sda_io;
-  inout iic1_scl_io;
-  inout iic1_sda_io;
   input int0;
   input int1;
   input int2;
@@ -161,13 +235,57 @@ module design_a9_1_wrapper
   input m_axis_stim_tready;
   output m_axis_stim_tvalid;
   output [0:0]rst_n;
+  input [31:0]s_axis_record1_tdata;
+  input [3:0]s_axis_record1_tkeep;
+  input s_axis_record1_tlast;
+  output s_axis_record1_tready;
+  input s_axis_record1_tvalid;
+  input [31:0]s_axis_record2_tdata;
+  input [3:0]s_axis_record2_tkeep;
+  input s_axis_record2_tlast;
+  output s_axis_record2_tready;
+  input s_axis_record2_tvalid;
   input [7:0]s_axis_record_tdata;
   output s_axis_record_tfull;
+  output s_axis_record_tfull1;
+  output s_axis_record_tfull2;
   input [0:0]s_axis_record_tkeep;
   input s_axis_record_tlast;
   output s_axis_record_tready;
   input s_axis_record_tvalid;
+  inout stim_spi_io0_io;
+  inout stim_spi_io1_io;
+  inout stim_spi_sck_io;
+  inout [0:0]stim_spi_ss_io;
+  inout zcheck_spi_io0_io;
+  inout zcheck_spi_io1_io;
+  inout zcheck_spi_sck_io;
+  inout [0:0]zcheck_spi_ss_io;
 
+  wire [0:0]CHANN_EN_tri_i_0;
+  wire [1:1]CHANN_EN_tri_i_1;
+  wire [0:0]CHANN_EN_tri_io_0;
+  wire [1:1]CHANN_EN_tri_io_1;
+  wire [0:0]CHANN_EN_tri_o_0;
+  wire [1:1]CHANN_EN_tri_o_1;
+  wire [0:0]CHANN_EN_tri_t_0;
+  wire [1:1]CHANN_EN_tri_t_1;
+  wire [0:0]CHANN_SEL_tri_i_0;
+  wire [1:1]CHANN_SEL_tri_i_1;
+  wire [2:2]CHANN_SEL_tri_i_2;
+  wire [3:3]CHANN_SEL_tri_i_3;
+  wire [0:0]CHANN_SEL_tri_io_0;
+  wire [1:1]CHANN_SEL_tri_io_1;
+  wire [2:2]CHANN_SEL_tri_io_2;
+  wire [3:3]CHANN_SEL_tri_io_3;
+  wire [0:0]CHANN_SEL_tri_o_0;
+  wire [1:1]CHANN_SEL_tri_o_1;
+  wire [2:2]CHANN_SEL_tri_o_2;
+  wire [3:3]CHANN_SEL_tri_o_3;
+  wire [0:0]CHANN_SEL_tri_t_0;
+  wire [1:1]CHANN_SEL_tri_t_1;
+  wire [2:2]CHANN_SEL_tri_t_2;
+  wire [3:3]CHANN_SEL_tri_t_3;
   wire [14:0]DDR_addr;
   wire [2:0]DDR_ba;
   wire DDR_cas_n;
@@ -189,6 +307,21 @@ module design_a9_1_wrapper
   wire FIXED_IO_ps_clk;
   wire FIXED_IO_ps_porb;
   wire FIXED_IO_ps_srstb;
+  wire [0:0]RST_AD5941_tri_i_0;
+  wire [0:0]RST_AD5941_tri_io_0;
+  wire [0:0]RST_AD5941_tri_o_0;
+  wire [0:0]RST_AD5941_tri_t_0;
+  wire [0:0]Z_IO_tri_i_0;
+  wire [0:0]Z_IO_tri_io_0;
+  wire [0:0]Z_IO_tri_o_0;
+  wire [0:0]Z_IO_tri_t_0;
+  wire [12:0]bram_cur_addr;
+  wire bram_cur_clk;
+  wire [31:0]bram_cur_din;
+  wire [31:0]bram_cur_dout;
+  wire bram_cur_en;
+  wire bram_cur_rst;
+  wire [3:0]bram_cur_we;
   wire [12:0]bram_eeg_addr;
   wire bram_eeg_clk;
   wire [31:0]bram_eeg_din;
@@ -203,6 +336,13 @@ module design_a9_1_wrapper
   wire bram_emg_en;
   wire bram_emg_rst;
   wire [3:0]bram_emg_we;
+  wire [12:0]bram_imp_addr;
+  wire bram_imp_clk;
+  wire [31:0]bram_imp_din;
+  wire [31:0]bram_imp_dout;
+  wire bram_imp_en;
+  wire bram_imp_rst;
+  wire [3:0]bram_imp_we;
   wire [12:0]bram_mems_addr;
   wire bram_mems_clk;
   wire [31:0]bram_mems_din;
@@ -214,6 +354,13 @@ module design_a9_1_wrapper
   wire bram_msg_clk;
   wire [31:0]bram_msg_din;
   wire [31:0]bram_msg_dout;
+  wire [12:0]bram_msg_emg_addr;
+  wire bram_msg_emg_clk;
+  wire [31:0]bram_msg_emg_din;
+  wire [31:0]bram_msg_emg_dout;
+  wire bram_msg_emg_en;
+  wire bram_msg_emg_rst;
+  wire [3:0]bram_msg_emg_we;
   wire bram_msg_en;
   wire bram_msg_rst;
   wire [3:0]bram_msg_we;
@@ -225,24 +372,52 @@ module design_a9_1_wrapper
   wire bram_stim_rst;
   wire [3:0]bram_stim_we;
   wire clk;
+  wire cur_spi_io0_i;
+  wire cur_spi_io0_io;
+  wire cur_spi_io0_o;
+  wire cur_spi_io0_t;
+  wire cur_spi_io1_i;
+  wire cur_spi_io1_io;
+  wire cur_spi_io1_o;
+  wire cur_spi_io1_t;
+  wire cur_spi_sck_i;
+  wire cur_spi_sck_io;
+  wire cur_spi_sck_o;
+  wire cur_spi_sck_t;
+  wire [0:0]cur_spi_ss_i_0;
+  wire [0:0]cur_spi_ss_io_0;
+  wire [0:0]cur_spi_ss_o_0;
+  wire cur_spi_ss_t;
+  wire [0:0]elec_mux_in_tri_i_0;
+  wire [1:1]elec_mux_in_tri_i_1;
+  wire [2:2]elec_mux_in_tri_i_2;
+  wire [3:3]elec_mux_in_tri_i_3;
+  wire [0:0]elec_mux_in_tri_io_0;
+  wire [1:1]elec_mux_in_tri_io_1;
+  wire [2:2]elec_mux_in_tri_io_2;
+  wire [3:3]elec_mux_in_tri_io_3;
+  wire [0:0]elec_mux_in_tri_o_0;
+  wire [1:1]elec_mux_in_tri_o_1;
+  wire [2:2]elec_mux_in_tri_o_2;
+  wire [3:3]elec_mux_in_tri_o_3;
+  wire [0:0]elec_mux_in_tri_t_0;
+  wire [1:1]elec_mux_in_tri_t_1;
+  wire [2:2]elec_mux_in_tri_t_2;
+  wire [3:3]elec_mux_in_tri_t_3;
   wire [7:0]gpio0_0_tri_i;
   wire [31:0]gpio0_1_tri_o;
-  wire iic0_scl_i;
+  wire [0:0]gpio0_tri_i_0;
-  wire iic0_scl_io;
+  wire [1:1]gpio0_tri_i_1;
-  wire iic0_scl_o;
+  wire [2:2]gpio0_tri_i_2;
-  wire iic0_scl_t;
+  wire [0:0]gpio0_tri_io_0;
-  wire iic0_sda_i;
+  wire [1:1]gpio0_tri_io_1;
-  wire iic0_sda_io;
+  wire [2:2]gpio0_tri_io_2;
-  wire iic0_sda_o;
+  wire [0:0]gpio0_tri_o_0;
-  wire iic0_sda_t;
+  wire [1:1]gpio0_tri_o_1;
-  wire iic1_scl_i;
+  wire [2:2]gpio0_tri_o_2;
-  wire iic1_scl_io;
+  wire [0:0]gpio0_tri_t_0;
-  wire iic1_scl_o;
+  wire [1:1]gpio0_tri_t_1;
-  wire iic1_scl_t;
+  wire [2:2]gpio0_tri_t_2;
-  wire iic1_sda_i;
-  wire iic1_sda_io;
-  wire iic1_sda_o;
-  wire iic1_sda_t;
   wire int0;
   wire int1;
   wire int2;
@@ -252,15 +427,125 @@ module design_a9_1_wrapper
   wire m_axis_stim_tready;
   wire m_axis_stim_tvalid;
   wire [0:0]rst_n;
+  wire [31:0]s_axis_record1_tdata;
+  wire [3:0]s_axis_record1_tkeep;
+  wire s_axis_record1_tlast;
+  wire s_axis_record1_tready;
+  wire s_axis_record1_tvalid;
+  wire [31:0]s_axis_record2_tdata;
+  wire [3:0]s_axis_record2_tkeep;
+  wire s_axis_record2_tlast;
+  wire s_axis_record2_tready;
+  wire s_axis_record2_tvalid;
   wire [7:0]s_axis_record_tdata;
   wire s_axis_record_tfull;
+  wire s_axis_record_tfull1;
+  wire s_axis_record_tfull2;
   wire [0:0]s_axis_record_tkeep;
   wire s_axis_record_tlast;
   wire s_axis_record_tready;
   wire s_axis_record_tvalid;
+  wire stim_spi_io0_i;
+  wire stim_spi_io0_io;
+  wire stim_spi_io0_o;
+  wire stim_spi_io0_t;
+  wire stim_spi_io1_i;
+  wire stim_spi_io1_io;
+  wire stim_spi_io1_o;
+  wire stim_spi_io1_t;
+  wire stim_spi_sck_i;
+  wire stim_spi_sck_io;
+  wire stim_spi_sck_o;
+  wire stim_spi_sck_t;
+  wire [0:0]stim_spi_ss_i_0;
+  wire [0:0]stim_spi_ss_io_0;
+  wire [0:0]stim_spi_ss_o_0;
+  wire stim_spi_ss_t;
+  wire zcheck_spi_io0_i;
+  wire zcheck_spi_io0_io;
+  wire zcheck_spi_io0_o;
+  wire zcheck_spi_io0_t;
+  wire zcheck_spi_io1_i;
+  wire zcheck_spi_io1_io;
+  wire zcheck_spi_io1_o;
+  wire zcheck_spi_io1_t;
+  wire zcheck_spi_sck_i;
+  wire zcheck_spi_sck_io;
+  wire zcheck_spi_sck_o;
+  wire zcheck_spi_sck_t;
+  wire [0:0]zcheck_spi_ss_i_0;
+  wire [0:0]zcheck_spi_ss_io_0;
+  wire [0:0]zcheck_spi_ss_o_0;
+  wire zcheck_spi_ss_t;
 
+  IOBUF CHANN_EN_tri_iobuf_0
+       (.I(CHANN_EN_tri_o_0),
+        .IO(CHANN_EN_tri_io[0]),
+        .O(CHANN_EN_tri_i_0),
+        .T(CHANN_EN_tri_t_0));
+  IOBUF CHANN_EN_tri_iobuf_1
+       (.I(CHANN_EN_tri_o_1),
+        .IO(CHANN_EN_tri_io[1]),
+        .O(CHANN_EN_tri_i_1),
+        .T(CHANN_EN_tri_t_1));
+  IOBUF CHANN_SEL_tri_iobuf_0
+       (.I(CHANN_SEL_tri_o_0),
+        .IO(CHANN_SEL_tri_io[0]),
+        .O(CHANN_SEL_tri_i_0),
+        .T(CHANN_SEL_tri_t_0));
+  IOBUF CHANN_SEL_tri_iobuf_1
+       (.I(CHANN_SEL_tri_o_1),
+        .IO(CHANN_SEL_tri_io[1]),
+        .O(CHANN_SEL_tri_i_1),
+        .T(CHANN_SEL_tri_t_1));
+  IOBUF CHANN_SEL_tri_iobuf_2
+       (.I(CHANN_SEL_tri_o_2),
+        .IO(CHANN_SEL_tri_io[2]),
+        .O(CHANN_SEL_tri_i_2),
+        .T(CHANN_SEL_tri_t_2));
+  IOBUF CHANN_SEL_tri_iobuf_3
+       (.I(CHANN_SEL_tri_o_3),
+        .IO(CHANN_SEL_tri_io[3]),
+        .O(CHANN_SEL_tri_i_3),
+        .T(CHANN_SEL_tri_t_3));
+  IOBUF RST_AD5941_tri_iobuf_0
+       (.I(RST_AD5941_tri_o_0),
+        .IO(RST_AD5941_tri_io[0]),
+        .O(RST_AD5941_tri_i_0),
+        .T(RST_AD5941_tri_t_0));
+  IOBUF Z_IO_tri_iobuf_0
+       (.I(Z_IO_tri_o_0),
+        .IO(Z_IO_tri_io[0]),
+        .O(Z_IO_tri_i_0),
+        .T(Z_IO_tri_t_0));
+  IOBUF cur_spi_io0_iobuf
+       (.I(cur_spi_io0_o),
+        .IO(cur_spi_io0_io),
+        .O(cur_spi_io0_i),
+        .T(cur_spi_io0_t));
+  IOBUF cur_spi_io1_iobuf
+       (.I(cur_spi_io1_o),
+        .IO(cur_spi_io1_io),
+        .O(cur_spi_io1_i),
+        .T(cur_spi_io1_t));
+  IOBUF cur_spi_sck_iobuf
+       (.I(cur_spi_sck_o),
+        .IO(cur_spi_sck_io),
+        .O(cur_spi_sck_i),
+        .T(cur_spi_sck_t));
+  IOBUF cur_spi_ss_iobuf_0
+       (.I(cur_spi_ss_o_0),
+        .IO(cur_spi_ss_io[0]),
+        .O(cur_spi_ss_i_0),
+        .T(cur_spi_ss_t));
   design_a9_1 design_a9_1_i
-       (.DDR_addr(DDR_addr),
+       (.CHANN_EN_tri_i({CHANN_EN_tri_i_1,CHANN_EN_tri_i_0}),
+        .CHANN_EN_tri_o({CHANN_EN_tri_o_1,CHANN_EN_tri_o_0}),
+        .CHANN_EN_tri_t({CHANN_EN_tri_t_1,CHANN_EN_tri_t_0}),
+        .CHANN_SEL_tri_i({CHANN_SEL_tri_i_3,CHANN_SEL_tri_i_2,CHANN_SEL_tri_i_1,CHANN_SEL_tri_i_0}),
+        .CHANN_SEL_tri_o({CHANN_SEL_tri_o_3,CHANN_SEL_tri_o_2,CHANN_SEL_tri_o_1,CHANN_SEL_tri_o_0}),
+        .CHANN_SEL_tri_t({CHANN_SEL_tri_t_3,CHANN_SEL_tri_t_2,CHANN_SEL_tri_t_1,CHANN_SEL_tri_t_0}),
+        .DDR_addr(DDR_addr),
         .DDR_ba(DDR_ba),
         .DDR_cas_n(DDR_cas_n),
         .DDR_ck_n(DDR_ck_n),
@@ -281,6 +566,19 @@ module design_a9_1_wrapper
         .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
         .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
         .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
+        .RST_AD5941_tri_i(RST_AD5941_tri_i_0),
+        .RST_AD5941_tri_o(RST_AD5941_tri_o_0),
+        .RST_AD5941_tri_t(RST_AD5941_tri_t_0),
+        .Z_IO_tri_i(Z_IO_tri_i_0),
+        .Z_IO_tri_o(Z_IO_tri_o_0),
+        .Z_IO_tri_t(Z_IO_tri_t_0),
+        .bram_cur_addr(bram_cur_addr),
+        .bram_cur_clk(bram_cur_clk),
+        .bram_cur_din(bram_cur_din),
+        .bram_cur_dout(bram_cur_dout),
+        .bram_cur_en(bram_cur_en),
+        .bram_cur_rst(bram_cur_rst),
+        .bram_cur_we(bram_cur_we),
         .bram_eeg_addr(bram_eeg_addr),
         .bram_eeg_clk(bram_eeg_clk),
         .bram_eeg_din(bram_eeg_din),
@@ -295,6 +593,13 @@ module design_a9_1_wrapper
         .bram_emg_en(bram_emg_en),
         .bram_emg_rst(bram_emg_rst),
         .bram_emg_we(bram_emg_we),
+        .bram_imp_addr(bram_imp_addr),
+        .bram_imp_clk(bram_imp_clk),
+        .bram_imp_din(bram_imp_din),
+        .bram_imp_dout(bram_imp_dout),
+        .bram_imp_en(bram_imp_en),
+        .bram_imp_rst(bram_imp_rst),
+        .bram_imp_we(bram_imp_we),
         .bram_mems_addr(bram_mems_addr),
         .bram_mems_clk(bram_mems_clk),
         .bram_mems_din(bram_mems_din),
@@ -306,6 +611,13 @@ module design_a9_1_wrapper
         .bram_msg_clk(bram_msg_clk),
         .bram_msg_din(bram_msg_din),
         .bram_msg_dout(bram_msg_dout),
+        .bram_msg_emg_addr(bram_msg_emg_addr),
+        .bram_msg_emg_clk(bram_msg_emg_clk),
+        .bram_msg_emg_din(bram_msg_emg_din),
+        .bram_msg_emg_dout(bram_msg_emg_dout),
+        .bram_msg_emg_en(bram_msg_emg_en),
+        .bram_msg_emg_rst(bram_msg_emg_rst),
+        .bram_msg_emg_we(bram_msg_emg_we),
         .bram_msg_en(bram_msg_en),
         .bram_msg_rst(bram_msg_rst),
         .bram_msg_we(bram_msg_we),
@@ -317,20 +629,26 @@ module design_a9_1_wrapper
         .bram_stim_rst(bram_stim_rst),
         .bram_stim_we(bram_stim_we),
         .clk(clk),
+        .cur_spi_io0_i(cur_spi_io0_i),
+        .cur_spi_io0_o(cur_spi_io0_o),
+        .cur_spi_io0_t(cur_spi_io0_t),
+        .cur_spi_io1_i(cur_spi_io1_i),
+        .cur_spi_io1_o(cur_spi_io1_o),
+        .cur_spi_io1_t(cur_spi_io1_t),
+        .cur_spi_sck_i(cur_spi_sck_i),
+        .cur_spi_sck_o(cur_spi_sck_o),
+        .cur_spi_sck_t(cur_spi_sck_t),
+        .cur_spi_ss_i(cur_spi_ss_i_0),
+        .cur_spi_ss_o(cur_spi_ss_o_0),
+        .cur_spi_ss_t(cur_spi_ss_t),
+        .elec_mux_in_tri_i({elec_mux_in_tri_i_3,elec_mux_in_tri_i_2,elec_mux_in_tri_i_1,elec_mux_in_tri_i_0}),
+        .elec_mux_in_tri_o({elec_mux_in_tri_o_3,elec_mux_in_tri_o_2,elec_mux_in_tri_o_1,elec_mux_in_tri_o_0}),
+        .elec_mux_in_tri_t({elec_mux_in_tri_t_3,elec_mux_in_tri_t_2,elec_mux_in_tri_t_1,elec_mux_in_tri_t_0}),
         .gpio0_0_tri_i(gpio0_0_tri_i),
         .gpio0_1_tri_o(gpio0_1_tri_o),
-        .iic0_scl_i(iic0_scl_i),
+        .gpio0_tri_i({gpio0_tri_i_2,gpio0_tri_i_1,gpio0_tri_i_0}),
-        .iic0_scl_o(iic0_scl_o),
+        .gpio0_tri_o({gpio0_tri_o_2,gpio0_tri_o_1,gpio0_tri_o_0}),
-        .iic0_scl_t(iic0_scl_t),
+        .gpio0_tri_t({gpio0_tri_t_2,gpio0_tri_t_1,gpio0_tri_t_0}),
-        .iic0_sda_i(iic0_sda_i),
-        .iic0_sda_o(iic0_sda_o),
-        .iic0_sda_t(iic0_sda_t),
-        .iic1_scl_i(iic1_scl_i),
-        .iic1_scl_o(iic1_scl_o),
-        .iic1_scl_t(iic1_scl_t),
-        .iic1_sda_i(iic1_sda_i),
-        .iic1_sda_o(iic1_sda_o),
-        .iic1_sda_t(iic1_sda_t),
         .int0(int0),
         .int1(int1),
         .int2(int2),
@@ -340,30 +658,121 @@ module design_a9_1_wrapper
         .m_axis_stim_tready(m_axis_stim_tready),
         .m_axis_stim_tvalid(m_axis_stim_tvalid),
         .rst_n(rst_n),
+        .s_axis_record1_tdata(s_axis_record1_tdata),
+        .s_axis_record1_tkeep(s_axis_record1_tkeep),
+        .s_axis_record1_tlast(s_axis_record1_tlast),
+        .s_axis_record1_tready(s_axis_record1_tready),
+        .s_axis_record1_tvalid(s_axis_record1_tvalid),
+        .s_axis_record2_tdata(s_axis_record2_tdata),
+        .s_axis_record2_tkeep(s_axis_record2_tkeep),
+        .s_axis_record2_tlast(s_axis_record2_tlast),
+        .s_axis_record2_tready(s_axis_record2_tready),
+        .s_axis_record2_tvalid(s_axis_record2_tvalid),
         .s_axis_record_tdata(s_axis_record_tdata),
         .s_axis_record_tfull(s_axis_record_tfull),
+        .s_axis_record_tfull1(s_axis_record_tfull1),
+        .s_axis_record_tfull2(s_axis_record_tfull2),
         .s_axis_record_tkeep(s_axis_record_tkeep),
         .s_axis_record_tlast(s_axis_record_tlast),
         .s_axis_record_tready(s_axis_record_tready),
-        .s_axis_record_tvalid(s_axis_record_tvalid));
+        .s_axis_record_tvalid(s_axis_record_tvalid),
-  IOBUF iic0_scl_iobuf
+        .stim_spi_io0_i(stim_spi_io0_i),
-       (.I(iic0_scl_o),
+        .stim_spi_io0_o(stim_spi_io0_o),
-        .IO(iic0_scl_io),
+        .stim_spi_io0_t(stim_spi_io0_t),
-        .O(iic0_scl_i),
+        .stim_spi_io1_i(stim_spi_io1_i),
-        .T(iic0_scl_t));
+        .stim_spi_io1_o(stim_spi_io1_o),
-  IOBUF iic0_sda_iobuf
+        .stim_spi_io1_t(stim_spi_io1_t),
-       (.I(iic0_sda_o),
+        .stim_spi_sck_i(stim_spi_sck_i),
-        .IO(iic0_sda_io),
+        .stim_spi_sck_o(stim_spi_sck_o),
-        .O(iic0_sda_i),
+        .stim_spi_sck_t(stim_spi_sck_t),
-        .T(iic0_sda_t));
+        .stim_spi_ss_i(stim_spi_ss_i_0),
-  IOBUF iic1_scl_iobuf
+        .stim_spi_ss_o(stim_spi_ss_o_0),
-       (.I(iic1_scl_o),
+        .stim_spi_ss_t(stim_spi_ss_t),
-        .IO(iic1_scl_io),
+        .zcheck_spi_io0_i(zcheck_spi_io0_i),
-        .O(iic1_scl_i),
+        .zcheck_spi_io0_o(zcheck_spi_io0_o),
-        .T(iic1_scl_t));
+        .zcheck_spi_io0_t(zcheck_spi_io0_t),
-  IOBUF iic1_sda_iobuf
+        .zcheck_spi_io1_i(zcheck_spi_io1_i),
-       (.I(iic1_sda_o),
+        .zcheck_spi_io1_o(zcheck_spi_io1_o),
-        .IO(iic1_sda_io),
+        .zcheck_spi_io1_t(zcheck_spi_io1_t),
-        .O(iic1_sda_i),
+        .zcheck_spi_sck_i(zcheck_spi_sck_i),
-        .T(iic1_sda_t));
+        .zcheck_spi_sck_o(zcheck_spi_sck_o),
+        .zcheck_spi_sck_t(zcheck_spi_sck_t),
+        .zcheck_spi_ss_i(zcheck_spi_ss_i_0),
+        .zcheck_spi_ss_o(zcheck_spi_ss_o_0),
+        .zcheck_spi_ss_t(zcheck_spi_ss_t));
+  IOBUF elec_mux_in_tri_iobuf_0
+       (.I(elec_mux_in_tri_o_0),
+        .IO(elec_mux_in_tri_io[0]),
+        .O(elec_mux_in_tri_i_0),
+        .T(elec_mux_in_tri_t_0));
+  IOBUF elec_mux_in_tri_iobuf_1
+       (.I(elec_mux_in_tri_o_1),
+        .IO(elec_mux_in_tri_io[1]),
+        .O(elec_mux_in_tri_i_1),
+        .T(elec_mux_in_tri_t_1));
+  IOBUF elec_mux_in_tri_iobuf_2
+       (.I(elec_mux_in_tri_o_2),
+        .IO(elec_mux_in_tri_io[2]),
+        .O(elec_mux_in_tri_i_2),
+        .T(elec_mux_in_tri_t_2));
+  IOBUF elec_mux_in_tri_iobuf_3
+       (.I(elec_mux_in_tri_o_3),
+        .IO(elec_mux_in_tri_io[3]),
+        .O(elec_mux_in_tri_i_3),
+        .T(elec_mux_in_tri_t_3));
+  IOBUF gpio0_tri_iobuf_0
+       (.I(gpio0_tri_o_0),
+        .IO(gpio0_tri_io[0]),
+        .O(gpio0_tri_i_0),
+        .T(gpio0_tri_t_0));
+  IOBUF gpio0_tri_iobuf_1
+       (.I(gpio0_tri_o_1),
+        .IO(gpio0_tri_io[1]),
+        .O(gpio0_tri_i_1),
+        .T(gpio0_tri_t_1));
+  IOBUF gpio0_tri_iobuf_2
+       (.I(gpio0_tri_o_2),
+        .IO(gpio0_tri_io[2]),
+        .O(gpio0_tri_i_2),
+        .T(gpio0_tri_t_2));
+  IOBUF stim_spi_io0_iobuf
+       (.I(stim_spi_io0_o),
+        .IO(stim_spi_io0_io),
+        .O(stim_spi_io0_i),
+        .T(stim_spi_io0_t));
+  IOBUF stim_spi_io1_iobuf
+       (.I(stim_spi_io1_o),
+        .IO(stim_spi_io1_io),
+        .O(stim_spi_io1_i),
+        .T(stim_spi_io1_t));
+  IOBUF stim_spi_sck_iobuf
+       (.I(stim_spi_sck_o),
+        .IO(stim_spi_sck_io),
+        .O(stim_spi_sck_i),
+        .T(stim_spi_sck_t));
+  IOBUF stim_spi_ss_iobuf_0
+       (.I(stim_spi_ss_o_0),
+        .IO(stim_spi_ss_io[0]),
+        .O(stim_spi_ss_i_0),
+        .T(stim_spi_ss_t));
+  IOBUF zcheck_spi_io0_iobuf
+       (.I(zcheck_spi_io0_o),
+        .IO(zcheck_spi_io0_io),
+        .O(zcheck_spi_io0_i),
+        .T(zcheck_spi_io0_t));
+  IOBUF zcheck_spi_io1_iobuf
+       (.I(zcheck_spi_io1_o),
+        .IO(zcheck_spi_io1_io),
+        .O(zcheck_spi_io1_i),
+        .T(zcheck_spi_io1_t));
+  IOBUF zcheck_spi_sck_iobuf
+       (.I(zcheck_spi_sck_o),
+        .IO(zcheck_spi_sck_io),
+        .O(zcheck_spi_sck_i),
+        .T(zcheck_spi_sck_t));
+  IOBUF zcheck_spi_ss_iobuf_0
+       (.I(zcheck_spi_ss_o_0),
+        .IO(zcheck_spi_ss_io[0]),
+        .O(zcheck_spi_ss_i_0),
+        .T(zcheck_spi_ss_t));
 endmodule

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xdc

@@ -0,0 +1,48 @@
+# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+set_false_path -to [get_pins -hier *cdc_to*/D]
+

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_board.xdc

@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_ooc.xdc

@@ -0,0 +1,62 @@
+
+################################################################################
+# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# User should update the correct clock period before proceeding further
+# This constraints file contains default clock frequencies to be used during 
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs. 
+# For best results the frequencies should be modified# to match the target 
+# frequencies. 
+
+
+ create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
+## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
+
+################################################################################

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_stub.v

@@ -0,0 +1,46 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Tue Oct 28 21:02:58 2025
+// Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top design_a9_1_CHANN_EN_0 -prefix
+//               design_a9_1_CHANN_EN_0_ design_a9_1_axi_gpio_1_0_stub.v
+// Design      : design_a9_1_axi_gpio_1_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axi_gpio,Vivado 2023.1" *)
+module design_a9_1_CHANN_EN_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
+/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]" */
+/* synthesis syn_force_seq_prim="s_axi_aclk" */;
+  input s_axi_aclk /* synthesis syn_isclock = 1 */;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input [3:0]gpio_io_i;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+endmodule

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_stub.vhdl

@@ -0,0 +1,52 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+-- Date        : Tue Oct 28 21:02:58 2025
+-- Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top design_a9_1_CHANN_EN_0 -prefix
+--               design_a9_1_CHANN_EN_0_ design_a9_1_axi_gpio_1_0_stub.vhdl
+-- Design      : design_a9_1_axi_gpio_1_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z020clg400-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity design_a9_1_CHANN_EN_0 is
+  Port ( 
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
+  );
+
+end design_a9_1_CHANN_EN_0;
+
+architecture stub of design_a9_1_CHANN_EN_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2023.1";
+begin
+end;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/sim/design_a9_1_CHANN_EN_0.vhd

@@ -0,0 +1,209 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
+-- IP Revision: 30
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_gpio_v2_0_30;
+USE axi_gpio_v2_0_30.axi_gpio;
+
+ENTITY design_a9_1_CHANN_EN_0 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+  );
+END design_a9_1_CHANN_EN_0;
+
+ARCHITECTURE design_a9_1_CHANN_EN_0_arch OF design_a9_1_CHANN_EN_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_EN_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_gpio IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_GPIO_WIDTH : INTEGER;
+      C_GPIO2_WIDTH : INTEGER;
+      C_ALL_INPUTS : INTEGER;
+      C_ALL_INPUTS_2 : INTEGER;
+      C_ALL_OUTPUTS : INTEGER;
+      C_ALL_OUTPUTS_2 : INTEGER;
+      C_INTERRUPT_PRESENT : INTEGER;
+      C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_IS_DUAL : INTEGER;
+      C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC;
+      gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi_gpio;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" & 
+"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+BEGIN
+  U0 : axi_gpio
+    GENERIC MAP (
+      C_FAMILY => "zynq",
+      C_S_AXI_ADDR_WIDTH => 9,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_GPIO_WIDTH => 4,
+      C_GPIO2_WIDTH => 32,
+      C_ALL_INPUTS => 0,
+      C_ALL_INPUTS_2 => 0,
+      C_ALL_OUTPUTS => 0,
+      C_ALL_OUTPUTS_2 => 0,
+      C_INTERRUPT_PRESENT => 0,
+      C_DOUT_DEFAULT => X"00000000",
+      C_TRI_DEFAULT => X"FFFFFFFF",
+      C_IS_DUAL => 0,
+      C_DOUT_DEFAULT_2 => X"00000000",
+      C_TRI_DEFAULT_2 => X"FFFFFFFF"
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      gpio_io_i => gpio_io_i,
+      gpio_io_o => gpio_io_o,
+      gpio_io_t => gpio_io_t,
+      gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
+    );
+END design_a9_1_CHANN_EN_0_arch;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/synth/design_a9_1_CHANN_EN_0.vhd

@@ -0,0 +1,215 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
+-- IP Revision: 30
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_gpio_v2_0_30;
+USE axi_gpio_v2_0_30.axi_gpio;
+
+ENTITY design_a9_1_CHANN_EN_0 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+  );
+END design_a9_1_CHANN_EN_0;
+
+ARCHITECTURE design_a9_1_CHANN_EN_0_arch OF design_a9_1_CHANN_EN_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_EN_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_gpio IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_GPIO_WIDTH : INTEGER;
+      C_GPIO2_WIDTH : INTEGER;
+      C_ALL_INPUTS : INTEGER;
+      C_ALL_INPUTS_2 : INTEGER;
+      C_ALL_OUTPUTS : INTEGER;
+      C_ALL_OUTPUTS_2 : INTEGER;
+      C_INTERRUPT_PRESENT : INTEGER;
+      C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_IS_DUAL : INTEGER;
+      C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC;
+      gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi_gpio;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_a9_1_CHANN_EN_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_a9_1_CHANN_EN_0_arch : ARCHITECTURE IS "design_a9_1_CHANN_EN_0,axi_gpio,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_a9_1_CHANN_EN_0_arch: ARCHITECTURE IS "design_a9_1_CHANN_EN_0,axi_gpio,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=30,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" & 
+"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+BEGIN
+  U0 : axi_gpio
+    GENERIC MAP (
+      C_FAMILY => "zynq",
+      C_S_AXI_ADDR_WIDTH => 9,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_GPIO_WIDTH => 4,
+      C_GPIO2_WIDTH => 32,
+      C_ALL_INPUTS => 0,
+      C_ALL_INPUTS_2 => 0,
+      C_ALL_OUTPUTS => 0,
+      C_ALL_OUTPUTS_2 => 0,
+      C_INTERRUPT_PRESENT => 0,
+      C_DOUT_DEFAULT => X"00000000",
+      C_TRI_DEFAULT => X"FFFFFFFF",
+      C_IS_DUAL => 0,
+      C_DOUT_DEFAULT_2 => X"00000000",
+      C_TRI_DEFAULT_2 => X"FFFFFFFF"
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      gpio_io_i => gpio_io_i,
+      gpio_io_o => gpio_io_o,
+      gpio_io_t => gpio_io_t,
+      gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
+    );
+END design_a9_1_CHANN_EN_0_arch;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xdc

@@ -0,0 +1,48 @@
+# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+set_false_path -to [get_pins -hier *cdc_to*/D]
+

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_board.xdc

@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_ooc.xdc

@@ -0,0 +1,62 @@
+
+################################################################################
+# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# User should update the correct clock period before proceeding further
+# This constraints file contains default clock frequencies to be used during 
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs. 
+# For best results the frequencies should be modified# to match the target 
+# frequencies. 
+
+
+ create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
+## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
+
+################################################################################

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_stub.v

@@ -0,0 +1,48 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Wed Jun 24 16:22:50 2026
+// Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_stub.v
+// Design      : design_a9_1_CHANN_EN_1
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axi_gpio,Vivado 2023.1" *)
+module design_a9_1_CHANN_EN_1(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i, gpio_io_o, 
+  gpio_io_t)
+/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[0:0],gpio_io_o[0:0],gpio_io_t[0:0]" */
+/* synthesis syn_force_seq_prim="s_axi_aclk" */;
+  input s_axi_aclk /* synthesis syn_isclock = 1 */;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  output ip2intc_irpt;
+  input [0:0]gpio_io_i;
+  output [0:0]gpio_io_o;
+  output [0:0]gpio_io_t;
+endmodule

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_stub.vhdl

@@ -0,0 +1,53 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+-- Date        : Wed Jun 24 16:22:50 2026
+-- Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_stub.vhdl
+-- Design      : design_a9_1_CHANN_EN_1
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z020clg400-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity design_a9_1_CHANN_EN_1 is
+  Port ( 
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    ip2intc_irpt : out STD_LOGIC;
+    gpio_io_i : in STD_LOGIC_VECTOR ( 0 to 0 );
+    gpio_io_o : out STD_LOGIC_VECTOR ( 0 to 0 );
+    gpio_io_t : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+
+end design_a9_1_CHANN_EN_1;
+
+architecture stub of design_a9_1_CHANN_EN_1 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[0:0],gpio_io_o[0:0],gpio_io_t[0:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2023.1";
+begin
+end;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/sim/design_a9_1_CHANN_EN_1.vhd

@@ -0,0 +1,213 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
+-- IP Revision: 30
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_gpio_v2_0_30;
+USE axi_gpio_v2_0_30.axi_gpio;
+
+ENTITY design_a9_1_CHANN_EN_1 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    ip2intc_irpt : OUT STD_LOGIC;
+    gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+  );
+END design_a9_1_CHANN_EN_1;
+
+ARCHITECTURE design_a9_1_CHANN_EN_1_arch OF design_a9_1_CHANN_EN_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_EN_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_gpio IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_GPIO_WIDTH : INTEGER;
+      C_GPIO2_WIDTH : INTEGER;
+      C_ALL_INPUTS : INTEGER;
+      C_ALL_INPUTS_2 : INTEGER;
+      C_ALL_OUTPUTS : INTEGER;
+      C_ALL_OUTPUTS_2 : INTEGER;
+      C_INTERRUPT_PRESENT : INTEGER;
+      C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_IS_DUAL : INTEGER;
+      C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC;
+      gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi_gpio;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ip2intc_irpt: SIGNAL IS "XIL_INTERFACENAME IP2INTC_IRQ, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
+  ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1," & 
+" NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+BEGIN
+  U0 : axi_gpio
+    GENERIC MAP (
+      C_FAMILY => "zynq",
+      C_S_AXI_ADDR_WIDTH => 9,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_GPIO_WIDTH => 1,
+      C_GPIO2_WIDTH => 32,
+      C_ALL_INPUTS => 0,
+      C_ALL_INPUTS_2 => 0,
+      C_ALL_OUTPUTS => 0,
+      C_ALL_OUTPUTS_2 => 0,
+      C_INTERRUPT_PRESENT => 1,
+      C_DOUT_DEFAULT => X"00000000",
+      C_TRI_DEFAULT => X"FFFFFFFF",
+      C_IS_DUAL => 0,
+      C_DOUT_DEFAULT_2 => X"00000000",
+      C_TRI_DEFAULT_2 => X"FFFFFFFF"
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      ip2intc_irpt => ip2intc_irpt,
+      gpio_io_i => gpio_io_i,
+      gpio_io_o => gpio_io_o,
+      gpio_io_t => gpio_io_t,
+      gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
+    );
+END design_a9_1_CHANN_EN_1_arch;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/synth/design_a9_1_CHANN_EN_1.vhd

@@ -0,0 +1,219 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
+-- IP Revision: 30
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_gpio_v2_0_30;
+USE axi_gpio_v2_0_30.axi_gpio;
+
+ENTITY design_a9_1_CHANN_EN_1 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    ip2intc_irpt : OUT STD_LOGIC;
+    gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+  );
+END design_a9_1_CHANN_EN_1;
+
+ARCHITECTURE design_a9_1_CHANN_EN_1_arch OF design_a9_1_CHANN_EN_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_EN_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_gpio IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_GPIO_WIDTH : INTEGER;
+      C_GPIO2_WIDTH : INTEGER;
+      C_ALL_INPUTS : INTEGER;
+      C_ALL_INPUTS_2 : INTEGER;
+      C_ALL_OUTPUTS : INTEGER;
+      C_ALL_OUTPUTS_2 : INTEGER;
+      C_INTERRUPT_PRESENT : INTEGER;
+      C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_IS_DUAL : INTEGER;
+      C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC;
+      gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi_gpio;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_a9_1_CHANN_EN_1_arch: ARCHITECTURE IS "axi_gpio,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_a9_1_CHANN_EN_1_arch : ARCHITECTURE IS "design_a9_1_CHANN_EN_1,axi_gpio,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_a9_1_CHANN_EN_1_arch: ARCHITECTURE IS "design_a9_1_CHANN_EN_1,axi_gpio,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=30,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=1,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ip2intc_irpt: SIGNAL IS "XIL_INTERFACENAME IP2INTC_IRQ, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
+  ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1," & 
+" NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+BEGIN
+  U0 : axi_gpio
+    GENERIC MAP (
+      C_FAMILY => "zynq",
+      C_S_AXI_ADDR_WIDTH => 9,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_GPIO_WIDTH => 1,
+      C_GPIO2_WIDTH => 32,
+      C_ALL_INPUTS => 0,
+      C_ALL_INPUTS_2 => 0,
+      C_ALL_OUTPUTS => 0,
+      C_ALL_OUTPUTS_2 => 0,
+      C_INTERRUPT_PRESENT => 1,
+      C_DOUT_DEFAULT => X"00000000",
+      C_TRI_DEFAULT => X"FFFFFFFF",
+      C_IS_DUAL => 0,
+      C_DOUT_DEFAULT_2 => X"00000000",
+      C_TRI_DEFAULT_2 => X"FFFFFFFF"
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      ip2intc_irpt => ip2intc_irpt,
+      gpio_io_i => gpio_io_i,
+      gpio_io_o => gpio_io_o,
+      gpio_io_t => gpio_io_t,
+      gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
+    );
+END design_a9_1_CHANN_EN_1_arch;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xdc

@@ -0,0 +1,48 @@
+# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+set_false_path -to [get_pins -hier *cdc_to*/D]
+

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_board.xdc

@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_ooc.xdc

@@ -0,0 +1,62 @@
+
+################################################################################
+# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# User should update the correct clock period before proceeding further
+# This constraints file contains default clock frequencies to be used during 
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs. 
+# For best results the frequencies should be modified# to match the target 
+# frequencies. 
+
+
+ create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
+## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
+
+################################################################################

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_stub.v

@@ -0,0 +1,46 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Wed Jun 24 13:53:29 2026
+// Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_stub.v
+// Design      : design_a9_1_CHANN_EN_2
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axi_gpio,Vivado 2023.1" *)
+module design_a9_1_CHANN_EN_2(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
+/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]" */
+/* synthesis syn_force_seq_prim="s_axi_aclk" */;
+  input s_axi_aclk /* synthesis syn_isclock = 1 */;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input [3:0]gpio_io_i;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+endmodule

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_stub.vhdl

@@ -0,0 +1,52 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+-- Date        : Wed Jun 24 13:53:29 2026
+-- Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_stub.vhdl
+-- Design      : design_a9_1_CHANN_EN_2
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z020clg400-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity design_a9_1_CHANN_EN_2 is
+  Port ( 
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
+  );
+
+end design_a9_1_CHANN_EN_2;
+
+architecture stub of design_a9_1_CHANN_EN_2 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2023.1";
+begin
+end;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/sim/design_a9_1_CHANN_EN_2.vhd

@@ -0,0 +1,209 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
+-- IP Revision: 30
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_gpio_v2_0_30;
+USE axi_gpio_v2_0_30.axi_gpio;
+
+ENTITY design_a9_1_CHANN_EN_2 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+  );
+END design_a9_1_CHANN_EN_2;
+
+ARCHITECTURE design_a9_1_CHANN_EN_2_arch OF design_a9_1_CHANN_EN_2 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_EN_2_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_gpio IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_GPIO_WIDTH : INTEGER;
+      C_GPIO2_WIDTH : INTEGER;
+      C_ALL_INPUTS : INTEGER;
+      C_ALL_INPUTS_2 : INTEGER;
+      C_ALL_OUTPUTS : INTEGER;
+      C_ALL_OUTPUTS_2 : INTEGER;
+      C_INTERRUPT_PRESENT : INTEGER;
+      C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_IS_DUAL : INTEGER;
+      C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC;
+      gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi_gpio;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1," & 
+" NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+BEGIN
+  U0 : axi_gpio
+    GENERIC MAP (
+      C_FAMILY => "zynq",
+      C_S_AXI_ADDR_WIDTH => 9,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_GPIO_WIDTH => 4,
+      C_GPIO2_WIDTH => 32,
+      C_ALL_INPUTS => 0,
+      C_ALL_INPUTS_2 => 0,
+      C_ALL_OUTPUTS => 0,
+      C_ALL_OUTPUTS_2 => 0,
+      C_INTERRUPT_PRESENT => 0,
+      C_DOUT_DEFAULT => X"00000000",
+      C_TRI_DEFAULT => X"FFFFFFFF",
+      C_IS_DUAL => 0,
+      C_DOUT_DEFAULT_2 => X"00000000",
+      C_TRI_DEFAULT_2 => X"FFFFFFFF"
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      gpio_io_i => gpio_io_i,
+      gpio_io_o => gpio_io_o,
+      gpio_io_t => gpio_io_t,
+      gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
+    );
+END design_a9_1_CHANN_EN_2_arch;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/synth/design_a9_1_CHANN_EN_2.vhd

@@ -0,0 +1,215 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
+-- IP Revision: 30
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_gpio_v2_0_30;
+USE axi_gpio_v2_0_30.axi_gpio;
+
+ENTITY design_a9_1_CHANN_EN_2 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+  );
+END design_a9_1_CHANN_EN_2;
+
+ARCHITECTURE design_a9_1_CHANN_EN_2_arch OF design_a9_1_CHANN_EN_2 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_EN_2_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_gpio IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_GPIO_WIDTH : INTEGER;
+      C_GPIO2_WIDTH : INTEGER;
+      C_ALL_INPUTS : INTEGER;
+      C_ALL_INPUTS_2 : INTEGER;
+      C_ALL_OUTPUTS : INTEGER;
+      C_ALL_OUTPUTS_2 : INTEGER;
+      C_INTERRUPT_PRESENT : INTEGER;
+      C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_IS_DUAL : INTEGER;
+      C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC;
+      gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi_gpio;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_a9_1_CHANN_EN_2_arch: ARCHITECTURE IS "axi_gpio,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_a9_1_CHANN_EN_2_arch : ARCHITECTURE IS "design_a9_1_CHANN_EN_2,axi_gpio,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_a9_1_CHANN_EN_2_arch: ARCHITECTURE IS "design_a9_1_CHANN_EN_2,axi_gpio,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=30,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1," & 
+" NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+BEGIN
+  U0 : axi_gpio
+    GENERIC MAP (
+      C_FAMILY => "zynq",
+      C_S_AXI_ADDR_WIDTH => 9,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_GPIO_WIDTH => 4,
+      C_GPIO2_WIDTH => 32,
+      C_ALL_INPUTS => 0,
+      C_ALL_INPUTS_2 => 0,
+      C_ALL_OUTPUTS => 0,
+      C_ALL_OUTPUTS_2 => 0,
+      C_INTERRUPT_PRESENT => 0,
+      C_DOUT_DEFAULT => X"00000000",
+      C_TRI_DEFAULT => X"FFFFFFFF",
+      C_IS_DUAL => 0,
+      C_DOUT_DEFAULT_2 => X"00000000",
+      C_TRI_DEFAULT_2 => X"FFFFFFFF"
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      gpio_io_i => gpio_io_i,
+      gpio_io_o => gpio_io_o,
+      gpio_io_t => gpio_io_t,
+      gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
+    );
+END design_a9_1_CHANN_EN_2_arch;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xdc

@@ -0,0 +1,48 @@
+# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+set_false_path -to [get_pins -hier *cdc_to*/D]
+

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_board.xdc

@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_ooc.xdc

@@ -0,0 +1,62 @@
+
+################################################################################
+# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# User should update the correct clock period before proceeding further
+# This constraints file contains default clock frequencies to be used during 
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs. 
+# For best results the frequencies should be modified# to match the target 
+# frequencies. 
+
+
+ create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
+## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
+
+################################################################################

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_stub.v

@@ -0,0 +1,46 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Tue Oct 28 21:02:19 2025
+// Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top design_a9_1_CHANN_SEL_0 -prefix
+//               design_a9_1_CHANN_SEL_0_ design_a9_1_CHANN_SEL_0_stub.v
+// Design      : design_a9_1_CHANN_SEL_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axi_gpio,Vivado 2023.1" *)
+module design_a9_1_CHANN_SEL_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
+/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[0:0],gpio_io_o[0:0],gpio_io_t[0:0]" */
+/* synthesis syn_force_seq_prim="s_axi_aclk" */;
+  input s_axi_aclk /* synthesis syn_isclock = 1 */;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input [0:0]gpio_io_i;
+  output [0:0]gpio_io_o;
+  output [0:0]gpio_io_t;
+endmodule

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_stub.vhdl

@@ -0,0 +1,52 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+-- Date        : Tue Oct 28 21:02:19 2025
+-- Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top design_a9_1_CHANN_SEL_0 -prefix
+--               design_a9_1_CHANN_SEL_0_ design_a9_1_CHANN_SEL_0_stub.vhdl
+-- Design      : design_a9_1_CHANN_SEL_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z020clg400-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity design_a9_1_CHANN_SEL_0 is
+  Port ( 
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    gpio_io_i : in STD_LOGIC_VECTOR ( 0 to 0 );
+    gpio_io_o : out STD_LOGIC_VECTOR ( 0 to 0 );
+    gpio_io_t : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+
+end design_a9_1_CHANN_SEL_0;
+
+architecture stub of design_a9_1_CHANN_SEL_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[0:0],gpio_io_o[0:0],gpio_io_t[0:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2023.1";
+begin
+end;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/sim/design_a9_1_CHANN_SEL_0.vhd

@@ -0,0 +1,209 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
+-- IP Revision: 30
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_gpio_v2_0_30;
+USE axi_gpio_v2_0_30.axi_gpio;
+
+ENTITY design_a9_1_CHANN_SEL_0 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+  );
+END design_a9_1_CHANN_SEL_0;
+
+ARCHITECTURE design_a9_1_CHANN_SEL_0_arch OF design_a9_1_CHANN_SEL_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_SEL_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_gpio IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_GPIO_WIDTH : INTEGER;
+      C_GPIO2_WIDTH : INTEGER;
+      C_ALL_INPUTS : INTEGER;
+      C_ALL_INPUTS_2 : INTEGER;
+      C_ALL_OUTPUTS : INTEGER;
+      C_ALL_OUTPUTS_2 : INTEGER;
+      C_INTERRUPT_PRESENT : INTEGER;
+      C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_IS_DUAL : INTEGER;
+      C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC;
+      gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi_gpio;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" & 
+"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+BEGIN
+  U0 : axi_gpio
+    GENERIC MAP (
+      C_FAMILY => "zynq",
+      C_S_AXI_ADDR_WIDTH => 9,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_GPIO_WIDTH => 1,
+      C_GPIO2_WIDTH => 32,
+      C_ALL_INPUTS => 0,
+      C_ALL_INPUTS_2 => 0,
+      C_ALL_OUTPUTS => 0,
+      C_ALL_OUTPUTS_2 => 0,
+      C_INTERRUPT_PRESENT => 0,
+      C_DOUT_DEFAULT => X"00000000",
+      C_TRI_DEFAULT => X"FFFFFFFF",
+      C_IS_DUAL => 0,
+      C_DOUT_DEFAULT_2 => X"00000000",
+      C_TRI_DEFAULT_2 => X"FFFFFFFF"
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      gpio_io_i => gpio_io_i,
+      gpio_io_o => gpio_io_o,
+      gpio_io_t => gpio_io_t,
+      gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
+    );
+END design_a9_1_CHANN_SEL_0_arch;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/synth/design_a9_1_CHANN_SEL_0.vhd

@@ -0,0 +1,215 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
+-- IP Revision: 30
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_gpio_v2_0_30;
+USE axi_gpio_v2_0_30.axi_gpio;
+
+ENTITY design_a9_1_CHANN_SEL_0 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+  );
+END design_a9_1_CHANN_SEL_0;
+
+ARCHITECTURE design_a9_1_CHANN_SEL_0_arch OF design_a9_1_CHANN_SEL_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_SEL_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_gpio IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_GPIO_WIDTH : INTEGER;
+      C_GPIO2_WIDTH : INTEGER;
+      C_ALL_INPUTS : INTEGER;
+      C_ALL_INPUTS_2 : INTEGER;
+      C_ALL_OUTPUTS : INTEGER;
+      C_ALL_OUTPUTS_2 : INTEGER;
+      C_INTERRUPT_PRESENT : INTEGER;
+      C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_IS_DUAL : INTEGER;
+      C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC;
+      gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi_gpio;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_a9_1_CHANN_SEL_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_a9_1_CHANN_SEL_0_arch : ARCHITECTURE IS "design_a9_1_CHANN_SEL_0,axi_gpio,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_a9_1_CHANN_SEL_0_arch: ARCHITECTURE IS "design_a9_1_CHANN_SEL_0,axi_gpio,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=30,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=1,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" & 
+"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+BEGIN
+  U0 : axi_gpio
+    GENERIC MAP (
+      C_FAMILY => "zynq",
+      C_S_AXI_ADDR_WIDTH => 9,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_GPIO_WIDTH => 1,
+      C_GPIO2_WIDTH => 32,
+      C_ALL_INPUTS => 0,
+      C_ALL_INPUTS_2 => 0,
+      C_ALL_OUTPUTS => 0,
+      C_ALL_OUTPUTS_2 => 0,
+      C_INTERRUPT_PRESENT => 0,
+      C_DOUT_DEFAULT => X"00000000",
+      C_TRI_DEFAULT => X"FFFFFFFF",
+      C_IS_DUAL => 0,
+      C_DOUT_DEFAULT_2 => X"00000000",
+      C_TRI_DEFAULT_2 => X"FFFFFFFF"
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      gpio_io_i => gpio_io_i,
+      gpio_io_o => gpio_io_o,
+      gpio_io_t => gpio_io_t,
+      gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
+    );
+END design_a9_1_CHANN_SEL_0_arch;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xdc

@@ -0,0 +1,99 @@
+# file: design_a9_1_STIM_SPI_0.xdc
+# (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+## IOB constraints ######
+set_property IOB true [get_cells -hierarchical -filter {NAME =~*IO*_I_REG}]
+
+#####################################################################################################
+# The following section list the board specific constraints (with/without STARTUPE2/E3 primitive)   #
+# as per guidance given in product guide.                                                           #
+# User should uncomment, update constraints based on board delays and use                           #
+#####################################################################################################
+
+#####################################################################################################
+# STARTUPE2 primitive is not used                                                                   #
+#####################################################################################################
+#### All the delay numbers have to be provided by the user
+
+#### CCLK max delay is 6.7 ns ; refer Data sheet
+#### We need to consider the max delay for worst case analysis
+##set cclk_delay 6.7
+
+#### Following are the SPI device parameters
+#### Max Tco
+##set tco_max 7
+#### Min Tco
+##set tco_min 1
+#### Setup time requirement
+##set tsu 2
+#### Hold time requirement
+##set th 3
+
+#### Following are the board/trace delay numbers
+#### Assumption is that all Data lines are matched
+##set tdata_trace_delay_max 0.25
+##set tdata_trace_delay_min 0.25
+##set tclk_trace_delay_max 0.2
+##set tclk_trace_delay_min 0.2
+
+##### End of user provided delay numbers
+####create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_ports <SCK_IO>] -edges {3 5 7}
+##create_generated_clock -name clk_sck -source [get_pins -filter {REF_PIN_NAME==ext_spi_clk} -of [get_cells -hier -filter {REF_NAME=~axi_quad_spi_0}]] [get_ports SCK_IO] -edges {3 5 7}
+
+#### Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCK falling edge
+#### Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk
+##set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports IO*_IO] -clock_fall;
+##set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports IO*_IO] -clock_fall;
+##set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
+##set_multicycle_path 1 -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
+
+#### Data is captured into SPI on the following rising edge of SCK
+#### Data is driven by the IP on alternate rising_edge of the ext_spi_clk
+##set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_ports IO*_IO];
+##set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min - $th - $tclk_trace_delay_max] [get_ports IO*_IO];
+##set_multicycle_path 2 -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
+##set_multicycle_path 1 -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_board.xdc

@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_clocks.xdc

@@ -0,0 +1,59 @@
+# file: design_a9_1_STIM_SPI_0.xdc
+# (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+
+			set clk_domain_axi_lite [get_clocks -of_objects [get_ports s_axi_aclk]]
+			set clk_domain_ext_spi_clk [get_clocks -of_objects [get_ports ext_spi_clk]]
+# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
+	
+	
+
+
+
+
+

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_ooc.xdc

@@ -0,0 +1,86 @@
+
+################################################################################
+# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# User should update the correct clock period before proceeding further
+# This constraints file contains default clock frequencies to be used during 
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs. 
+# For best results the frequencies should be modified# to match the target 
+# frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+################################################################################
+#create_clock -name clock_name -period 10 [get_ports clock_name] 
+################################################################################
+
+#list of all the clock needed for AXI Quad SPI core
+
+	create_clock -name all_clock -period 20 [get_ports {s_axi_aclk ext_spi_clk}] 
+##			 set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
+
+##			 set_property HD.CLK_SRC BUFGCTRL_X0Y1 [get_ports ext_spi_clk]
+
+
+set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/src_gray_ff_reg[*]] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/dest_graysync_ff_reg[0][*]] -filter {REF_PIN_NAME == D}]
+set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_reg[*]] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_reg[0][*]] -filter {REF_PIN_NAME == D}]
+set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/src_gray_ff_reg[*]] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/dest_graysync_ff_reg[0][*]] -filter {REF_PIN_NAME == D}]
+set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/*] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.*/*_CDC*] -filter {REF_PIN_NAME == D}]
+set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/SOFT_RESET_I/RESET_FLOPS[15].RST_FLOPS] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/RESET_SYNC_AX2S_1] -filter {REF_PIN_NAME == D}]
+set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg] -filter {REF_PIN_NAME ==C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/RESET_SYNC_AX2S_1] -filter {REF_PIN_NAME == D}]
+	
+
+	
+	
+
+
+	
+
+
+
+################################################################################

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_stub.v

@@ -0,0 +1,59 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Wed Jun 24 13:54:04 2026
+// Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_stub.v
+// Design      : design_a9_1_STIM_SPI_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axi_quad_spi,Vivado 2023.1" *)
+module design_a9_1_STIM_SPI_0(ext_spi_clk, s_axi_aclk, s_axi_aresetn, 
+  s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, 
+  s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, 
+  s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, io0_i, io0_o, io0_t, io1_i, 
+  io1_o, io1_t, sck_i, sck_o, sck_t, ss_i, ss_o, ss_t, ip2intc_irpt)
+/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt" */
+/* synthesis syn_force_seq_prim="ext_spi_clk" */
+/* synthesis syn_force_seq_prim="s_axi_aclk" */;
+  input ext_spi_clk /* synthesis syn_isclock = 1 */;
+  input s_axi_aclk /* synthesis syn_isclock = 1 */;
+  input s_axi_aresetn;
+  input [6:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [6:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input io0_i;
+  output io0_o;
+  output io0_t;
+  input io1_i;
+  output io1_o;
+  output io1_t;
+  input sck_i;
+  output sck_o;
+  output sck_t;
+  input [0:0]ss_i;
+  output [0:0]ss_o;
+  output ss_t;
+  output ip2intc_irpt;
+endmodule

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_stub.vhdl

@@ -0,0 +1,63 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+-- Date        : Wed Jun 24 13:54:04 2026
+-- Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_stub.vhdl
+-- Design      : design_a9_1_STIM_SPI_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z020clg400-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity design_a9_1_STIM_SPI_0 is
+  Port ( 
+    ext_spi_clk : in STD_LOGIC;
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    io0_i : in STD_LOGIC;
+    io0_o : out STD_LOGIC;
+    io0_t : out STD_LOGIC;
+    io1_i : in STD_LOGIC;
+    io1_o : out STD_LOGIC;
+    io1_t : out STD_LOGIC;
+    sck_i : in STD_LOGIC;
+    sck_o : out STD_LOGIC;
+    sck_t : out STD_LOGIC;
+    ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
+    ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
+    ss_t : out STD_LOGIC;
+    ip2intc_irpt : out STD_LOGIC
+  );
+
+end design_a9_1_STIM_SPI_0;
+
+architecture stub of design_a9_1_STIM_SPI_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "axi_quad_spi,Vivado 2023.1";
+begin
+end;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/netlist/mode_1_memory_0_mixed.mem

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c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/netlist/mode_1_memory_1_wb.mem

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c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/netlist/mode_2_memory_3_sp.mif

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c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/netlist/mode_2_memory_4_mx.mem

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c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/netlist/mode_2_memory_4_mx.mif

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c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/sim/design_a9_1_STIM_SPI_0.vhd

@@ -0,0 +1,393 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
+-- IP Revision: 27
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_quad_spi_v3_2_27;
+USE axi_quad_spi_v3_2_27.axi_quad_spi;
+
+ENTITY design_a9_1_STIM_SPI_0 IS
+  PORT (
+    ext_spi_clk : IN STD_LOGIC;
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    io0_i : IN STD_LOGIC;
+    io0_o : OUT STD_LOGIC;
+    io0_t : OUT STD_LOGIC;
+    io1_i : IN STD_LOGIC;
+    io1_o : OUT STD_LOGIC;
+    io1_t : OUT STD_LOGIC;
+    sck_i : IN STD_LOGIC;
+    sck_o : OUT STD_LOGIC;
+    sck_t : OUT STD_LOGIC;
+    ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ss_t : OUT STD_LOGIC;
+    ip2intc_irpt : OUT STD_LOGIC
+  );
+END design_a9_1_STIM_SPI_0;
+
+ARCHITECTURE design_a9_1_STIM_SPI_0_arch OF design_a9_1_STIM_SPI_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_STIM_SPI_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_quad_spi IS
+    GENERIC (
+      Async_Clk : INTEGER;
+      C_FAMILY : STRING;
+      C_SELECT_XPM : INTEGER;
+      C_SUB_FAMILY : STRING;
+      C_INSTANCE : STRING;
+      C_SPI_MEM_ADDR_BITS : INTEGER;
+      C_TYPE_OF_AXI4_INTERFACE : INTEGER;
+      C_XIP_MODE : INTEGER;
+      C_XIP_PERF_MODE : INTEGER;
+      C_BYTE_LEVEL_INTERRUPT_EN : INTEGER;
+      C_UC_FAMILY : INTEGER;
+      C_FIFO_DEPTH : INTEGER;
+      C_SCK_RATIO : INTEGER;
+      C_DUAL_QUAD_MODE : INTEGER;
+      C_NUM_SS_BITS : INTEGER;
+      C_NUM_TRANSFER_BITS : INTEGER;
+      C_NEW_SEQ_EN : INTEGER;
+      C_SPI_MODE : INTEGER;
+      C_USE_STARTUP : INTEGER;
+      C_USE_STARTUP_EXT : INTEGER;
+      C_SPI_MEMORY : INTEGER;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_S_AXI4_ADDR_WIDTH : INTEGER;
+      C_S_AXI4_DATA_WIDTH : INTEGER;
+      C_S_AXI4_ID_WIDTH : INTEGER;
+      C_SHARED_STARTUP : INTEGER;
+      C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
+      C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
+      C_LSB_STUP : INTEGER
+    );
+    PORT (
+      ext_spi_clk : IN STD_LOGIC;
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi4_aclk : IN STD_LOGIC;
+      s_axi4_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      s_axi4_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi4_awlock : IN STD_LOGIC;
+      s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi4_awvalid : IN STD_LOGIC;
+      s_axi4_awready : OUT STD_LOGIC;
+      s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_wlast : IN STD_LOGIC;
+      s_axi4_wvalid : IN STD_LOGIC;
+      s_axi4_wready : OUT STD_LOGIC;
+      s_axi4_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi4_bvalid : OUT STD_LOGIC;
+      s_axi4_bready : IN STD_LOGIC;
+      s_axi4_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi4_arlock : IN STD_LOGIC;
+      s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi4_arvalid : IN STD_LOGIC;
+      s_axi4_arready : OUT STD_LOGIC;
+      s_axi4_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi4_rlast : OUT STD_LOGIC;
+      s_axi4_rvalid : OUT STD_LOGIC;
+      s_axi4_rready : IN STD_LOGIC;
+      io0_i : IN STD_LOGIC;
+      io0_o : OUT STD_LOGIC;
+      io0_t : OUT STD_LOGIC;
+      io1_i : IN STD_LOGIC;
+      io1_o : OUT STD_LOGIC;
+      io1_t : OUT STD_LOGIC;
+      io2_i : IN STD_LOGIC;
+      io2_o : OUT STD_LOGIC;
+      io2_t : OUT STD_LOGIC;
+      io3_i : IN STD_LOGIC;
+      io3_o : OUT STD_LOGIC;
+      io3_t : OUT STD_LOGIC;
+      io0_1_i : IN STD_LOGIC;
+      io0_1_o : OUT STD_LOGIC;
+      io0_1_t : OUT STD_LOGIC;
+      io1_1_i : IN STD_LOGIC;
+      io1_1_o : OUT STD_LOGIC;
+      io1_1_t : OUT STD_LOGIC;
+      io2_1_i : IN STD_LOGIC;
+      io2_1_o : OUT STD_LOGIC;
+      io2_1_t : OUT STD_LOGIC;
+      io3_1_i : IN STD_LOGIC;
+      io3_1_o : OUT STD_LOGIC;
+      io3_1_t : OUT STD_LOGIC;
+      spisel : IN STD_LOGIC;
+      sck_i : IN STD_LOGIC;
+      sck_o : OUT STD_LOGIC;
+      sck_t : OUT STD_LOGIC;
+      ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      ss_t : OUT STD_LOGIC;
+      ss_1_i : IN STD_LOGIC;
+      ss_1_o : OUT STD_LOGIC;
+      ss_1_t : OUT STD_LOGIC;
+      cfgclk : OUT STD_LOGIC;
+      cfgmclk : OUT STD_LOGIC;
+      eos : OUT STD_LOGIC;
+      preq : OUT STD_LOGIC;
+      clk : IN STD_LOGIC;
+      gsr : IN STD_LOGIC;
+      gts : IN STD_LOGIC;
+      keyclearb : IN STD_LOGIC;
+      usrcclkts : IN STD_LOGIC;
+      usrdoneo : IN STD_LOGIC;
+      usrdonets : IN STD_LOGIC;
+      pack : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC
+    );
+  END COMPONENT axi_quad_spi;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ext_spi_clk: SIGNAL IS "XIL_INTERFACENAME spi_clk, ASSOCIATED_BUSIF SPI_0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF io0_i: SIGNAL IS "XIL_INTERFACENAME SPI_0, BOARD.ASSOCIATED_PARAM QSPI_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
+  ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
+  ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
+  ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
+  ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
+  ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ip2intc_irpt: SIGNAL IS "XIL_INTERFACENAME interrupt, SENSITIVITY EDGE_RISING, PORTWIDTH 1";
+  ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME lite_clk, ASSOCIATED_BUSIF AXI_LITE, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME lite_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 7, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" & 
+" 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
+  ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
+  ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
+  ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
+  ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
+  ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
+BEGIN
+  U0 : axi_quad_spi
+    GENERIC MAP (
+      Async_Clk => 0,
+      C_FAMILY => "zynq",
+      C_SELECT_XPM => 0,
+      C_SUB_FAMILY => "zynq",
+      C_INSTANCE => "axi_quad_spi_inst",
+      C_SPI_MEM_ADDR_BITS => 24,
+      C_TYPE_OF_AXI4_INTERFACE => 0,
+      C_XIP_MODE => 0,
+      C_XIP_PERF_MODE => 1,
+      C_BYTE_LEVEL_INTERRUPT_EN => 0,
+      C_UC_FAMILY => 0,
+      C_FIFO_DEPTH => 16,
+      C_SCK_RATIO => 16,
+      C_DUAL_QUAD_MODE => 0,
+      C_NUM_SS_BITS => 1,
+      C_NUM_TRANSFER_BITS => 8,
+      C_NEW_SEQ_EN => 1,
+      C_SPI_MODE => 0,
+      C_USE_STARTUP => 0,
+      C_USE_STARTUP_EXT => 0,
+      C_SPI_MEMORY => 1,
+      C_S_AXI_ADDR_WIDTH => 7,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_S_AXI4_ADDR_WIDTH => 24,
+      C_S_AXI4_DATA_WIDTH => 32,
+      C_S_AXI4_ID_WIDTH => 4,
+      C_SHARED_STARTUP => 0,
+      C_S_AXI4_BASEADDR => X"FFFFFFFF",
+      C_S_AXI4_HIGHADDR => X"00000000",
+      C_LSB_STUP => 0
+    )
+    PORT MAP (
+      ext_spi_clk => ext_spi_clk,
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi4_aclk => '0',
+      s_axi4_aresetn => '0',
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
+      s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi4_awlock => '0',
+      s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi4_awvalid => '0',
+      s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_wlast => '0',
+      s_axi4_wvalid => '0',
+      s_axi4_bready => '0',
+      s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
+      s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi4_arlock => '0',
+      s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi4_arvalid => '0',
+      s_axi4_rready => '0',
+      io0_i => io0_i,
+      io0_o => io0_o,
+      io0_t => io0_t,
+      io1_i => io1_i,
+      io1_o => io1_o,
+      io1_t => io1_t,
+      io2_i => '0',
+      io3_i => '0',
+      io0_1_i => '0',
+      io1_1_i => '0',
+      io2_1_i => '0',
+      io3_1_i => '0',
+      spisel => '1',
+      sck_i => sck_i,
+      sck_o => sck_o,
+      sck_t => sck_t,
+      ss_i => ss_i,
+      ss_o => ss_o,
+      ss_t => ss_t,
+      ss_1_i => '0',
+      clk => '0',
+      gsr => '0',
+      gts => '0',
+      keyclearb => '0',
+      usrcclkts => '0',
+      usrdoneo => '1',
+      usrdonets => '0',
+      pack => '0',
+      ip2intc_irpt => ip2intc_irpt
+    );
+END design_a9_1_STIM_SPI_0_arch;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/synth/design_a9_1_STIM_SPI_0.vhd

@@ -0,0 +1,400 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
+-- IP Revision: 27
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_quad_spi_v3_2_27;
+USE axi_quad_spi_v3_2_27.axi_quad_spi;
+
+ENTITY design_a9_1_STIM_SPI_0 IS
+  PORT (
+    ext_spi_clk : IN STD_LOGIC;
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    io0_i : IN STD_LOGIC;
+    io0_o : OUT STD_LOGIC;
+    io0_t : OUT STD_LOGIC;
+    io1_i : IN STD_LOGIC;
+    io1_o : OUT STD_LOGIC;
+    io1_t : OUT STD_LOGIC;
+    sck_i : IN STD_LOGIC;
+    sck_o : OUT STD_LOGIC;
+    sck_t : OUT STD_LOGIC;
+    ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ss_t : OUT STD_LOGIC;
+    ip2intc_irpt : OUT STD_LOGIC
+  );
+END design_a9_1_STIM_SPI_0;
+
+ARCHITECTURE design_a9_1_STIM_SPI_0_arch OF design_a9_1_STIM_SPI_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_STIM_SPI_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_quad_spi IS
+    GENERIC (
+      Async_Clk : INTEGER;
+      C_FAMILY : STRING;
+      C_SELECT_XPM : INTEGER;
+      C_SUB_FAMILY : STRING;
+      C_INSTANCE : STRING;
+      C_SPI_MEM_ADDR_BITS : INTEGER;
+      C_TYPE_OF_AXI4_INTERFACE : INTEGER;
+      C_XIP_MODE : INTEGER;
+      C_XIP_PERF_MODE : INTEGER;
+      C_BYTE_LEVEL_INTERRUPT_EN : INTEGER;
+      C_UC_FAMILY : INTEGER;
+      C_FIFO_DEPTH : INTEGER;
+      C_SCK_RATIO : INTEGER;
+      C_DUAL_QUAD_MODE : INTEGER;
+      C_NUM_SS_BITS : INTEGER;
+      C_NUM_TRANSFER_BITS : INTEGER;
+      C_NEW_SEQ_EN : INTEGER;
+      C_SPI_MODE : INTEGER;
+      C_USE_STARTUP : INTEGER;
+      C_USE_STARTUP_EXT : INTEGER;
+      C_SPI_MEMORY : INTEGER;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_S_AXI4_ADDR_WIDTH : INTEGER;
+      C_S_AXI4_DATA_WIDTH : INTEGER;
+      C_S_AXI4_ID_WIDTH : INTEGER;
+      C_SHARED_STARTUP : INTEGER;
+      C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
+      C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
+      C_LSB_STUP : INTEGER
+    );
+    PORT (
+      ext_spi_clk : IN STD_LOGIC;
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi4_aclk : IN STD_LOGIC;
+      s_axi4_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      s_axi4_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi4_awlock : IN STD_LOGIC;
+      s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi4_awvalid : IN STD_LOGIC;
+      s_axi4_awready : OUT STD_LOGIC;
+      s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_wlast : IN STD_LOGIC;
+      s_axi4_wvalid : IN STD_LOGIC;
+      s_axi4_wready : OUT STD_LOGIC;
+      s_axi4_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi4_bvalid : OUT STD_LOGIC;
+      s_axi4_bready : IN STD_LOGIC;
+      s_axi4_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi4_arlock : IN STD_LOGIC;
+      s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi4_arvalid : IN STD_LOGIC;
+      s_axi4_arready : OUT STD_LOGIC;
+      s_axi4_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi4_rlast : OUT STD_LOGIC;
+      s_axi4_rvalid : OUT STD_LOGIC;
+      s_axi4_rready : IN STD_LOGIC;
+      io0_i : IN STD_LOGIC;
+      io0_o : OUT STD_LOGIC;
+      io0_t : OUT STD_LOGIC;
+      io1_i : IN STD_LOGIC;
+      io1_o : OUT STD_LOGIC;
+      io1_t : OUT STD_LOGIC;
+      io2_i : IN STD_LOGIC;
+      io2_o : OUT STD_LOGIC;
+      io2_t : OUT STD_LOGIC;
+      io3_i : IN STD_LOGIC;
+      io3_o : OUT STD_LOGIC;
+      io3_t : OUT STD_LOGIC;
+      io0_1_i : IN STD_LOGIC;
+      io0_1_o : OUT STD_LOGIC;
+      io0_1_t : OUT STD_LOGIC;
+      io1_1_i : IN STD_LOGIC;
+      io1_1_o : OUT STD_LOGIC;
+      io1_1_t : OUT STD_LOGIC;
+      io2_1_i : IN STD_LOGIC;
+      io2_1_o : OUT STD_LOGIC;
+      io2_1_t : OUT STD_LOGIC;
+      io3_1_i : IN STD_LOGIC;
+      io3_1_o : OUT STD_LOGIC;
+      io3_1_t : OUT STD_LOGIC;
+      spisel : IN STD_LOGIC;
+      sck_i : IN STD_LOGIC;
+      sck_o : OUT STD_LOGIC;
+      sck_t : OUT STD_LOGIC;
+      ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      ss_t : OUT STD_LOGIC;
+      ss_1_i : IN STD_LOGIC;
+      ss_1_o : OUT STD_LOGIC;
+      ss_1_t : OUT STD_LOGIC;
+      cfgclk : OUT STD_LOGIC;
+      cfgmclk : OUT STD_LOGIC;
+      eos : OUT STD_LOGIC;
+      preq : OUT STD_LOGIC;
+      clk : IN STD_LOGIC;
+      gsr : IN STD_LOGIC;
+      gts : IN STD_LOGIC;
+      keyclearb : IN STD_LOGIC;
+      usrcclkts : IN STD_LOGIC;
+      usrdoneo : IN STD_LOGIC;
+      usrdonets : IN STD_LOGIC;
+      pack : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC
+    );
+  END COMPONENT axi_quad_spi;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_a9_1_STIM_SPI_0_arch: ARCHITECTURE IS "axi_quad_spi,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_a9_1_STIM_SPI_0_arch : ARCHITECTURE IS "design_a9_1_STIM_SPI_0,axi_quad_spi,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_a9_1_STIM_SPI_0_arch: ARCHITECTURE IS "design_a9_1_STIM_SPI_0,axi_quad_spi,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_quad_spi,x_ipVersion=3.2,x_ipCoreRevision=27,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,Async_Clk=0,C_FAMILY=zynq,C_SELECT_XPM=0,C_SUB_FAMILY=zynq,C_INSTANCE=axi_quad_spi_inst,C_SPI_MEM_ADDR_BITS=24,C_TYPE_OF_AXI4_INTERFACE=0,C_XIP_MODE=0,C_XIP_PERF_MODE=1,C_BYTE_LEVEL_INTERRUPT_EN=0,C_UC_FAMILY=0,C_FIFO_DEPTH=16,C_SCK_RATIO=16,C_DUAL_QUAD_MODE=0,C_NUM_SS_BITS=1,C_NUM_TRANSFER_BITS=8," & 
+"C_NEW_SEQ_EN=1,C_SPI_MODE=0,C_USE_STARTUP=0,C_USE_STARTUP_EXT=0,C_SPI_MEMORY=1,C_S_AXI_ADDR_WIDTH=7,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_ADDR_WIDTH=24,C_S_AXI4_DATA_WIDTH=32,C_S_AXI4_ID_WIDTH=4,C_SHARED_STARTUP=0,C_S_AXI4_BASEADDR=0xFFFFFFFF,C_S_AXI4_HIGHADDR=0x00000000,C_LSB_STUP=0}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ext_spi_clk: SIGNAL IS "XIL_INTERFACENAME spi_clk, ASSOCIATED_BUSIF SPI_0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF io0_i: SIGNAL IS "XIL_INTERFACENAME SPI_0, BOARD.ASSOCIATED_PARAM QSPI_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
+  ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
+  ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
+  ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
+  ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
+  ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ip2intc_irpt: SIGNAL IS "XIL_INTERFACENAME interrupt, SENSITIVITY EDGE_RISING, PORTWIDTH 1";
+  ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME lite_clk, ASSOCIATED_BUSIF AXI_LITE, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME lite_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 7, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" & 
+" 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
+  ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
+  ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
+  ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
+  ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
+  ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
+BEGIN
+  U0 : axi_quad_spi
+    GENERIC MAP (
+      Async_Clk => 0,
+      C_FAMILY => "zynq",
+      C_SELECT_XPM => 0,
+      C_SUB_FAMILY => "zynq",
+      C_INSTANCE => "axi_quad_spi_inst",
+      C_SPI_MEM_ADDR_BITS => 24,
+      C_TYPE_OF_AXI4_INTERFACE => 0,
+      C_XIP_MODE => 0,
+      C_XIP_PERF_MODE => 1,
+      C_BYTE_LEVEL_INTERRUPT_EN => 0,
+      C_UC_FAMILY => 0,
+      C_FIFO_DEPTH => 16,
+      C_SCK_RATIO => 16,
+      C_DUAL_QUAD_MODE => 0,
+      C_NUM_SS_BITS => 1,
+      C_NUM_TRANSFER_BITS => 8,
+      C_NEW_SEQ_EN => 1,
+      C_SPI_MODE => 0,
+      C_USE_STARTUP => 0,
+      C_USE_STARTUP_EXT => 0,
+      C_SPI_MEMORY => 1,
+      C_S_AXI_ADDR_WIDTH => 7,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_S_AXI4_ADDR_WIDTH => 24,
+      C_S_AXI4_DATA_WIDTH => 32,
+      C_S_AXI4_ID_WIDTH => 4,
+      C_SHARED_STARTUP => 0,
+      C_S_AXI4_BASEADDR => X"FFFFFFFF",
+      C_S_AXI4_HIGHADDR => X"00000000",
+      C_LSB_STUP => 0
+    )
+    PORT MAP (
+      ext_spi_clk => ext_spi_clk,
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi4_aclk => '0',
+      s_axi4_aresetn => '0',
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
+      s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi4_awlock => '0',
+      s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi4_awvalid => '0',
+      s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_wlast => '0',
+      s_axi4_wvalid => '0',
+      s_axi4_bready => '0',
+      s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
+      s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi4_arlock => '0',
+      s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi4_arvalid => '0',
+      s_axi4_rready => '0',
+      io0_i => io0_i,
+      io0_o => io0_o,
+      io0_t => io0_t,
+      io1_i => io1_i,
+      io1_o => io1_o,
+      io1_t => io1_t,
+      io2_i => '0',
+      io3_i => '0',
+      io0_1_i => '0',
+      io1_1_i => '0',
+      io2_1_i => '0',
+      io3_1_i => '0',
+      spisel => '1',
+      sck_i => sck_i,
+      sck_o => sck_o,
+      sck_t => sck_t,
+      ss_i => ss_i,
+      ss_o => ss_o,
+      ss_t => ss_t,
+      ss_1_i => '0',
+      clk => '0',
+      gsr => '0',
+      gts => '0',
+      keyclearb => '0',
+      usrcclkts => '0',
+      usrdoneo => '1',
+      usrdonets => '0',
+      pack => '0',
+      ip2intc_irpt => ip2intc_irpt
+    );
+END design_a9_1_STIM_SPI_0_arch;

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xdc

@@ -0,0 +1,99 @@
+# file: design_a9_1_ZCHECK_SPI_0.xdc
+# (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+## IOB constraints ######
+set_property IOB true [get_cells -hierarchical -filter {NAME =~*IO*_I_REG}]
+
+#####################################################################################################
+# The following section list the board specific constraints (with/without STARTUPE2/E3 primitive)   #
+# as per guidance given in product guide.                                                           #
+# User should uncomment, update constraints based on board delays and use                           #
+#####################################################################################################
+
+#####################################################################################################
+# STARTUPE2 primitive is not used                                                                   #
+#####################################################################################################
+#### All the delay numbers have to be provided by the user
+
+#### CCLK max delay is 6.7 ns ; refer Data sheet
+#### We need to consider the max delay for worst case analysis
+##set cclk_delay 6.7
+
+#### Following are the SPI device parameters
+#### Max Tco
+##set tco_max 7
+#### Min Tco
+##set tco_min 1
+#### Setup time requirement
+##set tsu 2
+#### Hold time requirement
+##set th 3
+
+#### Following are the board/trace delay numbers
+#### Assumption is that all Data lines are matched
+##set tdata_trace_delay_max 0.25
+##set tdata_trace_delay_min 0.25
+##set tclk_trace_delay_max 0.2
+##set tclk_trace_delay_min 0.2
+
+##### End of user provided delay numbers
+####create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_ports <SCK_IO>] -edges {3 5 7}
+##create_generated_clock -name clk_sck -source [get_pins -filter {REF_PIN_NAME==ext_spi_clk} -of [get_cells -hier -filter {REF_NAME=~axi_quad_spi_0}]] [get_ports SCK_IO] -edges {3 5 7}
+
+#### Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCK falling edge
+#### Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk
+##set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports IO*_IO] -clock_fall;
+##set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports IO*_IO] -clock_fall;
+##set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
+##set_multicycle_path 1 -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
+
+#### Data is captured into SPI on the following rising edge of SCK
+#### Data is driven by the IP on alternate rising_edge of the ext_spi_clk
+##set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_ports IO*_IO];
+##set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min - $th - $tclk_trace_delay_max] [get_ports IO*_IO];
+##set_multicycle_path 2 -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
+##set_multicycle_path 1 -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_board.xdc

@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_clocks.xdc

@@ -0,0 +1,59 @@
+# file: design_a9_1_ZCHECK_SPI_0.xdc
+# (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+
+			set clk_domain_axi_lite [get_clocks -of_objects [get_ports s_axi_aclk]]
+			set clk_domain_ext_spi_clk [get_clocks -of_objects [get_ports ext_spi_clk]]
+# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
+	
+	
+
+
+
+
+

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_ooc.xdc

@@ -0,0 +1,86 @@
+
+################################################################################
+# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# User should update the correct clock period before proceeding further
+# This constraints file contains default clock frequencies to be used during 
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs. 
+# For best results the frequencies should be modified# to match the target 
+# frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+################################################################################
+#create_clock -name clock_name -period 10 [get_ports clock_name] 
+################################################################################
+
+#list of all the clock needed for AXI Quad SPI core
+
+	create_clock -name all_clock -period 20 [get_ports {s_axi_aclk ext_spi_clk}] 
+##			 set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
+
+##			 set_property HD.CLK_SRC BUFGCTRL_X0Y1 [get_ports ext_spi_clk]
+
+
+set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/src_gray_ff_reg[*]] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/dest_graysync_ff_reg[0][*]] -filter {REF_PIN_NAME == D}]
+set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_reg[*]] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_reg[0][*]] -filter {REF_PIN_NAME == D}]
+set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/src_gray_ff_reg[*]] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/dest_graysync_ff_reg[0][*]] -filter {REF_PIN_NAME == D}]
+set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/*] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.*/*_CDC*] -filter {REF_PIN_NAME == D}]
+set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/SOFT_RESET_I/RESET_FLOPS[15].RST_FLOPS] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/RESET_SYNC_AX2S_1] -filter {REF_PIN_NAME == D}]
+set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg] -filter {REF_PIN_NAME ==C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/RESET_SYNC_AX2S_1] -filter {REF_PIN_NAME == D}]
+	
+
+	
+	
+
+
+	
+
+
+
+################################################################################

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_stub.v

@@ -0,0 +1,59 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Wed Jun 24 13:54:03 2026
+// Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top design_a9_1_ZCHECK_SPI_0 -prefix
+//               design_a9_1_ZCHECK_SPI_0_ design_a9_1_STIM_SPI_0_stub.v
+// Design      : design_a9_1_STIM_SPI_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axi_quad_spi,Vivado 2023.1" *)
+module design_a9_1_ZCHECK_SPI_0(ext_spi_clk, s_axi_aclk, s_axi_aresetn, 
+  s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, 
+  s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, 
+  s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, io0_i, io0_o, io0_t, io1_i, 
+  io1_o, io1_t, sck_i, sck_o, sck_t, ss_i, ss_o, ss_t, ip2intc_irpt)
+/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt" */
+/* synthesis syn_force_seq_prim="ext_spi_clk" */
+/* synthesis syn_force_seq_prim="s_axi_aclk" */;
+  input ext_spi_clk /* synthesis syn_isclock = 1 */;
+  input s_axi_aclk /* synthesis syn_isclock = 1 */;
+  input s_axi_aresetn;
+  input [6:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [6:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input io0_i;
+  output io0_o;
+  output io0_t;
+  input io1_i;
+  output io1_o;
+  output io1_t;
+  input sck_i;
+  output sck_o;
+  output sck_t;
+  input [0:0]ss_i;
+  output [0:0]ss_o;
+  output ss_t;
+  output ip2intc_irpt;
+endmodule

c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_stub.vhdl

@@ -0,0 +1,63 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+-- Date        : Wed Jun 24 13:54:03 2026
+-- Host        : DESKTOP-VN054CM running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top design_a9_1_ZCHECK_SPI_0 -prefix
+--               design_a9_1_ZCHECK_SPI_0_ design_a9_1_STIM_SPI_0_stub.vhdl
+-- Design      : design_a9_1_STIM_SPI_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z020clg400-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity design_a9_1_ZCHECK_SPI_0 is
+  Port ( 
+    ext_spi_clk : in STD_LOGIC;
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    io0_i : in STD_LOGIC;
+    io0_o : out STD_LOGIC;
+    io0_t : out STD_LOGIC;
+    io1_i : in STD_LOGIC;
+    io1_o : out STD_LOGIC;
+    io1_t : out STD_LOGIC;
+    sck_i : in STD_LOGIC;
+    sck_o : out STD_LOGIC;
+    sck_t : out STD_LOGIC;
+    ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
+    ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
+    ss_t : out STD_LOGIC;
+    ip2intc_irpt : out STD_LOGIC
+  );
+
+end design_a9_1_ZCHECK_SPI_0;
+
+architecture stub of design_a9_1_ZCHECK_SPI_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "axi_quad_spi,Vivado 2023.1";
+begin
+end;