sync chunk 9/12
This commit is contained in:
chunk-sync
@@ -225,6 +225,42 @@
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"TU": "memory"
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},
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"V5": {
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"VT": "AC",
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"BA": "0x00000000",
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||||
"HA": "0x1FFFFFFF",
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||||
"BP": "C_BASEADDR",
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||||
"HP": "C_HIGHADDR",
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||||
"MA": "Data_S2MM",
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||||
"MX": "/axi_dma_2",
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"MI": "M_AXI_S2MM",
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"MS": "SEG_processing_system7_0_HP0_DDR_LOWOCM",
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"MV": "xilinx.com:ip:axi_dma:7.1",
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"SX": "/processing_system7_0",
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"SI": "S_AXI_HP0",
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"SS": "HP0_DDR_LOWOCM",
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"SV": "xilinx.com:ip:processing_system7:5.5",
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"TM": "both",
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"TU": "memory"
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},
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"V6": {
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"VT": "AC",
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"BA": "0x00000000",
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"HA": "0x1FFFFFFF",
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"BP": "C_BASEADDR",
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"HP": "C_HIGHADDR",
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"MA": "Data_S2MM",
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"MX": "/axi_dma_3",
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"MI": "M_AXI_S2MM",
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"MS": "SEG_processing_system7_0_HP0_DDR_LOWOCM",
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"MV": "xilinx.com:ip:axi_dma:7.1",
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"SX": "/processing_system7_0",
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"SI": "S_AXI_HP0",
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"SS": "HP0_DDR_LOWOCM",
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"SV": "xilinx.com:ip:processing_system7:5.5",
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"TM": "both",
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"TU": "memory"
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},
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"V7": {
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"VT": "AC",
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"BA": "0x40000000",
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"HA": "0x40001FFF",
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@@ -242,7 +278,7 @@
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"TM": "both",
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"TU": "memory"
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},
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"V6": {
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"V8": {
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"VT": "AC",
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"BA": "0x40400000",
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"HA": "0x4040FFFF",
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@@ -260,7 +296,7 @@
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"TM": "both",
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"TU": "register"
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},
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"V7": {
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"V9": {
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"VT": "AC",
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"BA": "0x40410000",
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"HA": "0x4041FFFF",
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@@ -278,7 +314,43 @@
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"TM": "both",
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"TU": "register"
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},
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"V8": {
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"V10": {
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"VT": "AC",
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"BA": "0x40420000",
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"HA": "0x4042FFFF",
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"BP": "C_BASEADDR",
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"HP": "C_HIGHADDR",
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"MA": "Data",
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"MX": "/processing_system7_0",
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"MI": "M_AXI_GP0",
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"MS": "SEG_axi_dma_2_Reg",
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"MV": "xilinx.com:ip:processing_system7:5.5",
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"SX": "/axi_dma_2",
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"SI": "S_AXI_LITE",
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"SS": "Reg",
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"SV": "xilinx.com:ip:axi_dma:7.1",
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"TM": "both",
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"TU": "register"
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},
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"V11": {
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"VT": "AC",
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"BA": "0x40430000",
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"HA": "0x4043FFFF",
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"BP": "C_BASEADDR",
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"HP": "C_HIGHADDR",
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"MA": "Data",
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"MX": "/processing_system7_0",
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"MI": "M_AXI_GP0",
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"MS": "SEG_axi_dma_3_Reg",
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"MV": "xilinx.com:ip:processing_system7:5.5",
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"SX": "/axi_dma_3",
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"SI": "S_AXI_LITE",
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"SS": "Reg",
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"SV": "xilinx.com:ip:axi_dma:7.1",
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"TM": "both",
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"TU": "register"
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},
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"V12": {
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"VT": "AC",
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"BA": "0x41200000",
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"HA": "0x4120FFFF",
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@@ -296,43 +368,169 @@
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"TM": "both",
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"TU": "register"
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},
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"V9": {
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"V13": {
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"VT": "AC",
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"BA": "0x41600000",
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"HA": "0x4160FFFF",
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"BA": "0x41210000",
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"HA": "0x4121FFFF",
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"BP": "C_BASEADDR",
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"HP": "C_HIGHADDR",
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"MA": "Data",
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"MX": "/processing_system7_0",
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"MI": "M_AXI_GP0",
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"MS": "SEG_axi_iic_0_Reg",
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"MS": "SEG_CHANN_EN_Reg",
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"MV": "xilinx.com:ip:processing_system7:5.5",
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"SX": "/axi_iic_0",
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"SX": "/CHANN_EN",
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"SI": "S_AXI",
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"SS": "Reg",
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"SV": "xilinx.com:ip:axi_iic:2.1",
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"SV": "xilinx.com:ip:axi_gpio:2.0",
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"TM": "both",
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"TU": "register"
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},
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"V10": {
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"V14": {
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"VT": "AC",
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"BA": "0x41610000",
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"HA": "0x4161FFFF",
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"BA": "0x41220000",
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"HA": "0x4122FFFF",
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"BP": "C_BASEADDR",
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"HP": "C_HIGHADDR",
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"MA": "Data",
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"MX": "/processing_system7_0",
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"MI": "M_AXI_GP0",
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"MS": "SEG_axi_iic_1_Reg",
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"MS": "SEG_CHANN_SEL_Reg",
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"MV": "xilinx.com:ip:processing_system7:5.5",
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"SX": "/axi_iic_1",
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"SX": "/CHANN_SEL",
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"SI": "S_AXI",
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"SS": "Reg",
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"SV": "xilinx.com:ip:axi_iic:2.1",
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"SV": "xilinx.com:ip:axi_gpio:2.0",
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"TM": "both",
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"TU": "register"
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},
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"V11": {
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"V15": {
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"VT": "AC",
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"BA": "0x41230000",
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"HA": "0x4123FFFF",
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"BP": "C_BASEADDR",
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"HP": "C_HIGHADDR",
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"MA": "Data",
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"MX": "/processing_system7_0",
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"MI": "M_AXI_GP0",
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"MS": "SEG_RST_AD5941_Reg",
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"MV": "xilinx.com:ip:processing_system7:5.5",
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"SX": "/RST_AD5941",
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"SI": "S_AXI",
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"SS": "Reg",
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"SV": "xilinx.com:ip:axi_gpio:2.0",
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"TM": "both",
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"TU": "register"
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},
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"V16": {
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"VT": "AC",
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"BA": "0x41240000",
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"HA": "0x4124FFFF",
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"BP": "C_BASEADDR",
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"HP": "C_HIGHADDR",
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"MA": "Data",
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"MX": "/processing_system7_0",
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"MI": "M_AXI_GP0",
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"MS": "SEG_Z_IO_Reg",
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"MV": "xilinx.com:ip:processing_system7:5.5",
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"SX": "/Z_IO",
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"SI": "S_AXI",
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"SS": "Reg",
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"SV": "xilinx.com:ip:axi_gpio:2.0",
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"TM": "both",
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"TU": "register"
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},
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"V17": {
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"VT": "AC",
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"BA": "0x41250000",
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"HA": "0x4125FFFF",
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"BP": "C_BASEADDR",
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"HP": "C_HIGHADDR",
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"MA": "Data",
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"MX": "/processing_system7_0",
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"MI": "M_AXI_GP0",
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"MS": "SEG_GPIO_Reg",
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"MV": "xilinx.com:ip:processing_system7:5.5",
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"SX": "/GPIO",
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"SI": "S_AXI",
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"SS": "Reg",
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"SV": "xilinx.com:ip:axi_gpio:2.0",
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"TM": "both",
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"TU": "register"
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},
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"V18": {
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"VT": "AC",
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"BA": "0x41260000",
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"HA": "0x4126FFFF",
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"BP": "C_BASEADDR",
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"HP": "C_HIGHADDR",
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"MA": "Data",
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"MX": "/processing_system7_0",
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"MI": "M_AXI_GP0",
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"MS": "SEG_ELEC_MUX_IN_Reg",
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"MV": "xilinx.com:ip:processing_system7:5.5",
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"SX": "/ELEC_MUX_IN",
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"SI": "S_AXI",
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"SS": "Reg",
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"SV": "xilinx.com:ip:axi_gpio:2.0",
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"TM": "both",
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"TU": "register"
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},
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"V19": {
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"VT": "AC",
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"BA": "0x41E00000",
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"HA": "0x41E0FFFF",
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"BP": "C_BASEADDR",
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"HP": "C_HIGHADDR",
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"MA": "Data",
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"MX": "/processing_system7_0",
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"MI": "M_AXI_GP0",
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"MS": "SEG_STIM_SPI_Reg",
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"MV": "xilinx.com:ip:processing_system7:5.5",
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"SX": "/STIM_SPI",
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"SI": "AXI_LITE",
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"SS": "Reg",
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"SV": "xilinx.com:ip:axi_quad_spi:3.2",
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"TM": "both",
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"TU": "register"
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},
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"V20": {
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"VT": "AC",
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"BA": "0x41E10000",
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"HA": "0x41E1FFFF",
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"BP": "C_BASEADDR",
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"HP": "C_HIGHADDR",
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"MA": "Data",
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"MX": "/processing_system7_0",
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"MI": "M_AXI_GP0",
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"MS": "SEG_CUR_SPI_Reg",
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"MV": "xilinx.com:ip:processing_system7:5.5",
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"SX": "/CUR_SPI",
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"SI": "AXI_LITE",
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"SS": "Reg",
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"SV": "xilinx.com:ip:axi_quad_spi:3.2",
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"TM": "both",
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"TU": "register"
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},
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"V21": {
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"VT": "AC",
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"BA": "0x41E20000",
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"HA": "0x41E2FFFF",
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"BP": "C_BASEADDR",
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"HP": "C_HIGHADDR",
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"MA": "Data",
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"MX": "/processing_system7_0",
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"MI": "M_AXI_GP0",
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"MS": "SEG_ZCHECK_SPI_Reg",
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"MV": "xilinx.com:ip:processing_system7:5.5",
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"SX": "/ZCHECK_SPI",
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||||
"SI": "AXI_LITE",
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||||
"SS": "Reg",
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||||
"SV": "xilinx.com:ip:axi_quad_spi:3.2",
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"TM": "both",
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"TU": "register"
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},
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"V22": {
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"VT": "AC",
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"BA": "0x42000000",
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"HA": "0x42001FFF",
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@@ -350,7 +548,7 @@
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"TM": "both",
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"TU": "memory"
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},
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"V12": {
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"V23": {
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"VT": "AC",
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"BA": "0x44000000",
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"HA": "0x44001FFF",
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@@ -368,7 +566,7 @@
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"TM": "both",
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"TU": "memory"
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},
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"V13": {
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"V24": {
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"VT": "AC",
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"BA": "0x46000000",
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"HA": "0x46001FFF",
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@@ -386,7 +584,7 @@
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"TM": "both",
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"TU": "memory"
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},
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"V14": {
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"V25": {
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"VT": "AC",
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"BA": "0x48000000",
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"HA": "0x48001FFF",
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@@ -403,6 +601,60 @@
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"SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
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"TM": "both",
|
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"TU": "memory"
|
||||
},
|
||||
"V26": {
|
||||
"VT": "AC",
|
||||
"BA": "0x4A000000",
|
||||
"HA": "0x4A001FFF",
|
||||
"BP": "C_S_AXI_BASEADDR",
|
||||
"HP": "C_S_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_bram_ctrl_5_Mem0",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_bram_ctrl_5",
|
||||
"SI": "S_AXI",
|
||||
"SS": "Mem0",
|
||||
"SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"TM": "both",
|
||||
"TU": "memory"
|
||||
},
|
||||
"V27": {
|
||||
"VT": "AC",
|
||||
"BA": "0x4C000000",
|
||||
"HA": "0x4C001FFF",
|
||||
"BP": "C_S_AXI_BASEADDR",
|
||||
"HP": "C_S_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_bram_ctrl_6_Mem0",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_bram_ctrl_6",
|
||||
"SI": "S_AXI",
|
||||
"SS": "Mem0",
|
||||
"SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"TM": "both",
|
||||
"TU": "memory"
|
||||
},
|
||||
"V28": {
|
||||
"VT": "AC",
|
||||
"BA": "0x4E000000",
|
||||
"HA": "0x4E001FFF",
|
||||
"BP": "C_S_AXI_BASEADDR",
|
||||
"HP": "C_S_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_bram_ctrl_7_Mem0",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_bram_ctrl_7",
|
||||
"SI": "S_AXI",
|
||||
"SS": "Mem0",
|
||||
"SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"TM": "both",
|
||||
"TU": "memory"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
@@ -473,6 +725,76 @@
|
||||
"src": "V14",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V15",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V16",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V17",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V18",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V19",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V20",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V21",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V22",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V23",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V24",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V25",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V26",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V27",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V28",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
}
|
||||
]
|
||||
}
|
||||
|
||||
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="design_a9_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1714397435"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1714397435"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1714397435"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1714397435"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1787204488"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1787204488"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1787204488"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1787204488"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\design_a9_1.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
|
||||
@@ -2,8 +2,8 @@
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
//Date : Mon Apr 29 21:29:57 2024
|
||||
//Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
//Date : Thu Aug 20 13:40:13 2026
|
||||
//Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_a9_1_wrapper.bd
|
||||
//Design : design_a9_1_wrapper
|
||||
//Purpose : IP block netlist
|
||||
@@ -11,7 +11,9 @@
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module design_a9_1_wrapper
|
||||
(DDR_addr,
|
||||
(CHANN_EN_tri_io,
|
||||
CHANN_SEL_tri_io,
|
||||
DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
@@ -32,6 +34,15 @@ module design_a9_1_wrapper
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb,
|
||||
RST_AD5941_tri_io,
|
||||
Z_IO_tri_io,
|
||||
bram_cur_addr,
|
||||
bram_cur_clk,
|
||||
bram_cur_din,
|
||||
bram_cur_dout,
|
||||
bram_cur_en,
|
||||
bram_cur_rst,
|
||||
bram_cur_we,
|
||||
bram_eeg_addr,
|
||||
bram_eeg_clk,
|
||||
bram_eeg_din,
|
||||
@@ -46,6 +57,13 @@ module design_a9_1_wrapper
|
||||
bram_emg_en,
|
||||
bram_emg_rst,
|
||||
bram_emg_we,
|
||||
bram_imp_addr,
|
||||
bram_imp_clk,
|
||||
bram_imp_din,
|
||||
bram_imp_dout,
|
||||
bram_imp_en,
|
||||
bram_imp_rst,
|
||||
bram_imp_we,
|
||||
bram_mems_addr,
|
||||
bram_mems_clk,
|
||||
bram_mems_din,
|
||||
@@ -57,6 +75,13 @@ module design_a9_1_wrapper
|
||||
bram_msg_clk,
|
||||
bram_msg_din,
|
||||
bram_msg_dout,
|
||||
bram_msg_emg_addr,
|
||||
bram_msg_emg_clk,
|
||||
bram_msg_emg_din,
|
||||
bram_msg_emg_dout,
|
||||
bram_msg_emg_en,
|
||||
bram_msg_emg_rst,
|
||||
bram_msg_emg_we,
|
||||
bram_msg_en,
|
||||
bram_msg_rst,
|
||||
bram_msg_we,
|
||||
@@ -68,12 +93,14 @@ module design_a9_1_wrapper
|
||||
bram_stim_rst,
|
||||
bram_stim_we,
|
||||
clk,
|
||||
cur_spi_io0_io,
|
||||
cur_spi_io1_io,
|
||||
cur_spi_sck_io,
|
||||
cur_spi_ss_io,
|
||||
elec_mux_in_tri_io,
|
||||
gpio0_0_tri_i,
|
||||
gpio0_1_tri_o,
|
||||
iic0_scl_io,
|
||||
iic0_sda_io,
|
||||
iic1_scl_io,
|
||||
iic1_sda_io,
|
||||
gpio0_tri_io,
|
||||
int0,
|
||||
int1,
|
||||
int2,
|
||||
@@ -83,12 +110,34 @@ module design_a9_1_wrapper
|
||||
m_axis_stim_tready,
|
||||
m_axis_stim_tvalid,
|
||||
rst_n,
|
||||
s_axis_record1_tdata,
|
||||
s_axis_record1_tkeep,
|
||||
s_axis_record1_tlast,
|
||||
s_axis_record1_tready,
|
||||
s_axis_record1_tvalid,
|
||||
s_axis_record2_tdata,
|
||||
s_axis_record2_tkeep,
|
||||
s_axis_record2_tlast,
|
||||
s_axis_record2_tready,
|
||||
s_axis_record2_tvalid,
|
||||
s_axis_record_tdata,
|
||||
s_axis_record_tfull,
|
||||
s_axis_record_tfull1,
|
||||
s_axis_record_tfull2,
|
||||
s_axis_record_tkeep,
|
||||
s_axis_record_tlast,
|
||||
s_axis_record_tready,
|
||||
s_axis_record_tvalid);
|
||||
s_axis_record_tvalid,
|
||||
stim_spi_io0_io,
|
||||
stim_spi_io1_io,
|
||||
stim_spi_sck_io,
|
||||
stim_spi_ss_io,
|
||||
zcheck_spi_io0_io,
|
||||
zcheck_spi_io1_io,
|
||||
zcheck_spi_sck_io,
|
||||
zcheck_spi_ss_io);
|
||||
inout [1:0]CHANN_EN_tri_io;
|
||||
inout [3:0]CHANN_SEL_tri_io;
|
||||
inout [14:0]DDR_addr;
|
||||
inout [2:0]DDR_ba;
|
||||
inout DDR_cas_n;
|
||||
@@ -110,6 +159,15 @@ module design_a9_1_wrapper
|
||||
inout FIXED_IO_ps_clk;
|
||||
inout FIXED_IO_ps_porb;
|
||||
inout FIXED_IO_ps_srstb;
|
||||
inout [0:0]RST_AD5941_tri_io;
|
||||
inout [0:0]Z_IO_tri_io;
|
||||
output [12:0]bram_cur_addr;
|
||||
output bram_cur_clk;
|
||||
output [31:0]bram_cur_din;
|
||||
input [31:0]bram_cur_dout;
|
||||
output bram_cur_en;
|
||||
output bram_cur_rst;
|
||||
output [3:0]bram_cur_we;
|
||||
output [12:0]bram_eeg_addr;
|
||||
output bram_eeg_clk;
|
||||
output [31:0]bram_eeg_din;
|
||||
@@ -124,6 +182,13 @@ module design_a9_1_wrapper
|
||||
output bram_emg_en;
|
||||
output bram_emg_rst;
|
||||
output [3:0]bram_emg_we;
|
||||
output [12:0]bram_imp_addr;
|
||||
output bram_imp_clk;
|
||||
output [31:0]bram_imp_din;
|
||||
input [31:0]bram_imp_dout;
|
||||
output bram_imp_en;
|
||||
output bram_imp_rst;
|
||||
output [3:0]bram_imp_we;
|
||||
output [12:0]bram_mems_addr;
|
||||
output bram_mems_clk;
|
||||
output [31:0]bram_mems_din;
|
||||
@@ -135,6 +200,13 @@ module design_a9_1_wrapper
|
||||
output bram_msg_clk;
|
||||
output [31:0]bram_msg_din;
|
||||
input [31:0]bram_msg_dout;
|
||||
output [12:0]bram_msg_emg_addr;
|
||||
output bram_msg_emg_clk;
|
||||
output [31:0]bram_msg_emg_din;
|
||||
input [31:0]bram_msg_emg_dout;
|
||||
output bram_msg_emg_en;
|
||||
output bram_msg_emg_rst;
|
||||
output [3:0]bram_msg_emg_we;
|
||||
output bram_msg_en;
|
||||
output bram_msg_rst;
|
||||
output [3:0]bram_msg_we;
|
||||
@@ -146,12 +218,14 @@ module design_a9_1_wrapper
|
||||
output bram_stim_rst;
|
||||
output [3:0]bram_stim_we;
|
||||
output clk;
|
||||
inout cur_spi_io0_io;
|
||||
inout cur_spi_io1_io;
|
||||
inout cur_spi_sck_io;
|
||||
inout [0:0]cur_spi_ss_io;
|
||||
inout [3:0]elec_mux_in_tri_io;
|
||||
input [7:0]gpio0_0_tri_i;
|
||||
output [31:0]gpio0_1_tri_o;
|
||||
inout iic0_scl_io;
|
||||
inout iic0_sda_io;
|
||||
inout iic1_scl_io;
|
||||
inout iic1_sda_io;
|
||||
inout [2:0]gpio0_tri_io;
|
||||
input int0;
|
||||
input int1;
|
||||
input int2;
|
||||
@@ -161,13 +235,57 @@ module design_a9_1_wrapper
|
||||
input m_axis_stim_tready;
|
||||
output m_axis_stim_tvalid;
|
||||
output [0:0]rst_n;
|
||||
input [31:0]s_axis_record1_tdata;
|
||||
input [3:0]s_axis_record1_tkeep;
|
||||
input s_axis_record1_tlast;
|
||||
output s_axis_record1_tready;
|
||||
input s_axis_record1_tvalid;
|
||||
input [31:0]s_axis_record2_tdata;
|
||||
input [3:0]s_axis_record2_tkeep;
|
||||
input s_axis_record2_tlast;
|
||||
output s_axis_record2_tready;
|
||||
input s_axis_record2_tvalid;
|
||||
input [7:0]s_axis_record_tdata;
|
||||
output s_axis_record_tfull;
|
||||
output s_axis_record_tfull1;
|
||||
output s_axis_record_tfull2;
|
||||
input [0:0]s_axis_record_tkeep;
|
||||
input s_axis_record_tlast;
|
||||
output s_axis_record_tready;
|
||||
input s_axis_record_tvalid;
|
||||
inout stim_spi_io0_io;
|
||||
inout stim_spi_io1_io;
|
||||
inout stim_spi_sck_io;
|
||||
inout [0:0]stim_spi_ss_io;
|
||||
inout zcheck_spi_io0_io;
|
||||
inout zcheck_spi_io1_io;
|
||||
inout zcheck_spi_sck_io;
|
||||
inout [0:0]zcheck_spi_ss_io;
|
||||
|
||||
wire [0:0]CHANN_EN_tri_i_0;
|
||||
wire [1:1]CHANN_EN_tri_i_1;
|
||||
wire [0:0]CHANN_EN_tri_io_0;
|
||||
wire [1:1]CHANN_EN_tri_io_1;
|
||||
wire [0:0]CHANN_EN_tri_o_0;
|
||||
wire [1:1]CHANN_EN_tri_o_1;
|
||||
wire [0:0]CHANN_EN_tri_t_0;
|
||||
wire [1:1]CHANN_EN_tri_t_1;
|
||||
wire [0:0]CHANN_SEL_tri_i_0;
|
||||
wire [1:1]CHANN_SEL_tri_i_1;
|
||||
wire [2:2]CHANN_SEL_tri_i_2;
|
||||
wire [3:3]CHANN_SEL_tri_i_3;
|
||||
wire [0:0]CHANN_SEL_tri_io_0;
|
||||
wire [1:1]CHANN_SEL_tri_io_1;
|
||||
wire [2:2]CHANN_SEL_tri_io_2;
|
||||
wire [3:3]CHANN_SEL_tri_io_3;
|
||||
wire [0:0]CHANN_SEL_tri_o_0;
|
||||
wire [1:1]CHANN_SEL_tri_o_1;
|
||||
wire [2:2]CHANN_SEL_tri_o_2;
|
||||
wire [3:3]CHANN_SEL_tri_o_3;
|
||||
wire [0:0]CHANN_SEL_tri_t_0;
|
||||
wire [1:1]CHANN_SEL_tri_t_1;
|
||||
wire [2:2]CHANN_SEL_tri_t_2;
|
||||
wire [3:3]CHANN_SEL_tri_t_3;
|
||||
wire [14:0]DDR_addr;
|
||||
wire [2:0]DDR_ba;
|
||||
wire DDR_cas_n;
|
||||
@@ -189,6 +307,21 @@ module design_a9_1_wrapper
|
||||
wire FIXED_IO_ps_clk;
|
||||
wire FIXED_IO_ps_porb;
|
||||
wire FIXED_IO_ps_srstb;
|
||||
wire [0:0]RST_AD5941_tri_i_0;
|
||||
wire [0:0]RST_AD5941_tri_io_0;
|
||||
wire [0:0]RST_AD5941_tri_o_0;
|
||||
wire [0:0]RST_AD5941_tri_t_0;
|
||||
wire [0:0]Z_IO_tri_i_0;
|
||||
wire [0:0]Z_IO_tri_io_0;
|
||||
wire [0:0]Z_IO_tri_o_0;
|
||||
wire [0:0]Z_IO_tri_t_0;
|
||||
wire [12:0]bram_cur_addr;
|
||||
wire bram_cur_clk;
|
||||
wire [31:0]bram_cur_din;
|
||||
wire [31:0]bram_cur_dout;
|
||||
wire bram_cur_en;
|
||||
wire bram_cur_rst;
|
||||
wire [3:0]bram_cur_we;
|
||||
wire [12:0]bram_eeg_addr;
|
||||
wire bram_eeg_clk;
|
||||
wire [31:0]bram_eeg_din;
|
||||
@@ -203,6 +336,13 @@ module design_a9_1_wrapper
|
||||
wire bram_emg_en;
|
||||
wire bram_emg_rst;
|
||||
wire [3:0]bram_emg_we;
|
||||
wire [12:0]bram_imp_addr;
|
||||
wire bram_imp_clk;
|
||||
wire [31:0]bram_imp_din;
|
||||
wire [31:0]bram_imp_dout;
|
||||
wire bram_imp_en;
|
||||
wire bram_imp_rst;
|
||||
wire [3:0]bram_imp_we;
|
||||
wire [12:0]bram_mems_addr;
|
||||
wire bram_mems_clk;
|
||||
wire [31:0]bram_mems_din;
|
||||
@@ -214,6 +354,13 @@ module design_a9_1_wrapper
|
||||
wire bram_msg_clk;
|
||||
wire [31:0]bram_msg_din;
|
||||
wire [31:0]bram_msg_dout;
|
||||
wire [12:0]bram_msg_emg_addr;
|
||||
wire bram_msg_emg_clk;
|
||||
wire [31:0]bram_msg_emg_din;
|
||||
wire [31:0]bram_msg_emg_dout;
|
||||
wire bram_msg_emg_en;
|
||||
wire bram_msg_emg_rst;
|
||||
wire [3:0]bram_msg_emg_we;
|
||||
wire bram_msg_en;
|
||||
wire bram_msg_rst;
|
||||
wire [3:0]bram_msg_we;
|
||||
@@ -225,24 +372,52 @@ module design_a9_1_wrapper
|
||||
wire bram_stim_rst;
|
||||
wire [3:0]bram_stim_we;
|
||||
wire clk;
|
||||
wire cur_spi_io0_i;
|
||||
wire cur_spi_io0_io;
|
||||
wire cur_spi_io0_o;
|
||||
wire cur_spi_io0_t;
|
||||
wire cur_spi_io1_i;
|
||||
wire cur_spi_io1_io;
|
||||
wire cur_spi_io1_o;
|
||||
wire cur_spi_io1_t;
|
||||
wire cur_spi_sck_i;
|
||||
wire cur_spi_sck_io;
|
||||
wire cur_spi_sck_o;
|
||||
wire cur_spi_sck_t;
|
||||
wire [0:0]cur_spi_ss_i_0;
|
||||
wire [0:0]cur_spi_ss_io_0;
|
||||
wire [0:0]cur_spi_ss_o_0;
|
||||
wire cur_spi_ss_t;
|
||||
wire [0:0]elec_mux_in_tri_i_0;
|
||||
wire [1:1]elec_mux_in_tri_i_1;
|
||||
wire [2:2]elec_mux_in_tri_i_2;
|
||||
wire [3:3]elec_mux_in_tri_i_3;
|
||||
wire [0:0]elec_mux_in_tri_io_0;
|
||||
wire [1:1]elec_mux_in_tri_io_1;
|
||||
wire [2:2]elec_mux_in_tri_io_2;
|
||||
wire [3:3]elec_mux_in_tri_io_3;
|
||||
wire [0:0]elec_mux_in_tri_o_0;
|
||||
wire [1:1]elec_mux_in_tri_o_1;
|
||||
wire [2:2]elec_mux_in_tri_o_2;
|
||||
wire [3:3]elec_mux_in_tri_o_3;
|
||||
wire [0:0]elec_mux_in_tri_t_0;
|
||||
wire [1:1]elec_mux_in_tri_t_1;
|
||||
wire [2:2]elec_mux_in_tri_t_2;
|
||||
wire [3:3]elec_mux_in_tri_t_3;
|
||||
wire [7:0]gpio0_0_tri_i;
|
||||
wire [31:0]gpio0_1_tri_o;
|
||||
wire iic0_scl_i;
|
||||
wire iic0_scl_io;
|
||||
wire iic0_scl_o;
|
||||
wire iic0_scl_t;
|
||||
wire iic0_sda_i;
|
||||
wire iic0_sda_io;
|
||||
wire iic0_sda_o;
|
||||
wire iic0_sda_t;
|
||||
wire iic1_scl_i;
|
||||
wire iic1_scl_io;
|
||||
wire iic1_scl_o;
|
||||
wire iic1_scl_t;
|
||||
wire iic1_sda_i;
|
||||
wire iic1_sda_io;
|
||||
wire iic1_sda_o;
|
||||
wire iic1_sda_t;
|
||||
wire [0:0]gpio0_tri_i_0;
|
||||
wire [1:1]gpio0_tri_i_1;
|
||||
wire [2:2]gpio0_tri_i_2;
|
||||
wire [0:0]gpio0_tri_io_0;
|
||||
wire [1:1]gpio0_tri_io_1;
|
||||
wire [2:2]gpio0_tri_io_2;
|
||||
wire [0:0]gpio0_tri_o_0;
|
||||
wire [1:1]gpio0_tri_o_1;
|
||||
wire [2:2]gpio0_tri_o_2;
|
||||
wire [0:0]gpio0_tri_t_0;
|
||||
wire [1:1]gpio0_tri_t_1;
|
||||
wire [2:2]gpio0_tri_t_2;
|
||||
wire int0;
|
||||
wire int1;
|
||||
wire int2;
|
||||
@@ -252,15 +427,125 @@ module design_a9_1_wrapper
|
||||
wire m_axis_stim_tready;
|
||||
wire m_axis_stim_tvalid;
|
||||
wire [0:0]rst_n;
|
||||
wire [31:0]s_axis_record1_tdata;
|
||||
wire [3:0]s_axis_record1_tkeep;
|
||||
wire s_axis_record1_tlast;
|
||||
wire s_axis_record1_tready;
|
||||
wire s_axis_record1_tvalid;
|
||||
wire [31:0]s_axis_record2_tdata;
|
||||
wire [3:0]s_axis_record2_tkeep;
|
||||
wire s_axis_record2_tlast;
|
||||
wire s_axis_record2_tready;
|
||||
wire s_axis_record2_tvalid;
|
||||
wire [7:0]s_axis_record_tdata;
|
||||
wire s_axis_record_tfull;
|
||||
wire s_axis_record_tfull1;
|
||||
wire s_axis_record_tfull2;
|
||||
wire [0:0]s_axis_record_tkeep;
|
||||
wire s_axis_record_tlast;
|
||||
wire s_axis_record_tready;
|
||||
wire s_axis_record_tvalid;
|
||||
wire stim_spi_io0_i;
|
||||
wire stim_spi_io0_io;
|
||||
wire stim_spi_io0_o;
|
||||
wire stim_spi_io0_t;
|
||||
wire stim_spi_io1_i;
|
||||
wire stim_spi_io1_io;
|
||||
wire stim_spi_io1_o;
|
||||
wire stim_spi_io1_t;
|
||||
wire stim_spi_sck_i;
|
||||
wire stim_spi_sck_io;
|
||||
wire stim_spi_sck_o;
|
||||
wire stim_spi_sck_t;
|
||||
wire [0:0]stim_spi_ss_i_0;
|
||||
wire [0:0]stim_spi_ss_io_0;
|
||||
wire [0:0]stim_spi_ss_o_0;
|
||||
wire stim_spi_ss_t;
|
||||
wire zcheck_spi_io0_i;
|
||||
wire zcheck_spi_io0_io;
|
||||
wire zcheck_spi_io0_o;
|
||||
wire zcheck_spi_io0_t;
|
||||
wire zcheck_spi_io1_i;
|
||||
wire zcheck_spi_io1_io;
|
||||
wire zcheck_spi_io1_o;
|
||||
wire zcheck_spi_io1_t;
|
||||
wire zcheck_spi_sck_i;
|
||||
wire zcheck_spi_sck_io;
|
||||
wire zcheck_spi_sck_o;
|
||||
wire zcheck_spi_sck_t;
|
||||
wire [0:0]zcheck_spi_ss_i_0;
|
||||
wire [0:0]zcheck_spi_ss_io_0;
|
||||
wire [0:0]zcheck_spi_ss_o_0;
|
||||
wire zcheck_spi_ss_t;
|
||||
|
||||
IOBUF CHANN_EN_tri_iobuf_0
|
||||
(.I(CHANN_EN_tri_o_0),
|
||||
.IO(CHANN_EN_tri_io[0]),
|
||||
.O(CHANN_EN_tri_i_0),
|
||||
.T(CHANN_EN_tri_t_0));
|
||||
IOBUF CHANN_EN_tri_iobuf_1
|
||||
(.I(CHANN_EN_tri_o_1),
|
||||
.IO(CHANN_EN_tri_io[1]),
|
||||
.O(CHANN_EN_tri_i_1),
|
||||
.T(CHANN_EN_tri_t_1));
|
||||
IOBUF CHANN_SEL_tri_iobuf_0
|
||||
(.I(CHANN_SEL_tri_o_0),
|
||||
.IO(CHANN_SEL_tri_io[0]),
|
||||
.O(CHANN_SEL_tri_i_0),
|
||||
.T(CHANN_SEL_tri_t_0));
|
||||
IOBUF CHANN_SEL_tri_iobuf_1
|
||||
(.I(CHANN_SEL_tri_o_1),
|
||||
.IO(CHANN_SEL_tri_io[1]),
|
||||
.O(CHANN_SEL_tri_i_1),
|
||||
.T(CHANN_SEL_tri_t_1));
|
||||
IOBUF CHANN_SEL_tri_iobuf_2
|
||||
(.I(CHANN_SEL_tri_o_2),
|
||||
.IO(CHANN_SEL_tri_io[2]),
|
||||
.O(CHANN_SEL_tri_i_2),
|
||||
.T(CHANN_SEL_tri_t_2));
|
||||
IOBUF CHANN_SEL_tri_iobuf_3
|
||||
(.I(CHANN_SEL_tri_o_3),
|
||||
.IO(CHANN_SEL_tri_io[3]),
|
||||
.O(CHANN_SEL_tri_i_3),
|
||||
.T(CHANN_SEL_tri_t_3));
|
||||
IOBUF RST_AD5941_tri_iobuf_0
|
||||
(.I(RST_AD5941_tri_o_0),
|
||||
.IO(RST_AD5941_tri_io[0]),
|
||||
.O(RST_AD5941_tri_i_0),
|
||||
.T(RST_AD5941_tri_t_0));
|
||||
IOBUF Z_IO_tri_iobuf_0
|
||||
(.I(Z_IO_tri_o_0),
|
||||
.IO(Z_IO_tri_io[0]),
|
||||
.O(Z_IO_tri_i_0),
|
||||
.T(Z_IO_tri_t_0));
|
||||
IOBUF cur_spi_io0_iobuf
|
||||
(.I(cur_spi_io0_o),
|
||||
.IO(cur_spi_io0_io),
|
||||
.O(cur_spi_io0_i),
|
||||
.T(cur_spi_io0_t));
|
||||
IOBUF cur_spi_io1_iobuf
|
||||
(.I(cur_spi_io1_o),
|
||||
.IO(cur_spi_io1_io),
|
||||
.O(cur_spi_io1_i),
|
||||
.T(cur_spi_io1_t));
|
||||
IOBUF cur_spi_sck_iobuf
|
||||
(.I(cur_spi_sck_o),
|
||||
.IO(cur_spi_sck_io),
|
||||
.O(cur_spi_sck_i),
|
||||
.T(cur_spi_sck_t));
|
||||
IOBUF cur_spi_ss_iobuf_0
|
||||
(.I(cur_spi_ss_o_0),
|
||||
.IO(cur_spi_ss_io[0]),
|
||||
.O(cur_spi_ss_i_0),
|
||||
.T(cur_spi_ss_t));
|
||||
design_a9_1 design_a9_1_i
|
||||
(.DDR_addr(DDR_addr),
|
||||
(.CHANN_EN_tri_i({CHANN_EN_tri_i_1,CHANN_EN_tri_i_0}),
|
||||
.CHANN_EN_tri_o({CHANN_EN_tri_o_1,CHANN_EN_tri_o_0}),
|
||||
.CHANN_EN_tri_t({CHANN_EN_tri_t_1,CHANN_EN_tri_t_0}),
|
||||
.CHANN_SEL_tri_i({CHANN_SEL_tri_i_3,CHANN_SEL_tri_i_2,CHANN_SEL_tri_i_1,CHANN_SEL_tri_i_0}),
|
||||
.CHANN_SEL_tri_o({CHANN_SEL_tri_o_3,CHANN_SEL_tri_o_2,CHANN_SEL_tri_o_1,CHANN_SEL_tri_o_0}),
|
||||
.CHANN_SEL_tri_t({CHANN_SEL_tri_t_3,CHANN_SEL_tri_t_2,CHANN_SEL_tri_t_1,CHANN_SEL_tri_t_0}),
|
||||
.DDR_addr(DDR_addr),
|
||||
.DDR_ba(DDR_ba),
|
||||
.DDR_cas_n(DDR_cas_n),
|
||||
.DDR_ck_n(DDR_ck_n),
|
||||
@@ -281,6 +566,19 @@ module design_a9_1_wrapper
|
||||
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
|
||||
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
|
||||
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
|
||||
.RST_AD5941_tri_i(RST_AD5941_tri_i_0),
|
||||
.RST_AD5941_tri_o(RST_AD5941_tri_o_0),
|
||||
.RST_AD5941_tri_t(RST_AD5941_tri_t_0),
|
||||
.Z_IO_tri_i(Z_IO_tri_i_0),
|
||||
.Z_IO_tri_o(Z_IO_tri_o_0),
|
||||
.Z_IO_tri_t(Z_IO_tri_t_0),
|
||||
.bram_cur_addr(bram_cur_addr),
|
||||
.bram_cur_clk(bram_cur_clk),
|
||||
.bram_cur_din(bram_cur_din),
|
||||
.bram_cur_dout(bram_cur_dout),
|
||||
.bram_cur_en(bram_cur_en),
|
||||
.bram_cur_rst(bram_cur_rst),
|
||||
.bram_cur_we(bram_cur_we),
|
||||
.bram_eeg_addr(bram_eeg_addr),
|
||||
.bram_eeg_clk(bram_eeg_clk),
|
||||
.bram_eeg_din(bram_eeg_din),
|
||||
@@ -295,6 +593,13 @@ module design_a9_1_wrapper
|
||||
.bram_emg_en(bram_emg_en),
|
||||
.bram_emg_rst(bram_emg_rst),
|
||||
.bram_emg_we(bram_emg_we),
|
||||
.bram_imp_addr(bram_imp_addr),
|
||||
.bram_imp_clk(bram_imp_clk),
|
||||
.bram_imp_din(bram_imp_din),
|
||||
.bram_imp_dout(bram_imp_dout),
|
||||
.bram_imp_en(bram_imp_en),
|
||||
.bram_imp_rst(bram_imp_rst),
|
||||
.bram_imp_we(bram_imp_we),
|
||||
.bram_mems_addr(bram_mems_addr),
|
||||
.bram_mems_clk(bram_mems_clk),
|
||||
.bram_mems_din(bram_mems_din),
|
||||
@@ -306,6 +611,13 @@ module design_a9_1_wrapper
|
||||
.bram_msg_clk(bram_msg_clk),
|
||||
.bram_msg_din(bram_msg_din),
|
||||
.bram_msg_dout(bram_msg_dout),
|
||||
.bram_msg_emg_addr(bram_msg_emg_addr),
|
||||
.bram_msg_emg_clk(bram_msg_emg_clk),
|
||||
.bram_msg_emg_din(bram_msg_emg_din),
|
||||
.bram_msg_emg_dout(bram_msg_emg_dout),
|
||||
.bram_msg_emg_en(bram_msg_emg_en),
|
||||
.bram_msg_emg_rst(bram_msg_emg_rst),
|
||||
.bram_msg_emg_we(bram_msg_emg_we),
|
||||
.bram_msg_en(bram_msg_en),
|
||||
.bram_msg_rst(bram_msg_rst),
|
||||
.bram_msg_we(bram_msg_we),
|
||||
@@ -317,20 +629,26 @@ module design_a9_1_wrapper
|
||||
.bram_stim_rst(bram_stim_rst),
|
||||
.bram_stim_we(bram_stim_we),
|
||||
.clk(clk),
|
||||
.cur_spi_io0_i(cur_spi_io0_i),
|
||||
.cur_spi_io0_o(cur_spi_io0_o),
|
||||
.cur_spi_io0_t(cur_spi_io0_t),
|
||||
.cur_spi_io1_i(cur_spi_io1_i),
|
||||
.cur_spi_io1_o(cur_spi_io1_o),
|
||||
.cur_spi_io1_t(cur_spi_io1_t),
|
||||
.cur_spi_sck_i(cur_spi_sck_i),
|
||||
.cur_spi_sck_o(cur_spi_sck_o),
|
||||
.cur_spi_sck_t(cur_spi_sck_t),
|
||||
.cur_spi_ss_i(cur_spi_ss_i_0),
|
||||
.cur_spi_ss_o(cur_spi_ss_o_0),
|
||||
.cur_spi_ss_t(cur_spi_ss_t),
|
||||
.elec_mux_in_tri_i({elec_mux_in_tri_i_3,elec_mux_in_tri_i_2,elec_mux_in_tri_i_1,elec_mux_in_tri_i_0}),
|
||||
.elec_mux_in_tri_o({elec_mux_in_tri_o_3,elec_mux_in_tri_o_2,elec_mux_in_tri_o_1,elec_mux_in_tri_o_0}),
|
||||
.elec_mux_in_tri_t({elec_mux_in_tri_t_3,elec_mux_in_tri_t_2,elec_mux_in_tri_t_1,elec_mux_in_tri_t_0}),
|
||||
.gpio0_0_tri_i(gpio0_0_tri_i),
|
||||
.gpio0_1_tri_o(gpio0_1_tri_o),
|
||||
.iic0_scl_i(iic0_scl_i),
|
||||
.iic0_scl_o(iic0_scl_o),
|
||||
.iic0_scl_t(iic0_scl_t),
|
||||
.iic0_sda_i(iic0_sda_i),
|
||||
.iic0_sda_o(iic0_sda_o),
|
||||
.iic0_sda_t(iic0_sda_t),
|
||||
.iic1_scl_i(iic1_scl_i),
|
||||
.iic1_scl_o(iic1_scl_o),
|
||||
.iic1_scl_t(iic1_scl_t),
|
||||
.iic1_sda_i(iic1_sda_i),
|
||||
.iic1_sda_o(iic1_sda_o),
|
||||
.iic1_sda_t(iic1_sda_t),
|
||||
.gpio0_tri_i({gpio0_tri_i_2,gpio0_tri_i_1,gpio0_tri_i_0}),
|
||||
.gpio0_tri_o({gpio0_tri_o_2,gpio0_tri_o_1,gpio0_tri_o_0}),
|
||||
.gpio0_tri_t({gpio0_tri_t_2,gpio0_tri_t_1,gpio0_tri_t_0}),
|
||||
.int0(int0),
|
||||
.int1(int1),
|
||||
.int2(int2),
|
||||
@@ -340,30 +658,121 @@ module design_a9_1_wrapper
|
||||
.m_axis_stim_tready(m_axis_stim_tready),
|
||||
.m_axis_stim_tvalid(m_axis_stim_tvalid),
|
||||
.rst_n(rst_n),
|
||||
.s_axis_record1_tdata(s_axis_record1_tdata),
|
||||
.s_axis_record1_tkeep(s_axis_record1_tkeep),
|
||||
.s_axis_record1_tlast(s_axis_record1_tlast),
|
||||
.s_axis_record1_tready(s_axis_record1_tready),
|
||||
.s_axis_record1_tvalid(s_axis_record1_tvalid),
|
||||
.s_axis_record2_tdata(s_axis_record2_tdata),
|
||||
.s_axis_record2_tkeep(s_axis_record2_tkeep),
|
||||
.s_axis_record2_tlast(s_axis_record2_tlast),
|
||||
.s_axis_record2_tready(s_axis_record2_tready),
|
||||
.s_axis_record2_tvalid(s_axis_record2_tvalid),
|
||||
.s_axis_record_tdata(s_axis_record_tdata),
|
||||
.s_axis_record_tfull(s_axis_record_tfull),
|
||||
.s_axis_record_tfull1(s_axis_record_tfull1),
|
||||
.s_axis_record_tfull2(s_axis_record_tfull2),
|
||||
.s_axis_record_tkeep(s_axis_record_tkeep),
|
||||
.s_axis_record_tlast(s_axis_record_tlast),
|
||||
.s_axis_record_tready(s_axis_record_tready),
|
||||
.s_axis_record_tvalid(s_axis_record_tvalid));
|
||||
IOBUF iic0_scl_iobuf
|
||||
(.I(iic0_scl_o),
|
||||
.IO(iic0_scl_io),
|
||||
.O(iic0_scl_i),
|
||||
.T(iic0_scl_t));
|
||||
IOBUF iic0_sda_iobuf
|
||||
(.I(iic0_sda_o),
|
||||
.IO(iic0_sda_io),
|
||||
.O(iic0_sda_i),
|
||||
.T(iic0_sda_t));
|
||||
IOBUF iic1_scl_iobuf
|
||||
(.I(iic1_scl_o),
|
||||
.IO(iic1_scl_io),
|
||||
.O(iic1_scl_i),
|
||||
.T(iic1_scl_t));
|
||||
IOBUF iic1_sda_iobuf
|
||||
(.I(iic1_sda_o),
|
||||
.IO(iic1_sda_io),
|
||||
.O(iic1_sda_i),
|
||||
.T(iic1_sda_t));
|
||||
.s_axis_record_tvalid(s_axis_record_tvalid),
|
||||
.stim_spi_io0_i(stim_spi_io0_i),
|
||||
.stim_spi_io0_o(stim_spi_io0_o),
|
||||
.stim_spi_io0_t(stim_spi_io0_t),
|
||||
.stim_spi_io1_i(stim_spi_io1_i),
|
||||
.stim_spi_io1_o(stim_spi_io1_o),
|
||||
.stim_spi_io1_t(stim_spi_io1_t),
|
||||
.stim_spi_sck_i(stim_spi_sck_i),
|
||||
.stim_spi_sck_o(stim_spi_sck_o),
|
||||
.stim_spi_sck_t(stim_spi_sck_t),
|
||||
.stim_spi_ss_i(stim_spi_ss_i_0),
|
||||
.stim_spi_ss_o(stim_spi_ss_o_0),
|
||||
.stim_spi_ss_t(stim_spi_ss_t),
|
||||
.zcheck_spi_io0_i(zcheck_spi_io0_i),
|
||||
.zcheck_spi_io0_o(zcheck_spi_io0_o),
|
||||
.zcheck_spi_io0_t(zcheck_spi_io0_t),
|
||||
.zcheck_spi_io1_i(zcheck_spi_io1_i),
|
||||
.zcheck_spi_io1_o(zcheck_spi_io1_o),
|
||||
.zcheck_spi_io1_t(zcheck_spi_io1_t),
|
||||
.zcheck_spi_sck_i(zcheck_spi_sck_i),
|
||||
.zcheck_spi_sck_o(zcheck_spi_sck_o),
|
||||
.zcheck_spi_sck_t(zcheck_spi_sck_t),
|
||||
.zcheck_spi_ss_i(zcheck_spi_ss_i_0),
|
||||
.zcheck_spi_ss_o(zcheck_spi_ss_o_0),
|
||||
.zcheck_spi_ss_t(zcheck_spi_ss_t));
|
||||
IOBUF elec_mux_in_tri_iobuf_0
|
||||
(.I(elec_mux_in_tri_o_0),
|
||||
.IO(elec_mux_in_tri_io[0]),
|
||||
.O(elec_mux_in_tri_i_0),
|
||||
.T(elec_mux_in_tri_t_0));
|
||||
IOBUF elec_mux_in_tri_iobuf_1
|
||||
(.I(elec_mux_in_tri_o_1),
|
||||
.IO(elec_mux_in_tri_io[1]),
|
||||
.O(elec_mux_in_tri_i_1),
|
||||
.T(elec_mux_in_tri_t_1));
|
||||
IOBUF elec_mux_in_tri_iobuf_2
|
||||
(.I(elec_mux_in_tri_o_2),
|
||||
.IO(elec_mux_in_tri_io[2]),
|
||||
.O(elec_mux_in_tri_i_2),
|
||||
.T(elec_mux_in_tri_t_2));
|
||||
IOBUF elec_mux_in_tri_iobuf_3
|
||||
(.I(elec_mux_in_tri_o_3),
|
||||
.IO(elec_mux_in_tri_io[3]),
|
||||
.O(elec_mux_in_tri_i_3),
|
||||
.T(elec_mux_in_tri_t_3));
|
||||
IOBUF gpio0_tri_iobuf_0
|
||||
(.I(gpio0_tri_o_0),
|
||||
.IO(gpio0_tri_io[0]),
|
||||
.O(gpio0_tri_i_0),
|
||||
.T(gpio0_tri_t_0));
|
||||
IOBUF gpio0_tri_iobuf_1
|
||||
(.I(gpio0_tri_o_1),
|
||||
.IO(gpio0_tri_io[1]),
|
||||
.O(gpio0_tri_i_1),
|
||||
.T(gpio0_tri_t_1));
|
||||
IOBUF gpio0_tri_iobuf_2
|
||||
(.I(gpio0_tri_o_2),
|
||||
.IO(gpio0_tri_io[2]),
|
||||
.O(gpio0_tri_i_2),
|
||||
.T(gpio0_tri_t_2));
|
||||
IOBUF stim_spi_io0_iobuf
|
||||
(.I(stim_spi_io0_o),
|
||||
.IO(stim_spi_io0_io),
|
||||
.O(stim_spi_io0_i),
|
||||
.T(stim_spi_io0_t));
|
||||
IOBUF stim_spi_io1_iobuf
|
||||
(.I(stim_spi_io1_o),
|
||||
.IO(stim_spi_io1_io),
|
||||
.O(stim_spi_io1_i),
|
||||
.T(stim_spi_io1_t));
|
||||
IOBUF stim_spi_sck_iobuf
|
||||
(.I(stim_spi_sck_o),
|
||||
.IO(stim_spi_sck_io),
|
||||
.O(stim_spi_sck_i),
|
||||
.T(stim_spi_sck_t));
|
||||
IOBUF stim_spi_ss_iobuf_0
|
||||
(.I(stim_spi_ss_o_0),
|
||||
.IO(stim_spi_ss_io[0]),
|
||||
.O(stim_spi_ss_i_0),
|
||||
.T(stim_spi_ss_t));
|
||||
IOBUF zcheck_spi_io0_iobuf
|
||||
(.I(zcheck_spi_io0_o),
|
||||
.IO(zcheck_spi_io0_io),
|
||||
.O(zcheck_spi_io0_i),
|
||||
.T(zcheck_spi_io0_t));
|
||||
IOBUF zcheck_spi_io1_iobuf
|
||||
(.I(zcheck_spi_io1_o),
|
||||
.IO(zcheck_spi_io1_io),
|
||||
.O(zcheck_spi_io1_i),
|
||||
.T(zcheck_spi_io1_t));
|
||||
IOBUF zcheck_spi_sck_iobuf
|
||||
(.I(zcheck_spi_sck_o),
|
||||
.IO(zcheck_spi_sck_io),
|
||||
.O(zcheck_spi_sck_i),
|
||||
.T(zcheck_spi_sck_t));
|
||||
IOBUF zcheck_spi_ss_iobuf_0
|
||||
(.I(zcheck_spi_ss_o_0),
|
||||
.IO(zcheck_spi_ss_io[0]),
|
||||
.O(zcheck_spi_ss_i_0),
|
||||
.T(zcheck_spi_ss_t));
|
||||
endmodule
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
BIN
Binary file not shown.
+48
@@ -0,0 +1,48 @@
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
||||
+2109
File diff suppressed because it is too large
Load Diff
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
|
||||
|
||||
create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
|
||||
|
||||
################################################################################
|
||||
+1999
File diff suppressed because it is too large
Load Diff
+2224
File diff suppressed because it is too large
Load Diff
+46
@@ -0,0 +1,46 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Oct 28 21:02:58 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top design_a9_1_CHANN_EN_0 -prefix
|
||||
// design_a9_1_CHANN_EN_0_ design_a9_1_axi_gpio_1_0_stub.v
|
||||
// Design : design_a9_1_axi_gpio_1_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_gpio,Vivado 2023.1" *)
|
||||
module design_a9_1_CHANN_EN_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [8:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [8:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
input [3:0]gpio_io_i;
|
||||
output [3:0]gpio_io_o;
|
||||
output [3:0]gpio_io_t;
|
||||
endmodule
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Oct 28 21:02:58 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top design_a9_1_CHANN_EN_0 -prefix
|
||||
-- design_a9_1_CHANN_EN_0_ design_a9_1_axi_gpio_1_0_stub.vhdl
|
||||
-- Design : design_a9_1_axi_gpio_1_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity design_a9_1_CHANN_EN_0 is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
|
||||
);
|
||||
|
||||
end design_a9_1_CHANN_EN_0;
|
||||
|
||||
architecture stub of design_a9_1_CHANN_EN_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
+209
@@ -0,0 +1,209 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 30
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_30;
|
||||
USE axi_gpio_v2_0_30.axi_gpio;
|
||||
|
||||
ENTITY design_a9_1_CHANN_EN_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
|
||||
);
|
||||
END design_a9_1_CHANN_EN_0;
|
||||
|
||||
ARCHITECTURE design_a9_1_CHANN_EN_0_arch OF design_a9_1_CHANN_EN_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_EN_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 4,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 0,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => gpio_io_i,
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio_io_t => gpio_io_t,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END design_a9_1_CHANN_EN_0_arch;
|
||||
+215
@@ -0,0 +1,215 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 30
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_30;
|
||||
USE axi_gpio_v2_0_30.axi_gpio;
|
||||
|
||||
ENTITY design_a9_1_CHANN_EN_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
|
||||
);
|
||||
END design_a9_1_CHANN_EN_0;
|
||||
|
||||
ARCHITECTURE design_a9_1_CHANN_EN_0_arch OF design_a9_1_CHANN_EN_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_EN_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_a9_1_CHANN_EN_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_a9_1_CHANN_EN_0_arch : ARCHITECTURE IS "design_a9_1_CHANN_EN_0,axi_gpio,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_a9_1_CHANN_EN_0_arch: ARCHITECTURE IS "design_a9_1_CHANN_EN_0,axi_gpio,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=30,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 4,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 0,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => gpio_io_i,
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio_io_t => gpio_io_t,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END design_a9_1_CHANN_EN_0_arch;
|
||||
BIN
Binary file not shown.
+48
@@ -0,0 +1,48 @@
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
||||
+2112
File diff suppressed because it is too large
Load Diff
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
|
||||
|
||||
create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
|
||||
|
||||
################################################################################
|
||||
+2665
File diff suppressed because it is too large
Load Diff
+2821
File diff suppressed because it is too large
Load Diff
+48
@@ -0,0 +1,48 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jun 24 16:22:50 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_stub.v
|
||||
// Design : design_a9_1_CHANN_EN_1
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_gpio,Vivado 2023.1" *)
|
||||
module design_a9_1_CHANN_EN_1(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i, gpio_io_o,
|
||||
gpio_io_t)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[0:0],gpio_io_o[0:0],gpio_io_t[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [8:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [8:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output ip2intc_irpt;
|
||||
input [0:0]gpio_io_i;
|
||||
output [0:0]gpio_io_o;
|
||||
output [0:0]gpio_io_t;
|
||||
endmodule
|
||||
+53
@@ -0,0 +1,53 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jun 24 16:22:50 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_stub.vhdl
|
||||
-- Design : design_a9_1_CHANN_EN_1
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity design_a9_1_CHANN_EN_1 is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
ip2intc_irpt : out STD_LOGIC;
|
||||
gpio_io_i : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
gpio_io_o : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
gpio_io_t : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end design_a9_1_CHANN_EN_1;
|
||||
|
||||
architecture stub of design_a9_1_CHANN_EN_1 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[0:0],gpio_io_o[0:0],gpio_io_t[0:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
+213
@@ -0,0 +1,213 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 30
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_30;
|
||||
USE axi_gpio_v2_0_30.axi_gpio;
|
||||
|
||||
ENTITY design_a9_1_CHANN_EN_1 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END design_a9_1_CHANN_EN_1;
|
||||
|
||||
ARCHITECTURE design_a9_1_CHANN_EN_1_arch OF design_a9_1_CHANN_EN_1 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_EN_1_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ip2intc_irpt: SIGNAL IS "XIL_INTERFACENAME IP2INTC_IRQ, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1," &
|
||||
" NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 1,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 0,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 1,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
ip2intc_irpt => ip2intc_irpt,
|
||||
gpio_io_i => gpio_io_i,
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio_io_t => gpio_io_t,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END design_a9_1_CHANN_EN_1_arch;
|
||||
+219
@@ -0,0 +1,219 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 30
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_30;
|
||||
USE axi_gpio_v2_0_30.axi_gpio;
|
||||
|
||||
ENTITY design_a9_1_CHANN_EN_1 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END design_a9_1_CHANN_EN_1;
|
||||
|
||||
ARCHITECTURE design_a9_1_CHANN_EN_1_arch OF design_a9_1_CHANN_EN_1 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_EN_1_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_a9_1_CHANN_EN_1_arch: ARCHITECTURE IS "axi_gpio,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_a9_1_CHANN_EN_1_arch : ARCHITECTURE IS "design_a9_1_CHANN_EN_1,axi_gpio,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_a9_1_CHANN_EN_1_arch: ARCHITECTURE IS "design_a9_1_CHANN_EN_1,axi_gpio,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=30,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=1,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ip2intc_irpt: SIGNAL IS "XIL_INTERFACENAME IP2INTC_IRQ, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1," &
|
||||
" NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 1,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 0,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 1,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
ip2intc_irpt => ip2intc_irpt,
|
||||
gpio_io_i => gpio_io_i,
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio_io_t => gpio_io_t,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END design_a9_1_CHANN_EN_1_arch;
|
||||
BIN
Binary file not shown.
+48
@@ -0,0 +1,48 @@
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
||||
+2109
File diff suppressed because it is too large
Load Diff
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
|
||||
|
||||
create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
|
||||
|
||||
################################################################################
|
||||
+2004
File diff suppressed because it is too large
Load Diff
+2236
File diff suppressed because it is too large
Load Diff
+46
@@ -0,0 +1,46 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jun 24 13:53:29 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_stub.v
|
||||
// Design : design_a9_1_CHANN_EN_2
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_gpio,Vivado 2023.1" *)
|
||||
module design_a9_1_CHANN_EN_2(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [8:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [8:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
input [3:0]gpio_io_i;
|
||||
output [3:0]gpio_io_o;
|
||||
output [3:0]gpio_io_t;
|
||||
endmodule
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jun 24 13:53:29 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_stub.vhdl
|
||||
-- Design : design_a9_1_CHANN_EN_2
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity design_a9_1_CHANN_EN_2 is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
|
||||
);
|
||||
|
||||
end design_a9_1_CHANN_EN_2;
|
||||
|
||||
architecture stub of design_a9_1_CHANN_EN_2 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
+209
@@ -0,0 +1,209 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 30
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_30;
|
||||
USE axi_gpio_v2_0_30.axi_gpio;
|
||||
|
||||
ENTITY design_a9_1_CHANN_EN_2 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
|
||||
);
|
||||
END design_a9_1_CHANN_EN_2;
|
||||
|
||||
ARCHITECTURE design_a9_1_CHANN_EN_2_arch OF design_a9_1_CHANN_EN_2 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_EN_2_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1," &
|
||||
" NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 4,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 0,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => gpio_io_i,
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio_io_t => gpio_io_t,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END design_a9_1_CHANN_EN_2_arch;
|
||||
+215
@@ -0,0 +1,215 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 30
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_30;
|
||||
USE axi_gpio_v2_0_30.axi_gpio;
|
||||
|
||||
ENTITY design_a9_1_CHANN_EN_2 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
|
||||
);
|
||||
END design_a9_1_CHANN_EN_2;
|
||||
|
||||
ARCHITECTURE design_a9_1_CHANN_EN_2_arch OF design_a9_1_CHANN_EN_2 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_EN_2_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_a9_1_CHANN_EN_2_arch: ARCHITECTURE IS "axi_gpio,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_a9_1_CHANN_EN_2_arch : ARCHITECTURE IS "design_a9_1_CHANN_EN_2,axi_gpio,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_a9_1_CHANN_EN_2_arch: ARCHITECTURE IS "design_a9_1_CHANN_EN_2,axi_gpio,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=30,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1," &
|
||||
" NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 4,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 0,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => gpio_io_i,
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio_io_t => gpio_io_t,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END design_a9_1_CHANN_EN_2_arch;
|
||||
BIN
Binary file not shown.
+48
@@ -0,0 +1,48 @@
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
||||
+2109
File diff suppressed because it is too large
Load Diff
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
|
||||
|
||||
create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
|
||||
|
||||
################################################################################
|
||||
+1690
File diff suppressed because it is too large
Load Diff
+1749
File diff suppressed because it is too large
Load Diff
+46
@@ -0,0 +1,46 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Oct 28 21:02:19 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top design_a9_1_CHANN_SEL_0 -prefix
|
||||
// design_a9_1_CHANN_SEL_0_ design_a9_1_CHANN_SEL_0_stub.v
|
||||
// Design : design_a9_1_CHANN_SEL_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_gpio,Vivado 2023.1" *)
|
||||
module design_a9_1_CHANN_SEL_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[0:0],gpio_io_o[0:0],gpio_io_t[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [8:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [8:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
input [0:0]gpio_io_i;
|
||||
output [0:0]gpio_io_o;
|
||||
output [0:0]gpio_io_t;
|
||||
endmodule
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Oct 28 21:02:19 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top design_a9_1_CHANN_SEL_0 -prefix
|
||||
-- design_a9_1_CHANN_SEL_0_ design_a9_1_CHANN_SEL_0_stub.vhdl
|
||||
-- Design : design_a9_1_CHANN_SEL_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity design_a9_1_CHANN_SEL_0 is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
gpio_io_i : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
gpio_io_o : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
gpio_io_t : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end design_a9_1_CHANN_SEL_0;
|
||||
|
||||
architecture stub of design_a9_1_CHANN_SEL_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[0:0],gpio_io_o[0:0],gpio_io_t[0:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
+209
@@ -0,0 +1,209 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 30
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_30;
|
||||
USE axi_gpio_v2_0_30.axi_gpio;
|
||||
|
||||
ENTITY design_a9_1_CHANN_SEL_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END design_a9_1_CHANN_SEL_0;
|
||||
|
||||
ARCHITECTURE design_a9_1_CHANN_SEL_0_arch OF design_a9_1_CHANN_SEL_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_SEL_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 1,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 0,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => gpio_io_i,
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio_io_t => gpio_io_t,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END design_a9_1_CHANN_SEL_0_arch;
|
||||
+215
@@ -0,0 +1,215 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 30
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_30;
|
||||
USE axi_gpio_v2_0_30.axi_gpio;
|
||||
|
||||
ENTITY design_a9_1_CHANN_SEL_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END design_a9_1_CHANN_SEL_0;
|
||||
|
||||
ARCHITECTURE design_a9_1_CHANN_SEL_0_arch OF design_a9_1_CHANN_SEL_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_CHANN_SEL_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_a9_1_CHANN_SEL_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_a9_1_CHANN_SEL_0_arch : ARCHITECTURE IS "design_a9_1_CHANN_SEL_0,axi_gpio,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_a9_1_CHANN_SEL_0_arch: ARCHITECTURE IS "design_a9_1_CHANN_SEL_0,axi_gpio,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=30,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=1,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 1,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 0,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => gpio_io_i,
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio_io_t => gpio_io_t,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END design_a9_1_CHANN_SEL_0_arch;
|
||||
BIN
Binary file not shown.
+99
@@ -0,0 +1,99 @@
|
||||
# file: design_a9_1_STIM_SPI_0.xdc
|
||||
# (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
## IOB constraints ######
|
||||
set_property IOB true [get_cells -hierarchical -filter {NAME =~*IO*_I_REG}]
|
||||
|
||||
#####################################################################################################
|
||||
# The following section list the board specific constraints (with/without STARTUPE2/E3 primitive) #
|
||||
# as per guidance given in product guide. #
|
||||
# User should uncomment, update constraints based on board delays and use #
|
||||
#####################################################################################################
|
||||
|
||||
#####################################################################################################
|
||||
# STARTUPE2 primitive is not used #
|
||||
#####################################################################################################
|
||||
#### All the delay numbers have to be provided by the user
|
||||
|
||||
#### CCLK max delay is 6.7 ns ; refer Data sheet
|
||||
#### We need to consider the max delay for worst case analysis
|
||||
##set cclk_delay 6.7
|
||||
|
||||
#### Following are the SPI device parameters
|
||||
#### Max Tco
|
||||
##set tco_max 7
|
||||
#### Min Tco
|
||||
##set tco_min 1
|
||||
#### Setup time requirement
|
||||
##set tsu 2
|
||||
#### Hold time requirement
|
||||
##set th 3
|
||||
|
||||
#### Following are the board/trace delay numbers
|
||||
#### Assumption is that all Data lines are matched
|
||||
##set tdata_trace_delay_max 0.25
|
||||
##set tdata_trace_delay_min 0.25
|
||||
##set tclk_trace_delay_max 0.2
|
||||
##set tclk_trace_delay_min 0.2
|
||||
|
||||
##### End of user provided delay numbers
|
||||
####create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_ports <SCK_IO>] -edges {3 5 7}
|
||||
##create_generated_clock -name clk_sck -source [get_pins -filter {REF_PIN_NAME==ext_spi_clk} -of [get_cells -hier -filter {REF_NAME=~axi_quad_spi_0}]] [get_ports SCK_IO] -edges {3 5 7}
|
||||
|
||||
#### Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCK falling edge
|
||||
#### Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk
|
||||
##set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports IO*_IO] -clock_fall;
|
||||
##set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports IO*_IO] -clock_fall;
|
||||
##set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
|
||||
##set_multicycle_path 1 -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
|
||||
|
||||
#### Data is captured into SPI on the following rising edge of SCK
|
||||
#### Data is driven by the IP on alternate rising_edge of the ext_spi_clk
|
||||
##set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_ports IO*_IO];
|
||||
##set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min - $th - $tclk_trace_delay_max] [get_ports IO*_IO];
|
||||
##set_multicycle_path 2 -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
|
||||
##set_multicycle_path 1 -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
|
||||
+8403
File diff suppressed because it is too large
Load Diff
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+59
@@ -0,0 +1,59 @@
|
||||
# file: design_a9_1_STIM_SPI_0.xdc
|
||||
# (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
|
||||
set clk_domain_axi_lite [get_clocks -of_objects [get_ports s_axi_aclk]]
|
||||
set clk_domain_ext_spi_clk [get_clocks -of_objects [get_ports ext_spi_clk]]
|
||||
# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
+86
@@ -0,0 +1,86 @@
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
|
||||
################################################################################
|
||||
#create_clock -name clock_name -period 10 [get_ports clock_name]
|
||||
################################################################################
|
||||
|
||||
#list of all the clock needed for AXI Quad SPI core
|
||||
|
||||
create_clock -name all_clock -period 20 [get_ports {s_axi_aclk ext_spi_clk}]
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
|
||||
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y1 [get_ports ext_spi_clk]
|
||||
|
||||
|
||||
set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/src_gray_ff_reg[*]] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/dest_graysync_ff_reg[0][*]] -filter {REF_PIN_NAME == D}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_reg[*]] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_reg[0][*]] -filter {REF_PIN_NAME == D}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/src_gray_ff_reg[*]] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/dest_graysync_ff_reg[0][*]] -filter {REF_PIN_NAME == D}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/*] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.*/*_CDC*] -filter {REF_PIN_NAME == D}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/SOFT_RESET_I/RESET_FLOPS[15].RST_FLOPS] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/RESET_SYNC_AX2S_1] -filter {REF_PIN_NAME == D}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg] -filter {REF_PIN_NAME ==C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/RESET_SYNC_AX2S_1] -filter {REF_PIN_NAME == D}]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
################################################################################
|
||||
+17058
File diff suppressed because it is too large
Load Diff
+20356
File diff suppressed because it is too large
Load Diff
+59
@@ -0,0 +1,59 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jun 24 13:54:04 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_stub.v
|
||||
// Design : design_a9_1_STIM_SPI_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_quad_spi,Vivado 2023.1" *)
|
||||
module design_a9_1_STIM_SPI_0(ext_spi_clk, s_axi_aclk, s_axi_aresetn,
|
||||
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
|
||||
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
|
||||
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, io0_i, io0_o, io0_t, io1_i,
|
||||
io1_o, io1_t, sck_i, sck_o, sck_t, ss_i, ss_o, ss_t, ip2intc_irpt)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt" */
|
||||
/* synthesis syn_force_seq_prim="ext_spi_clk" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input ext_spi_clk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [6:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [6:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
input io0_i;
|
||||
output io0_o;
|
||||
output io0_t;
|
||||
input io1_i;
|
||||
output io1_o;
|
||||
output io1_t;
|
||||
input sck_i;
|
||||
output sck_o;
|
||||
output sck_t;
|
||||
input [0:0]ss_i;
|
||||
output [0:0]ss_o;
|
||||
output ss_t;
|
||||
output ip2intc_irpt;
|
||||
endmodule
|
||||
+63
@@ -0,0 +1,63 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jun 24 13:54:04 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_stub.vhdl
|
||||
-- Design : design_a9_1_STIM_SPI_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity design_a9_1_STIM_SPI_0 is
|
||||
Port (
|
||||
ext_spi_clk : in STD_LOGIC;
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
io0_i : in STD_LOGIC;
|
||||
io0_o : out STD_LOGIC;
|
||||
io0_t : out STD_LOGIC;
|
||||
io1_i : in STD_LOGIC;
|
||||
io1_o : out STD_LOGIC;
|
||||
io1_t : out STD_LOGIC;
|
||||
sck_i : in STD_LOGIC;
|
||||
sck_o : out STD_LOGIC;
|
||||
sck_t : out STD_LOGIC;
|
||||
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ss_t : out STD_LOGIC;
|
||||
ip2intc_irpt : out STD_LOGIC
|
||||
);
|
||||
|
||||
end design_a9_1_STIM_SPI_0;
|
||||
|
||||
architecture stub of design_a9_1_STIM_SPI_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_quad_spi,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
+256
@@ -0,0 +1,256 @@
|
||||
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|
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|
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|
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|
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|
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||||
001
|
||||
001
|
||||
001
|
||||
008
|
||||
001
|
||||
000
|
||||
008
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
008
|
||||
001
|
||||
001
|
||||
001
|
||||
018
|
||||
001
|
||||
001
|
||||
001
|
||||
118
|
||||
918
|
||||
118
|
||||
818
|
||||
000
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
000
|
||||
001
|
||||
5C8
|
||||
5D8
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
000
|
||||
001
|
||||
001
|
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001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
+256
@@ -0,0 +1,256 @@
|
||||
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|
||||
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|
||||
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|
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|
||||
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||||
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|
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|
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|
||||
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||||
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|
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|
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|
||||
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|
||||
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|
||||
000000000001
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
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|
||||
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|
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|
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|
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|
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|
||||
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|
||||
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||||
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|
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|
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
000000000001
|
||||
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|
||||
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|
||||
001100101000
|
||||
001100111000
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000001000
|
||||
000000000000
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000001000
|
||||
000000000001
|
||||
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|
||||
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|
||||
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|
||||
000000000001
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
000000000001
|
||||
000000000001
|
||||
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|
||||
000000001000
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000011000
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000100011000
|
||||
100100011000
|
||||
000100011000
|
||||
100000011000
|
||||
000000000000
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000000
|
||||
000000000001
|
||||
010111001000
|
||||
010111011000
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000000
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
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|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
+393
@@ -0,0 +1,393 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
|
||||
-- IP Revision: 27
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_quad_spi_v3_2_27;
|
||||
USE axi_quad_spi_v3_2_27.axi_quad_spi;
|
||||
|
||||
ENTITY design_a9_1_STIM_SPI_0 IS
|
||||
PORT (
|
||||
ext_spi_clk : IN STD_LOGIC;
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
io0_i : IN STD_LOGIC;
|
||||
io0_o : OUT STD_LOGIC;
|
||||
io0_t : OUT STD_LOGIC;
|
||||
io1_i : IN STD_LOGIC;
|
||||
io1_o : OUT STD_LOGIC;
|
||||
io1_t : OUT STD_LOGIC;
|
||||
sck_i : IN STD_LOGIC;
|
||||
sck_o : OUT STD_LOGIC;
|
||||
sck_t : OUT STD_LOGIC;
|
||||
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ss_t : OUT STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC
|
||||
);
|
||||
END design_a9_1_STIM_SPI_0;
|
||||
|
||||
ARCHITECTURE design_a9_1_STIM_SPI_0_arch OF design_a9_1_STIM_SPI_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_STIM_SPI_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_quad_spi IS
|
||||
GENERIC (
|
||||
Async_Clk : INTEGER;
|
||||
C_FAMILY : STRING;
|
||||
C_SELECT_XPM : INTEGER;
|
||||
C_SUB_FAMILY : STRING;
|
||||
C_INSTANCE : STRING;
|
||||
C_SPI_MEM_ADDR_BITS : INTEGER;
|
||||
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
|
||||
C_XIP_MODE : INTEGER;
|
||||
C_XIP_PERF_MODE : INTEGER;
|
||||
C_BYTE_LEVEL_INTERRUPT_EN : INTEGER;
|
||||
C_UC_FAMILY : INTEGER;
|
||||
C_FIFO_DEPTH : INTEGER;
|
||||
C_SCK_RATIO : INTEGER;
|
||||
C_DUAL_QUAD_MODE : INTEGER;
|
||||
C_NUM_SS_BITS : INTEGER;
|
||||
C_NUM_TRANSFER_BITS : INTEGER;
|
||||
C_NEW_SEQ_EN : INTEGER;
|
||||
C_SPI_MODE : INTEGER;
|
||||
C_USE_STARTUP : INTEGER;
|
||||
C_USE_STARTUP_EXT : INTEGER;
|
||||
C_SPI_MEMORY : INTEGER;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_S_AXI4_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI4_DATA_WIDTH : INTEGER;
|
||||
C_S_AXI4_ID_WIDTH : INTEGER;
|
||||
C_SHARED_STARTUP : INTEGER;
|
||||
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
|
||||
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
|
||||
C_LSB_STUP : INTEGER
|
||||
);
|
||||
PORT (
|
||||
ext_spi_clk : IN STD_LOGIC;
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi4_aclk : IN STD_LOGIC;
|
||||
s_axi4_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
s_axi4_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi4_awlock : IN STD_LOGIC;
|
||||
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi4_awvalid : IN STD_LOGIC;
|
||||
s_axi4_awready : OUT STD_LOGIC;
|
||||
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_wlast : IN STD_LOGIC;
|
||||
s_axi4_wvalid : IN STD_LOGIC;
|
||||
s_axi4_wready : OUT STD_LOGIC;
|
||||
s_axi4_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi4_bvalid : OUT STD_LOGIC;
|
||||
s_axi4_bready : IN STD_LOGIC;
|
||||
s_axi4_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi4_arlock : IN STD_LOGIC;
|
||||
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi4_arvalid : IN STD_LOGIC;
|
||||
s_axi4_arready : OUT STD_LOGIC;
|
||||
s_axi4_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi4_rlast : OUT STD_LOGIC;
|
||||
s_axi4_rvalid : OUT STD_LOGIC;
|
||||
s_axi4_rready : IN STD_LOGIC;
|
||||
io0_i : IN STD_LOGIC;
|
||||
io0_o : OUT STD_LOGIC;
|
||||
io0_t : OUT STD_LOGIC;
|
||||
io1_i : IN STD_LOGIC;
|
||||
io1_o : OUT STD_LOGIC;
|
||||
io1_t : OUT STD_LOGIC;
|
||||
io2_i : IN STD_LOGIC;
|
||||
io2_o : OUT STD_LOGIC;
|
||||
io2_t : OUT STD_LOGIC;
|
||||
io3_i : IN STD_LOGIC;
|
||||
io3_o : OUT STD_LOGIC;
|
||||
io3_t : OUT STD_LOGIC;
|
||||
io0_1_i : IN STD_LOGIC;
|
||||
io0_1_o : OUT STD_LOGIC;
|
||||
io0_1_t : OUT STD_LOGIC;
|
||||
io1_1_i : IN STD_LOGIC;
|
||||
io1_1_o : OUT STD_LOGIC;
|
||||
io1_1_t : OUT STD_LOGIC;
|
||||
io2_1_i : IN STD_LOGIC;
|
||||
io2_1_o : OUT STD_LOGIC;
|
||||
io2_1_t : OUT STD_LOGIC;
|
||||
io3_1_i : IN STD_LOGIC;
|
||||
io3_1_o : OUT STD_LOGIC;
|
||||
io3_1_t : OUT STD_LOGIC;
|
||||
spisel : IN STD_LOGIC;
|
||||
sck_i : IN STD_LOGIC;
|
||||
sck_o : OUT STD_LOGIC;
|
||||
sck_t : OUT STD_LOGIC;
|
||||
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ss_t : OUT STD_LOGIC;
|
||||
ss_1_i : IN STD_LOGIC;
|
||||
ss_1_o : OUT STD_LOGIC;
|
||||
ss_1_t : OUT STD_LOGIC;
|
||||
cfgclk : OUT STD_LOGIC;
|
||||
cfgmclk : OUT STD_LOGIC;
|
||||
eos : OUT STD_LOGIC;
|
||||
preq : OUT STD_LOGIC;
|
||||
clk : IN STD_LOGIC;
|
||||
gsr : IN STD_LOGIC;
|
||||
gts : IN STD_LOGIC;
|
||||
keyclearb : IN STD_LOGIC;
|
||||
usrcclkts : IN STD_LOGIC;
|
||||
usrdoneo : IN STD_LOGIC;
|
||||
usrdonets : IN STD_LOGIC;
|
||||
pack : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT axi_quad_spi;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_spi_clk: SIGNAL IS "XIL_INTERFACENAME spi_clk, ASSOCIATED_BUSIF SPI_0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF io0_i: SIGNAL IS "XIL_INTERFACENAME SPI_0, BOARD.ASSOCIATED_PARAM QSPI_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ip2intc_irpt: SIGNAL IS "XIL_INTERFACENAME interrupt, SENSITIVITY EDGE_RISING, PORTWIDTH 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME lite_clk, ASSOCIATED_BUSIF AXI_LITE, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME lite_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 7, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" &
|
||||
" 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
|
||||
BEGIN
|
||||
U0 : axi_quad_spi
|
||||
GENERIC MAP (
|
||||
Async_Clk => 0,
|
||||
C_FAMILY => "zynq",
|
||||
C_SELECT_XPM => 0,
|
||||
C_SUB_FAMILY => "zynq",
|
||||
C_INSTANCE => "axi_quad_spi_inst",
|
||||
C_SPI_MEM_ADDR_BITS => 24,
|
||||
C_TYPE_OF_AXI4_INTERFACE => 0,
|
||||
C_XIP_MODE => 0,
|
||||
C_XIP_PERF_MODE => 1,
|
||||
C_BYTE_LEVEL_INTERRUPT_EN => 0,
|
||||
C_UC_FAMILY => 0,
|
||||
C_FIFO_DEPTH => 16,
|
||||
C_SCK_RATIO => 16,
|
||||
C_DUAL_QUAD_MODE => 0,
|
||||
C_NUM_SS_BITS => 1,
|
||||
C_NUM_TRANSFER_BITS => 8,
|
||||
C_NEW_SEQ_EN => 1,
|
||||
C_SPI_MODE => 0,
|
||||
C_USE_STARTUP => 0,
|
||||
C_USE_STARTUP_EXT => 0,
|
||||
C_SPI_MEMORY => 1,
|
||||
C_S_AXI_ADDR_WIDTH => 7,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_S_AXI4_ADDR_WIDTH => 24,
|
||||
C_S_AXI4_DATA_WIDTH => 32,
|
||||
C_S_AXI4_ID_WIDTH => 4,
|
||||
C_SHARED_STARTUP => 0,
|
||||
C_S_AXI4_BASEADDR => X"FFFFFFFF",
|
||||
C_S_AXI4_HIGHADDR => X"00000000",
|
||||
C_LSB_STUP => 0
|
||||
)
|
||||
PORT MAP (
|
||||
ext_spi_clk => ext_spi_clk,
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi4_aclk => '0',
|
||||
s_axi4_aresetn => '0',
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
|
||||
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi4_awlock => '0',
|
||||
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi4_awvalid => '0',
|
||||
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_wlast => '0',
|
||||
s_axi4_wvalid => '0',
|
||||
s_axi4_bready => '0',
|
||||
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
|
||||
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi4_arlock => '0',
|
||||
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi4_arvalid => '0',
|
||||
s_axi4_rready => '0',
|
||||
io0_i => io0_i,
|
||||
io0_o => io0_o,
|
||||
io0_t => io0_t,
|
||||
io1_i => io1_i,
|
||||
io1_o => io1_o,
|
||||
io1_t => io1_t,
|
||||
io2_i => '0',
|
||||
io3_i => '0',
|
||||
io0_1_i => '0',
|
||||
io1_1_i => '0',
|
||||
io2_1_i => '0',
|
||||
io3_1_i => '0',
|
||||
spisel => '1',
|
||||
sck_i => sck_i,
|
||||
sck_o => sck_o,
|
||||
sck_t => sck_t,
|
||||
ss_i => ss_i,
|
||||
ss_o => ss_o,
|
||||
ss_t => ss_t,
|
||||
ss_1_i => '0',
|
||||
clk => '0',
|
||||
gsr => '0',
|
||||
gts => '0',
|
||||
keyclearb => '0',
|
||||
usrcclkts => '0',
|
||||
usrdoneo => '1',
|
||||
usrdonets => '0',
|
||||
pack => '0',
|
||||
ip2intc_irpt => ip2intc_irpt
|
||||
);
|
||||
END design_a9_1_STIM_SPI_0_arch;
|
||||
+400
@@ -0,0 +1,400 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
|
||||
-- IP Revision: 27
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_quad_spi_v3_2_27;
|
||||
USE axi_quad_spi_v3_2_27.axi_quad_spi;
|
||||
|
||||
ENTITY design_a9_1_STIM_SPI_0 IS
|
||||
PORT (
|
||||
ext_spi_clk : IN STD_LOGIC;
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
io0_i : IN STD_LOGIC;
|
||||
io0_o : OUT STD_LOGIC;
|
||||
io0_t : OUT STD_LOGIC;
|
||||
io1_i : IN STD_LOGIC;
|
||||
io1_o : OUT STD_LOGIC;
|
||||
io1_t : OUT STD_LOGIC;
|
||||
sck_i : IN STD_LOGIC;
|
||||
sck_o : OUT STD_LOGIC;
|
||||
sck_t : OUT STD_LOGIC;
|
||||
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ss_t : OUT STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC
|
||||
);
|
||||
END design_a9_1_STIM_SPI_0;
|
||||
|
||||
ARCHITECTURE design_a9_1_STIM_SPI_0_arch OF design_a9_1_STIM_SPI_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_a9_1_STIM_SPI_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_quad_spi IS
|
||||
GENERIC (
|
||||
Async_Clk : INTEGER;
|
||||
C_FAMILY : STRING;
|
||||
C_SELECT_XPM : INTEGER;
|
||||
C_SUB_FAMILY : STRING;
|
||||
C_INSTANCE : STRING;
|
||||
C_SPI_MEM_ADDR_BITS : INTEGER;
|
||||
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
|
||||
C_XIP_MODE : INTEGER;
|
||||
C_XIP_PERF_MODE : INTEGER;
|
||||
C_BYTE_LEVEL_INTERRUPT_EN : INTEGER;
|
||||
C_UC_FAMILY : INTEGER;
|
||||
C_FIFO_DEPTH : INTEGER;
|
||||
C_SCK_RATIO : INTEGER;
|
||||
C_DUAL_QUAD_MODE : INTEGER;
|
||||
C_NUM_SS_BITS : INTEGER;
|
||||
C_NUM_TRANSFER_BITS : INTEGER;
|
||||
C_NEW_SEQ_EN : INTEGER;
|
||||
C_SPI_MODE : INTEGER;
|
||||
C_USE_STARTUP : INTEGER;
|
||||
C_USE_STARTUP_EXT : INTEGER;
|
||||
C_SPI_MEMORY : INTEGER;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_S_AXI4_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI4_DATA_WIDTH : INTEGER;
|
||||
C_S_AXI4_ID_WIDTH : INTEGER;
|
||||
C_SHARED_STARTUP : INTEGER;
|
||||
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
|
||||
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
|
||||
C_LSB_STUP : INTEGER
|
||||
);
|
||||
PORT (
|
||||
ext_spi_clk : IN STD_LOGIC;
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi4_aclk : IN STD_LOGIC;
|
||||
s_axi4_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
s_axi4_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi4_awlock : IN STD_LOGIC;
|
||||
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi4_awvalid : IN STD_LOGIC;
|
||||
s_axi4_awready : OUT STD_LOGIC;
|
||||
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_wlast : IN STD_LOGIC;
|
||||
s_axi4_wvalid : IN STD_LOGIC;
|
||||
s_axi4_wready : OUT STD_LOGIC;
|
||||
s_axi4_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi4_bvalid : OUT STD_LOGIC;
|
||||
s_axi4_bready : IN STD_LOGIC;
|
||||
s_axi4_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi4_arlock : IN STD_LOGIC;
|
||||
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi4_arvalid : IN STD_LOGIC;
|
||||
s_axi4_arready : OUT STD_LOGIC;
|
||||
s_axi4_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi4_rlast : OUT STD_LOGIC;
|
||||
s_axi4_rvalid : OUT STD_LOGIC;
|
||||
s_axi4_rready : IN STD_LOGIC;
|
||||
io0_i : IN STD_LOGIC;
|
||||
io0_o : OUT STD_LOGIC;
|
||||
io0_t : OUT STD_LOGIC;
|
||||
io1_i : IN STD_LOGIC;
|
||||
io1_o : OUT STD_LOGIC;
|
||||
io1_t : OUT STD_LOGIC;
|
||||
io2_i : IN STD_LOGIC;
|
||||
io2_o : OUT STD_LOGIC;
|
||||
io2_t : OUT STD_LOGIC;
|
||||
io3_i : IN STD_LOGIC;
|
||||
io3_o : OUT STD_LOGIC;
|
||||
io3_t : OUT STD_LOGIC;
|
||||
io0_1_i : IN STD_LOGIC;
|
||||
io0_1_o : OUT STD_LOGIC;
|
||||
io0_1_t : OUT STD_LOGIC;
|
||||
io1_1_i : IN STD_LOGIC;
|
||||
io1_1_o : OUT STD_LOGIC;
|
||||
io1_1_t : OUT STD_LOGIC;
|
||||
io2_1_i : IN STD_LOGIC;
|
||||
io2_1_o : OUT STD_LOGIC;
|
||||
io2_1_t : OUT STD_LOGIC;
|
||||
io3_1_i : IN STD_LOGIC;
|
||||
io3_1_o : OUT STD_LOGIC;
|
||||
io3_1_t : OUT STD_LOGIC;
|
||||
spisel : IN STD_LOGIC;
|
||||
sck_i : IN STD_LOGIC;
|
||||
sck_o : OUT STD_LOGIC;
|
||||
sck_t : OUT STD_LOGIC;
|
||||
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ss_t : OUT STD_LOGIC;
|
||||
ss_1_i : IN STD_LOGIC;
|
||||
ss_1_o : OUT STD_LOGIC;
|
||||
ss_1_t : OUT STD_LOGIC;
|
||||
cfgclk : OUT STD_LOGIC;
|
||||
cfgmclk : OUT STD_LOGIC;
|
||||
eos : OUT STD_LOGIC;
|
||||
preq : OUT STD_LOGIC;
|
||||
clk : IN STD_LOGIC;
|
||||
gsr : IN STD_LOGIC;
|
||||
gts : IN STD_LOGIC;
|
||||
keyclearb : IN STD_LOGIC;
|
||||
usrcclkts : IN STD_LOGIC;
|
||||
usrdoneo : IN STD_LOGIC;
|
||||
usrdonets : IN STD_LOGIC;
|
||||
pack : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT axi_quad_spi;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_a9_1_STIM_SPI_0_arch: ARCHITECTURE IS "axi_quad_spi,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_a9_1_STIM_SPI_0_arch : ARCHITECTURE IS "design_a9_1_STIM_SPI_0,axi_quad_spi,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_a9_1_STIM_SPI_0_arch: ARCHITECTURE IS "design_a9_1_STIM_SPI_0,axi_quad_spi,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_quad_spi,x_ipVersion=3.2,x_ipCoreRevision=27,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,Async_Clk=0,C_FAMILY=zynq,C_SELECT_XPM=0,C_SUB_FAMILY=zynq,C_INSTANCE=axi_quad_spi_inst,C_SPI_MEM_ADDR_BITS=24,C_TYPE_OF_AXI4_INTERFACE=0,C_XIP_MODE=0,C_XIP_PERF_MODE=1,C_BYTE_LEVEL_INTERRUPT_EN=0,C_UC_FAMILY=0,C_FIFO_DEPTH=16,C_SCK_RATIO=16,C_DUAL_QUAD_MODE=0,C_NUM_SS_BITS=1,C_NUM_TRANSFER_BITS=8," &
|
||||
"C_NEW_SEQ_EN=1,C_SPI_MODE=0,C_USE_STARTUP=0,C_USE_STARTUP_EXT=0,C_SPI_MEMORY=1,C_S_AXI_ADDR_WIDTH=7,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_ADDR_WIDTH=24,C_S_AXI4_DATA_WIDTH=32,C_S_AXI4_ID_WIDTH=4,C_SHARED_STARTUP=0,C_S_AXI4_BASEADDR=0xFFFFFFFF,C_S_AXI4_HIGHADDR=0x00000000,C_LSB_STUP=0}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_spi_clk: SIGNAL IS "XIL_INTERFACENAME spi_clk, ASSOCIATED_BUSIF SPI_0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF io0_i: SIGNAL IS "XIL_INTERFACENAME SPI_0, BOARD.ASSOCIATED_PARAM QSPI_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ip2intc_irpt: SIGNAL IS "XIL_INTERFACENAME interrupt, SENSITIVITY EDGE_RISING, PORTWIDTH 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME lite_clk, ASSOCIATED_BUSIF AXI_LITE, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME lite_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 7, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" &
|
||||
" 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
|
||||
BEGIN
|
||||
U0 : axi_quad_spi
|
||||
GENERIC MAP (
|
||||
Async_Clk => 0,
|
||||
C_FAMILY => "zynq",
|
||||
C_SELECT_XPM => 0,
|
||||
C_SUB_FAMILY => "zynq",
|
||||
C_INSTANCE => "axi_quad_spi_inst",
|
||||
C_SPI_MEM_ADDR_BITS => 24,
|
||||
C_TYPE_OF_AXI4_INTERFACE => 0,
|
||||
C_XIP_MODE => 0,
|
||||
C_XIP_PERF_MODE => 1,
|
||||
C_BYTE_LEVEL_INTERRUPT_EN => 0,
|
||||
C_UC_FAMILY => 0,
|
||||
C_FIFO_DEPTH => 16,
|
||||
C_SCK_RATIO => 16,
|
||||
C_DUAL_QUAD_MODE => 0,
|
||||
C_NUM_SS_BITS => 1,
|
||||
C_NUM_TRANSFER_BITS => 8,
|
||||
C_NEW_SEQ_EN => 1,
|
||||
C_SPI_MODE => 0,
|
||||
C_USE_STARTUP => 0,
|
||||
C_USE_STARTUP_EXT => 0,
|
||||
C_SPI_MEMORY => 1,
|
||||
C_S_AXI_ADDR_WIDTH => 7,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_S_AXI4_ADDR_WIDTH => 24,
|
||||
C_S_AXI4_DATA_WIDTH => 32,
|
||||
C_S_AXI4_ID_WIDTH => 4,
|
||||
C_SHARED_STARTUP => 0,
|
||||
C_S_AXI4_BASEADDR => X"FFFFFFFF",
|
||||
C_S_AXI4_HIGHADDR => X"00000000",
|
||||
C_LSB_STUP => 0
|
||||
)
|
||||
PORT MAP (
|
||||
ext_spi_clk => ext_spi_clk,
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi4_aclk => '0',
|
||||
s_axi4_aresetn => '0',
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
|
||||
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi4_awlock => '0',
|
||||
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi4_awvalid => '0',
|
||||
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_wlast => '0',
|
||||
s_axi4_wvalid => '0',
|
||||
s_axi4_bready => '0',
|
||||
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
|
||||
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi4_arlock => '0',
|
||||
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi4_arvalid => '0',
|
||||
s_axi4_rready => '0',
|
||||
io0_i => io0_i,
|
||||
io0_o => io0_o,
|
||||
io0_t => io0_t,
|
||||
io1_i => io1_i,
|
||||
io1_o => io1_o,
|
||||
io1_t => io1_t,
|
||||
io2_i => '0',
|
||||
io3_i => '0',
|
||||
io0_1_i => '0',
|
||||
io1_1_i => '0',
|
||||
io2_1_i => '0',
|
||||
io3_1_i => '0',
|
||||
spisel => '1',
|
||||
sck_i => sck_i,
|
||||
sck_o => sck_o,
|
||||
sck_t => sck_t,
|
||||
ss_i => ss_i,
|
||||
ss_o => ss_o,
|
||||
ss_t => ss_t,
|
||||
ss_1_i => '0',
|
||||
clk => '0',
|
||||
gsr => '0',
|
||||
gts => '0',
|
||||
keyclearb => '0',
|
||||
usrcclkts => '0',
|
||||
usrdoneo => '1',
|
||||
usrdonets => '0',
|
||||
pack => '0',
|
||||
ip2intc_irpt => ip2intc_irpt
|
||||
);
|
||||
END design_a9_1_STIM_SPI_0_arch;
|
||||
BIN
Binary file not shown.
+99
@@ -0,0 +1,99 @@
|
||||
# file: design_a9_1_ZCHECK_SPI_0.xdc
|
||||
# (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
## IOB constraints ######
|
||||
set_property IOB true [get_cells -hierarchical -filter {NAME =~*IO*_I_REG}]
|
||||
|
||||
#####################################################################################################
|
||||
# The following section list the board specific constraints (with/without STARTUPE2/E3 primitive) #
|
||||
# as per guidance given in product guide. #
|
||||
# User should uncomment, update constraints based on board delays and use #
|
||||
#####################################################################################################
|
||||
|
||||
#####################################################################################################
|
||||
# STARTUPE2 primitive is not used #
|
||||
#####################################################################################################
|
||||
#### All the delay numbers have to be provided by the user
|
||||
|
||||
#### CCLK max delay is 6.7 ns ; refer Data sheet
|
||||
#### We need to consider the max delay for worst case analysis
|
||||
##set cclk_delay 6.7
|
||||
|
||||
#### Following are the SPI device parameters
|
||||
#### Max Tco
|
||||
##set tco_max 7
|
||||
#### Min Tco
|
||||
##set tco_min 1
|
||||
#### Setup time requirement
|
||||
##set tsu 2
|
||||
#### Hold time requirement
|
||||
##set th 3
|
||||
|
||||
#### Following are the board/trace delay numbers
|
||||
#### Assumption is that all Data lines are matched
|
||||
##set tdata_trace_delay_max 0.25
|
||||
##set tdata_trace_delay_min 0.25
|
||||
##set tclk_trace_delay_max 0.2
|
||||
##set tclk_trace_delay_min 0.2
|
||||
|
||||
##### End of user provided delay numbers
|
||||
####create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_ports <SCK_IO>] -edges {3 5 7}
|
||||
##create_generated_clock -name clk_sck -source [get_pins -filter {REF_PIN_NAME==ext_spi_clk} -of [get_cells -hier -filter {REF_NAME=~axi_quad_spi_0}]] [get_ports SCK_IO] -edges {3 5 7}
|
||||
|
||||
#### Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCK falling edge
|
||||
#### Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk
|
||||
##set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports IO*_IO] -clock_fall;
|
||||
##set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports IO*_IO] -clock_fall;
|
||||
##set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
|
||||
##set_multicycle_path 1 -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
|
||||
|
||||
#### Data is captured into SPI on the following rising edge of SCK
|
||||
#### Data is driven by the IP on alternate rising_edge of the ext_spi_clk
|
||||
##set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_ports IO*_IO];
|
||||
##set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min - $th - $tclk_trace_delay_max] [get_ports IO*_IO];
|
||||
##set_multicycle_path 2 -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
|
||||
##set_multicycle_path 1 -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
|
||||
+8403
File diff suppressed because it is too large
Load Diff
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+59
@@ -0,0 +1,59 @@
|
||||
# file: design_a9_1_ZCHECK_SPI_0.xdc
|
||||
# (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
|
||||
set clk_domain_axi_lite [get_clocks -of_objects [get_ports s_axi_aclk]]
|
||||
set clk_domain_ext_spi_clk [get_clocks -of_objects [get_ports ext_spi_clk]]
|
||||
# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
+86
@@ -0,0 +1,86 @@
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
|
||||
################################################################################
|
||||
#create_clock -name clock_name -period 10 [get_ports clock_name]
|
||||
################################################################################
|
||||
|
||||
#list of all the clock needed for AXI Quad SPI core
|
||||
|
||||
create_clock -name all_clock -period 20 [get_ports {s_axi_aclk ext_spi_clk}]
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
|
||||
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y1 [get_ports ext_spi_clk]
|
||||
|
||||
|
||||
set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/src_gray_ff_reg[*]] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/dest_graysync_ff_reg[0][*]] -filter {REF_PIN_NAME == D}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_reg[*]] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_reg[0][*]] -filter {REF_PIN_NAME == D}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/src_gray_ff_reg[*]] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.*_pntr_cdc_*inst/dest_graysync_ff_reg[0][*]] -filter {REF_PIN_NAME == D}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/*] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.*/*_CDC*] -filter {REF_PIN_NAME == D}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/SOFT_RESET_I/RESET_FLOPS[15].RST_FLOPS] -filter {REF_PIN_NAME == C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/RESET_SYNC_AX2S_1] -filter {REF_PIN_NAME == D}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg] -filter {REF_PIN_NAME ==C}] -to [get_pins -of [get_cells -hier -filter name=~*U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/RESET_SYNC_AX2S_1] -filter {REF_PIN_NAME == D}]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
################################################################################
|
||||
+17036
File diff suppressed because it is too large
Load Diff
+20304
File diff suppressed because it is too large
Load Diff
+59
@@ -0,0 +1,59 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jun 24 13:54:03 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top design_a9_1_ZCHECK_SPI_0 -prefix
|
||||
// design_a9_1_ZCHECK_SPI_0_ design_a9_1_STIM_SPI_0_stub.v
|
||||
// Design : design_a9_1_STIM_SPI_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_quad_spi,Vivado 2023.1" *)
|
||||
module design_a9_1_ZCHECK_SPI_0(ext_spi_clk, s_axi_aclk, s_axi_aresetn,
|
||||
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
|
||||
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
|
||||
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, io0_i, io0_o, io0_t, io1_i,
|
||||
io1_o, io1_t, sck_i, sck_o, sck_t, ss_i, ss_o, ss_t, ip2intc_irpt)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt" */
|
||||
/* synthesis syn_force_seq_prim="ext_spi_clk" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input ext_spi_clk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [6:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [6:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
input io0_i;
|
||||
output io0_o;
|
||||
output io0_t;
|
||||
input io1_i;
|
||||
output io1_o;
|
||||
output io1_t;
|
||||
input sck_i;
|
||||
output sck_o;
|
||||
output sck_t;
|
||||
input [0:0]ss_i;
|
||||
output [0:0]ss_o;
|
||||
output ss_t;
|
||||
output ip2intc_irpt;
|
||||
endmodule
|
||||
+63
@@ -0,0 +1,63 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jun 24 13:54:03 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top design_a9_1_ZCHECK_SPI_0 -prefix
|
||||
-- design_a9_1_ZCHECK_SPI_0_ design_a9_1_STIM_SPI_0_stub.vhdl
|
||||
-- Design : design_a9_1_STIM_SPI_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity design_a9_1_ZCHECK_SPI_0 is
|
||||
Port (
|
||||
ext_spi_clk : in STD_LOGIC;
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
io0_i : in STD_LOGIC;
|
||||
io0_o : out STD_LOGIC;
|
||||
io0_t : out STD_LOGIC;
|
||||
io1_i : in STD_LOGIC;
|
||||
io1_o : out STD_LOGIC;
|
||||
io1_t : out STD_LOGIC;
|
||||
sck_i : in STD_LOGIC;
|
||||
sck_o : out STD_LOGIC;
|
||||
sck_t : out STD_LOGIC;
|
||||
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ss_t : out STD_LOGIC;
|
||||
ip2intc_irpt : out STD_LOGIC
|
||||
);
|
||||
|
||||
end design_a9_1_ZCHECK_SPI_0;
|
||||
|
||||
architecture stub of design_a9_1_ZCHECK_SPI_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_quad_spi,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
+256
@@ -0,0 +1,256 @@
|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
+256
@@ -0,0 +1,256 @@
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
+256
@@ -0,0 +1,256 @@
|
||||
001
|
||||
008
|
||||
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|
||||
008
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
001
|
||||
001
|
||||
098
|
||||
498
|
||||
498
|
||||
001
|
||||
008
|
||||
408
|
||||
008
|
||||
001
|
||||
408
|
||||
000
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
008
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
188
|
||||
198
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
000
|
||||
001
|
||||
008
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
008
|
||||
001
|
||||
018
|
||||
001
|
||||
001
|
||||
001
|
||||
000
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
000
|
||||
001
|
||||
008
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
008
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
000
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
008
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
000
|
||||
000
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
008
|
||||
008
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
000
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
000
|
||||
008
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
000
|
||||
001
|
||||
000
|
||||
001
|
||||
1A8
|
||||
1B8
|
||||
001
|
||||
001
|
||||
001
|
||||
008
|
||||
000
|
||||
001
|
||||
001
|
||||
001
|
||||
008
|
||||
001
|
||||
000
|
||||
008
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
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||||
001
|
||||
001
|
||||
001
|
||||
008
|
||||
001
|
||||
001
|
||||
001
|
||||
018
|
||||
001
|
||||
001
|
||||
001
|
||||
098
|
||||
498
|
||||
098
|
||||
418
|
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000
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
000
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
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||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
+256
@@ -0,0 +1,256 @@
|
||||
00000000000
|
||||
00000001000
|
||||
10010001000
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||||
00000001000
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00000000000
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00000001000
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00000001000
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00000001000
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00000000001
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00000000001
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00000000001
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10010011000
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00000001000
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00000000001
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00000001000
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00000001000
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00000001000
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00000000000
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00000000001
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00000001000
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00000000001
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00000000001
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00010011000
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10010011000
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10010011000
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00000000001
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00000001000
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10000001000
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00000001000
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00000000001
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10000001000
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00000000000
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00000000001
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00000000001
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00000001000
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00110001000
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00110011000
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00000001000
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00000001000
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00000001000
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00110101000
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00110111000
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00000001000
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00000001000
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00000001000
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00000000001
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00000000001
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00000011000
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00000000001
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00000000001
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00010011000
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10010011000
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00010011000
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10000011000
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00000000000
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00000000001
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00000000001
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00000000000
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00000000001
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00000000001
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00000000001
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00000000001
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|
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00000000001
|
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00000000001
|
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00000000001
|
||||
00000000001
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user