sync chunk 9/12
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@@ -0,0 +1,89 @@
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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// Date : Wed Jun 24 16:42:05 2026
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// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
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// Design : u_ila_0
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z020clg400-2
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* X_CORE_INFO = "ila,Vivado 2023.1" *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
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probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
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probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
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probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
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probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
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probe51, probe52, probe53, probe54, probe55, probe56, probe57, probe58, probe59, probe60, probe61)
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/* synthesis syn_black_box black_box_pad_pin="probe0[31:0],probe1[31:0],probe2[1:0],probe3[7:0],probe4[7:0],probe5[15:0],probe6[15:0],probe7[7:0],probe8[0:0],probe9[7:0],probe10[15:0],probe11[1:0],probe12[7:0],probe13[7:0],probe14[15:0],probe15[15:0],probe16[8:0],probe17[15:0],probe18[8:0],probe19[7:0],probe20[15:0],probe21[15:0],probe22[7:0],probe23[7:0],probe24[7:0],probe25[12:0],probe26[31:0],probe27[3:0],probe28[31:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0]" */
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/* synthesis syn_force_seq_prim="clk" */;
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input clk /* synthesis syn_isclock = 1 */;
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input [31:0]probe0;
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input [31:0]probe1;
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input [1:0]probe2;
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input [7:0]probe3;
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input [7:0]probe4;
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input [15:0]probe5;
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input [15:0]probe6;
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input [7:0]probe7;
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input [0:0]probe8;
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input [7:0]probe9;
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input [15:0]probe10;
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input [1:0]probe11;
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input [7:0]probe12;
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input [7:0]probe13;
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input [15:0]probe14;
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input [15:0]probe15;
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input [8:0]probe16;
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input [15:0]probe17;
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input [8:0]probe18;
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input [7:0]probe19;
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input [15:0]probe20;
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input [15:0]probe21;
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input [7:0]probe22;
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input [7:0]probe23;
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input [7:0]probe24;
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input [12:0]probe25;
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input [31:0]probe26;
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input [3:0]probe27;
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input [31:0]probe28;
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input [0:0]probe29;
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input [0:0]probe30;
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input [0:0]probe31;
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input [0:0]probe32;
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input [0:0]probe33;
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input [0:0]probe34;
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input [0:0]probe35;
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input [0:0]probe36;
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input [0:0]probe37;
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input [0:0]probe38;
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input [0:0]probe39;
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input [0:0]probe40;
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input [0:0]probe41;
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input [0:0]probe42;
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input [0:0]probe43;
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input [0:0]probe44;
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input [0:0]probe45;
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input [0:0]probe46;
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input [0:0]probe47;
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input [0:0]probe48;
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input [0:0]probe49;
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input [0:0]probe50;
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input [0:0]probe51;
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input [0:0]probe52;
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input [0:0]probe53;
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input [0:0]probe54;
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input [0:0]probe55;
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input [0:0]probe56;
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input [0:0]probe57;
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input [0:0]probe58;
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input [0:0]probe59;
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input [0:0]probe60;
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input [0:0]probe61;
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endmodule
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@@ -0,0 +1,93 @@
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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-- Date : Wed Jun 24 16:42:05 2026
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-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
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-- Design : u_ila_0
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7z020clg400-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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Port (
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clk : in STD_LOGIC;
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probe0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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probe2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
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probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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probe4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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probe5 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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probe6 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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probe7 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe9 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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probe10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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probe11 : in STD_LOGIC_VECTOR ( 1 downto 0 );
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probe12 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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probe13 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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probe14 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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probe15 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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probe16 : in STD_LOGIC_VECTOR ( 8 downto 0 );
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probe17 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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probe18 : in STD_LOGIC_VECTOR ( 8 downto 0 );
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probe19 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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probe20 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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probe21 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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probe22 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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probe23 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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probe24 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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probe25 : in STD_LOGIC_VECTOR ( 12 downto 0 );
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probe26 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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probe27 : in STD_LOGIC_VECTOR ( 3 downto 0 );
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probe28 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe54 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe55 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe56 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe57 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe58 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe59 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe60 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe61 : in STD_LOGIC_VECTOR ( 0 to 0 )
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);
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end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "clk,probe0[31:0],probe1[31:0],probe2[1:0],probe3[7:0],probe4[7:0],probe5[15:0],probe6[15:0],probe7[7:0],probe8[0:0],probe9[7:0],probe10[15:0],probe11[1:0],probe12[7:0],probe13[7:0],probe14[15:0],probe15[15:0],probe16[8:0],probe17[15:0],probe18[8:0],probe19[7:0],probe20[15:0],probe21[15:0],probe22[7:0],probe23[7:0],probe24[7:0],probe25[12:0],probe26[31:0],probe27[3:0],probe28[31:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0]";
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attribute X_CORE_INFO : string;
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attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
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begin
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end;
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+194
-11
@@ -2,43 +2,100 @@
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# DONOT REMOVE THIS FILE
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||||
# Unified simulation database file for selected simulation model for IP
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||||
#
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||||
# File: ssm.db (Fri Mar 29 13:04:39 2024)
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||||
# File: ssm.db (Wed Jun 24 17:45:27 2026)
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#
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# This file is generated by the unified simulation automation and contains the
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||||
# selected simulation model information for the IP/BD instances.
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||||
# DONOT REMOVE THIS FILE
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################################################################################
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axis_data_fifo_w32_d16,rtl
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||||
axis_data_fifo_w32_d32,rtl
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||||
axis_data_fifo_w8_d128,rtl
|
||||
dds_stim_16ch,rtl
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||||
c_add_s16_s32,rtl
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design_a9_1_CHANN_EN_0,rtl
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||||
design_a9_1_CHANN_EN_1,rtl
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||||
design_a9_1_CHANN_EN_2,rtl
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||||
design_a9_1_CHANN_SEL_0,rtl
|
||||
design_a9_1_STIM_SPI_0,rtl
|
||||
design_a9_1_ZCHECK_SPI_0,rtl
|
||||
design_a9_1_Z_IO_0,rtl
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||||
design_a9_1_axi_bram_ctrl_0_0,rtl
|
||||
design_a9_1_axi_bram_ctrl_1_0,rtl
|
||||
design_a9_1_axi_bram_ctrl_2_0,rtl
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||||
design_a9_1_axi_bram_ctrl_3_0,rtl
|
||||
design_a9_1_axi_bram_ctrl_3_1,rtl
|
||||
design_a9_1_axi_bram_ctrl_4_0,rtl
|
||||
design_a9_1_axi_bram_ctrl_5_0,rtl
|
||||
design_a9_1_axi_bram_ctrl_6_0,rtl
|
||||
design_a9_1_axi_dma_0_0,rtl
|
||||
design_a9_1_axi_dma_1_0,rtl
|
||||
design_a9_1_axi_dma_1_1,rtl
|
||||
design_a9_1_axi_dma_2_0,rtl
|
||||
design_a9_1_axi_gpio_0_0,rtl
|
||||
design_a9_1_axi_iic_0_0,rtl
|
||||
design_a9_1_axi_iic_1_0,rtl
|
||||
design_a9_1_axi_gpio_1_0,rtl
|
||||
design_a9_1_axi_quad_spi_0_0,rtl
|
||||
design_a9_1_axi_smc_0,rtl
|
||||
design_a9_1_axis_data_fifo_0_0,rtl
|
||||
design_a9_1_axis_data_fifo_1_0,rtl
|
||||
design_a9_1_axis_data_fifo_1_1,rtl
|
||||
design_a9_1_axis_data_fifo_2_0,rtl
|
||||
design_a9_1_processing_system7_0_0,rtl
|
||||
design_a9_1_rst_ps7_0_50M_0,rtl
|
||||
design_a9_1_smartconnect_0_0,rtl
|
||||
design_a9_1_xlconcat_0_0,rtl
|
||||
mult_gen_au8_bu9_p8,rtl
|
||||
fifo_generator_0,rtl
|
||||
fifo_generator_1,rtl
|
||||
vio_cur_flt_state,rtl
|
||||
bd_6e35_arinsw_0,rtl
|
||||
bd_6e35_arinsw_1,rtl
|
||||
bd_6e35_arinsw_2,rtl
|
||||
bd_6e35_arinsw_3,rtl
|
||||
bd_6e35_arinsw_4,rtl
|
||||
bd_6e35_arinsw_5,rtl
|
||||
bd_6e35_arinsw_6,rtl
|
||||
bd_6e35_arinsw_7,rtl
|
||||
bd_6e35_arinsw_8,rtl
|
||||
bd_6e35_arni_0,rtl
|
||||
bd_6e35_aroutsw_0,rtl
|
||||
bd_6e35_arni_1,rtl
|
||||
bd_6e35_arni_2,rtl
|
||||
bd_6e35_arni_3,rtl
|
||||
bd_6e35_arni_4,rtl
|
||||
bd_6e35_arni_5,rtl
|
||||
bd_6e35_arni_6,rtl
|
||||
bd_6e35_arni_7,rtl
|
||||
bd_6e35_awinsw_0,rtl
|
||||
bd_6e35_awinsw_1,rtl
|
||||
bd_6e35_awinsw_2,rtl
|
||||
bd_6e35_awinsw_3,rtl
|
||||
bd_6e35_awinsw_4,rtl
|
||||
bd_6e35_awinsw_5,rtl
|
||||
bd_6e35_awinsw_6,rtl
|
||||
bd_6e35_awinsw_7,rtl
|
||||
bd_6e35_awinsw_8,rtl
|
||||
bd_6e35_awni_0,rtl
|
||||
bd_6e35_awoutsw_0,rtl
|
||||
bd_6e35_awni_1,rtl
|
||||
bd_6e35_awni_2,rtl
|
||||
bd_6e35_awni_3,rtl
|
||||
bd_6e35_awni_4,rtl
|
||||
bd_6e35_awni_5,rtl
|
||||
bd_6e35_awni_6,rtl
|
||||
bd_6e35_awni_7,rtl
|
||||
bd_6e35_binsw_0,rtl
|
||||
bd_6e35_binsw_1,rtl
|
||||
bd_6e35_binsw_2,rtl
|
||||
bd_6e35_binsw_3,rtl
|
||||
bd_6e35_binsw_4,rtl
|
||||
bd_6e35_binsw_5,rtl
|
||||
bd_6e35_binsw_6,rtl
|
||||
bd_6e35_binsw_7,rtl
|
||||
bd_6e35_binsw_8,rtl
|
||||
bd_6e35_bni_0,rtl
|
||||
bd_6e35_boutsw_0,rtl
|
||||
bd_6e35_bni_1,rtl
|
||||
bd_6e35_bni_2,rtl
|
||||
bd_6e35_bni_3,rtl
|
||||
bd_6e35_bni_4,rtl
|
||||
bd_6e35_bni_5,rtl
|
||||
bd_6e35_bni_6,rtl
|
||||
bd_6e35_bni_7,rtl
|
||||
bd_6e35_m00arn_0,rtl
|
||||
bd_6e35_m00awn_0,rtl
|
||||
bd_6e35_m00bn_0,rtl
|
||||
@@ -109,11 +166,109 @@ bd_6e35_m09e_0,rtl
|
||||
bd_6e35_m09rn_0,rtl
|
||||
bd_6e35_m09s2a_0,rtl
|
||||
bd_6e35_m09wn_0,rtl
|
||||
bd_6e35_m10arn_0,rtl
|
||||
bd_6e35_m10awn_0,rtl
|
||||
bd_6e35_m10bn_0,rtl
|
||||
bd_6e35_m10e_0,rtl
|
||||
bd_6e35_m10rn_0,rtl
|
||||
bd_6e35_m10s2a_0,rtl
|
||||
bd_6e35_m10wn_0,rtl
|
||||
bd_6e35_m11arn_0,rtl
|
||||
bd_6e35_m11awn_0,rtl
|
||||
bd_6e35_m11bn_0,rtl
|
||||
bd_6e35_m11e_0,rtl
|
||||
bd_6e35_m11rn_0,rtl
|
||||
bd_6e35_m11s2a_0,rtl
|
||||
bd_6e35_m11wn_0,rtl
|
||||
bd_6e35_m12arn_0,rtl
|
||||
bd_6e35_m12awn_0,rtl
|
||||
bd_6e35_m12bn_0,rtl
|
||||
bd_6e35_m12e_0,rtl
|
||||
bd_6e35_m12rn_0,rtl
|
||||
bd_6e35_m12s2a_0,rtl
|
||||
bd_6e35_m12wn_0,rtl
|
||||
bd_6e35_m13arn_0,rtl
|
||||
bd_6e35_m13awn_0,rtl
|
||||
bd_6e35_m13bn_0,rtl
|
||||
bd_6e35_m13e_0,rtl
|
||||
bd_6e35_m13rn_0,rtl
|
||||
bd_6e35_m13s2a_0,rtl
|
||||
bd_6e35_m13wn_0,rtl
|
||||
bd_6e35_m14arn_0,rtl
|
||||
bd_6e35_m14awn_0,rtl
|
||||
bd_6e35_m14bn_0,rtl
|
||||
bd_6e35_m14e_0,rtl
|
||||
bd_6e35_m14rn_0,rtl
|
||||
bd_6e35_m14s2a_0,rtl
|
||||
bd_6e35_m14wn_0,rtl
|
||||
bd_6e35_m15arn_0,rtl
|
||||
bd_6e35_m15awn_0,rtl
|
||||
bd_6e35_m15bn_0,rtl
|
||||
bd_6e35_m15e_0,rtl
|
||||
bd_6e35_m15rn_0,rtl
|
||||
bd_6e35_m15s2a_0,rtl
|
||||
bd_6e35_m15wn_0,rtl
|
||||
bd_6e35_m16arn_0,rtl
|
||||
bd_6e35_m16awn_0,rtl
|
||||
bd_6e35_m16bn_0,rtl
|
||||
bd_6e35_m16e_0,rtl
|
||||
bd_6e35_m16rn_0,rtl
|
||||
bd_6e35_m16s2a_0,rtl
|
||||
bd_6e35_m16wn_0,rtl
|
||||
bd_6e35_m17arn_0,rtl
|
||||
bd_6e35_m17awn_0,rtl
|
||||
bd_6e35_m17bn_0,rtl
|
||||
bd_6e35_m17e_0,rtl
|
||||
bd_6e35_m17rn_0,rtl
|
||||
bd_6e35_m17s2a_0,rtl
|
||||
bd_6e35_m17wn_0,rtl
|
||||
bd_6e35_m18arn_0,rtl
|
||||
bd_6e35_m18awn_0,rtl
|
||||
bd_6e35_m18bn_0,rtl
|
||||
bd_6e35_m18e_0,rtl
|
||||
bd_6e35_m18rn_0,rtl
|
||||
bd_6e35_m18s2a_0,rtl
|
||||
bd_6e35_m18wn_0,rtl
|
||||
bd_6e35_m19arn_0,rtl
|
||||
bd_6e35_m19awn_0,rtl
|
||||
bd_6e35_m19bn_0,rtl
|
||||
bd_6e35_m19e_0,rtl
|
||||
bd_6e35_m19rn_0,rtl
|
||||
bd_6e35_m19s2a_0,rtl
|
||||
bd_6e35_m19wn_0,rtl
|
||||
bd_6e35_m20arn_0,rtl
|
||||
bd_6e35_m20awn_0,rtl
|
||||
bd_6e35_m20bn_0,rtl
|
||||
bd_6e35_m20e_0,rtl
|
||||
bd_6e35_m20rn_0,rtl
|
||||
bd_6e35_m20s2a_0,rtl
|
||||
bd_6e35_m20wn_0,rtl
|
||||
bd_6e35_m21arn_0,rtl
|
||||
bd_6e35_m21awn_0,rtl
|
||||
bd_6e35_m21bn_0,rtl
|
||||
bd_6e35_m21e_0,rtl
|
||||
bd_6e35_m21rn_0,rtl
|
||||
bd_6e35_m21s2a_0,rtl
|
||||
bd_6e35_m21wn_0,rtl
|
||||
bd_6e35_one_0,rtl
|
||||
bd_6e35_psr_aclk_0,rtl
|
||||
bd_6e35_rinsw_0,rtl
|
||||
bd_6e35_rinsw_1,rtl
|
||||
bd_6e35_rinsw_2,rtl
|
||||
bd_6e35_rinsw_3,rtl
|
||||
bd_6e35_rinsw_4,rtl
|
||||
bd_6e35_rinsw_5,rtl
|
||||
bd_6e35_rinsw_6,rtl
|
||||
bd_6e35_rinsw_7,rtl
|
||||
bd_6e35_rinsw_8,rtl
|
||||
bd_6e35_rni_0,rtl
|
||||
bd_6e35_routsw_0,rtl
|
||||
bd_6e35_rni_1,rtl
|
||||
bd_6e35_rni_2,rtl
|
||||
bd_6e35_rni_3,rtl
|
||||
bd_6e35_rni_4,rtl
|
||||
bd_6e35_rni_5,rtl
|
||||
bd_6e35_rni_6,rtl
|
||||
bd_6e35_rni_7,rtl
|
||||
bd_6e35_s00a2s_0,rtl
|
||||
bd_6e35_s00mmu_0,rtl
|
||||
bd_6e35_s00sic_0,rtl
|
||||
@@ -124,8 +279,22 @@ bd_6e35_sbn_0,rtl
|
||||
bd_6e35_srn_0,rtl
|
||||
bd_6e35_swn_0,rtl
|
||||
bd_6e35_winsw_0,rtl
|
||||
bd_6e35_winsw_1,rtl
|
||||
bd_6e35_winsw_2,rtl
|
||||
bd_6e35_winsw_3,rtl
|
||||
bd_6e35_winsw_4,rtl
|
||||
bd_6e35_winsw_5,rtl
|
||||
bd_6e35_winsw_6,rtl
|
||||
bd_6e35_winsw_7,rtl
|
||||
bd_6e35_winsw_8,rtl
|
||||
bd_6e35_wni_0,rtl
|
||||
bd_6e35_woutsw_0,rtl
|
||||
bd_6e35_wni_1,rtl
|
||||
bd_6e35_wni_2,rtl
|
||||
bd_6e35_wni_3,rtl
|
||||
bd_6e35_wni_4,rtl
|
||||
bd_6e35_wni_5,rtl
|
||||
bd_6e35_wni_6,rtl
|
||||
bd_6e35_wni_7,rtl
|
||||
bd_962a_arsw_0,rtl
|
||||
bd_962a_awsw_0,rtl
|
||||
bd_962a_bsw_0,rtl
|
||||
@@ -147,9 +316,23 @@ bd_962a_s01a2s_0,rtl
|
||||
bd_962a_s01mmu_0,rtl
|
||||
bd_962a_s01sic_0,rtl
|
||||
bd_962a_s01tr_0,rtl
|
||||
bd_962a_s02a2s_0,rtl
|
||||
bd_962a_s02mmu_0,rtl
|
||||
bd_962a_s02sic_0,rtl
|
||||
bd_962a_s02tr_0,rtl
|
||||
bd_962a_s03a2s_0,rtl
|
||||
bd_962a_s03mmu_0,rtl
|
||||
bd_962a_s03sic_0,rtl
|
||||
bd_962a_s03tr_0,rtl
|
||||
bd_962a_sarn_0,rtl
|
||||
bd_962a_sawn_0,rtl
|
||||
bd_962a_sawn_1,rtl
|
||||
bd_962a_sawn_2,rtl
|
||||
bd_962a_sbn_0,rtl
|
||||
bd_962a_sbn_1,rtl
|
||||
bd_962a_sbn_2,rtl
|
||||
bd_962a_srn_0,rtl
|
||||
bd_962a_swn_0,rtl
|
||||
bd_962a_swn_1,rtl
|
||||
bd_962a_swn_2,rtl
|
||||
bd_962a_wsw_0,rtl
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
version:1
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:343
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:242
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:377
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:320
|
||||
eof:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303130636c673430302d32:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303230636c673430302d32:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:63363470726f5f746f70:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
@@ -42,7 +42,7 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a353873:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323738372e3637324d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313239312e3931344d42:00:00
|
||||
eof:2994962430
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30333a343173:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323932372e3439324d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313238312e3235384d42:00:00
|
||||
eof:2555888587
|
||||
|
||||
@@ -3,10 +3,10 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Sun Aug 4 13:38:06 2024">
|
||||
<application name="pa" timeStamp="Fri Sep 4 15:23:20 2026">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="49fe14c92914459aaee0d1ade43fb90b" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="424" type="ProjectIteration"/>
|
||||
<property name="ProjectIteration" value="469" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
|
||||
@@ -0,0 +1,4 @@
|
||||
version:1
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
|
||||
eof:241934075
|
||||
Reference in New Issue
Block a user