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chunk-sync
2026-09-11 14:09:32 +08:00
parent 17539ce9a3
commit db59cc669b
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c64_pro.cache/ip/2023.1/3/c/3cf36d047b77f0aa/3cf36d047b77f0aa.xci
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>ipcache</spirit:library>
<spirit:name>3cf36d047b77f0aa</spirit:name>
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<spirit:instanceName>dbg_hub</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xsdbm" spirit:version="3.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
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c64_pro.cache/ip/2023.1/3/c/3cf36d047b77f0aa/dbg_hub.dcp
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c64_pro.cache/ip/2023.1/3/c/3cf36d047b77f0aa/dbg_hub_sim_netlist.v
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c64_pro.cache/ip/2023.1/3/c/3cf36d047b77f0aa/dbg_hub_sim_netlist.vhdl
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c64_pro.cache/ip/2023.1/3/c/3cf36d047b77f0aa/dbg_hub_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Nov 12 17:34:50 2025
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_hub_stub.v
// Design : dbg_hub
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "xsdbm_v3_0_0_xsdbm,Vivado 2023.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sl_iport0_o, sl_oport0_i, clk)
/* synthesis syn_black_box black_box_pad_pin="sl_iport0_o[36:0],sl_oport0_i[16:0]" */
/* synthesis syn_force_seq_prim="clk" */;
output [36:0]sl_iport0_o;
input [16:0]sl_oport0_i;
input clk /* synthesis syn_isclock = 1 */;
endmodule
c64_pro.cache/ip/2023.1/3/c/3cf36d047b77f0aa/dbg_hub_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Wed Nov 12 17:34:50 2025
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_hub_stub.vhdl
-- Design : dbg_hub
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
sl_iport0_o : out STD_LOGIC_VECTOR ( 36 downto 0 );
sl_oport0_i : in STD_LOGIC_VECTOR ( 16 downto 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "sl_iport0_o[36:0],sl_oport0_i[16:0],clk";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "xsdbm_v3_0_0_xsdbm,Vivado 2023.1";
begin
end;
c64_pro.cache/ip/2023.1/3/c/3cf36d047b77f0aa/stats.txt
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Timestamp: Fri Apr 24 07:42:06 UTC 2026