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2026-09-11 14:09:32 +08:00
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c64_pro.cache/ip/2023.1/3/8/38804ebe230b6a56/design_a9_1_axi_smc_0_sim_netlist.vhdl
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c64_pro.cache/ip/2023.1/3/8/38804ebe230b6a56/design_a9_1_axi_smc_0_stub.v
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NumberHits:1
Timestamp: Mon Jul 06 05:11:01 UTC 2026
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c64_pro.cache/ip/2023.1/3/b/3b4beab38bbe78f0/u_ila_0_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Nov 19 10:27:33 2025
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
// Design : u_ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
probe51, probe52, probe53, probe54)
/* synthesis syn_black_box black_box_pad_pin="probe0[7:0],probe1[7:0],probe2[15:0],probe3[15:0],probe4[15:0],probe5[7:0],probe6[8:0],probe7[15:0],probe8[7:0],probe9[8:0],probe10[7:0],probe11[31:0],probe12[31:0],probe13[31:0],probe14[31:0],probe15[15:0],probe16[23:0],probe17[0:0],probe18[7:0],probe19[7:0],probe20[1:0],probe21[7:0],probe22[15:0],probe23[23:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0]" */
/* synthesis syn_force_seq_prim="clk" */;
input clk /* synthesis syn_isclock = 1 */;
input [7:0]probe0;
input [7:0]probe1;
input [15:0]probe2;
input [15:0]probe3;
input [15:0]probe4;
input [7:0]probe5;
input [8:0]probe6;
input [15:0]probe7;
input [7:0]probe8;
input [8:0]probe9;
input [7:0]probe10;
input [31:0]probe11;
input [31:0]probe12;
input [31:0]probe13;
input [31:0]probe14;
input [15:0]probe15;
input [23:0]probe16;
input [0:0]probe17;
input [7:0]probe18;
input [7:0]probe19;
input [1:0]probe20;
input [7:0]probe21;
input [15:0]probe22;
input [23:0]probe23;
input [0:0]probe24;
input [0:0]probe25;
input [0:0]probe26;
input [0:0]probe27;
input [0:0]probe28;
input [0:0]probe29;
input [0:0]probe30;
input [0:0]probe31;
input [0:0]probe32;
input [0:0]probe33;
input [0:0]probe34;
input [0:0]probe35;
input [0:0]probe36;
input [0:0]probe37;
input [0:0]probe38;
input [0:0]probe39;
input [0:0]probe40;
input [0:0]probe41;
input [0:0]probe42;
input [0:0]probe43;
input [0:0]probe44;
input [0:0]probe45;
input [0:0]probe46;
input [0:0]probe47;
input [0:0]probe48;
input [0:0]probe49;
input [0:0]probe50;
input [0:0]probe51;
input [0:0]probe52;
input [0:0]probe53;
input [0:0]probe54;
endmodule
c64_pro.cache/ip/2023.1/3/b/3b4beab38bbe78f0/u_ila_0_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Wed Nov 19 10:27:33 2025
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
-- Design : u_ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe4 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe6 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe7 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe9 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe12 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe14 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe15 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe16 : in STD_LOGIC_VECTOR ( 23 downto 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe19 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 1 downto 0 );
probe21 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe23 : in STD_LOGIC_VECTOR ( 23 downto 0 );
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe26 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[7:0],probe1[7:0],probe2[15:0],probe3[15:0],probe4[15:0],probe5[7:0],probe6[8:0],probe7[15:0],probe8[7:0],probe9[8:0],probe10[7:0],probe11[31:0],probe12[31:0],probe13[31:0],probe14[31:0],probe15[15:0],probe16[23:0],probe17[0:0],probe18[7:0],probe19[7:0],probe20[1:0],probe21[7:0],probe22[15:0],probe23[23:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
begin
end;
c64_pro.cache/ip/2023.1/3/c/3c6bbcbcc9068e37/3c6bbcbcc9068e37.xci
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Thu Aug 20 10:17:20 2026
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_smartconnect_0_0_stub.v
// Design : design_a9_1_smartconnect_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "bd_962a,Vivado 2023.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, S00_AXI_araddr, S00_AXI_arlen,
S00_AXI_arsize, S00_AXI_arburst, S00_AXI_arlock, S00_AXI_arcache, S00_AXI_arprot,
S00_AXI_arqos, S00_AXI_arvalid, S00_AXI_arready, S00_AXI_rdata, S00_AXI_rresp,
S00_AXI_rlast, S00_AXI_rvalid, S00_AXI_rready, S01_AXI_awaddr, S01_AXI_awlen,
S01_AXI_awsize, S01_AXI_awburst, S01_AXI_awlock, S01_AXI_awcache, S01_AXI_awprot,
S01_AXI_awqos, S01_AXI_awvalid, S01_AXI_awready, S01_AXI_wdata, S01_AXI_wstrb,
S01_AXI_wlast, S01_AXI_wvalid, S01_AXI_wready, S01_AXI_bresp, S01_AXI_bvalid,
S01_AXI_bready, S02_AXI_awaddr, S02_AXI_awlen, S02_AXI_awsize, S02_AXI_awburst,
S02_AXI_awlock, S02_AXI_awcache, S02_AXI_awprot, S02_AXI_awqos, S02_AXI_awvalid,
S02_AXI_awready, S02_AXI_wdata, S02_AXI_wstrb, S02_AXI_wlast, S02_AXI_wvalid,
S02_AXI_wready, S02_AXI_bresp, S02_AXI_bvalid, S02_AXI_bready, S03_AXI_awaddr,
S03_AXI_awlen, S03_AXI_awsize, S03_AXI_awburst, S03_AXI_awlock, S03_AXI_awcache,
S03_AXI_awprot, S03_AXI_awqos, S03_AXI_awvalid, S03_AXI_awready, S03_AXI_wdata,
S03_AXI_wstrb, S03_AXI_wlast, S03_AXI_wvalid, S03_AXI_wready, S03_AXI_bresp,
S03_AXI_bvalid, S03_AXI_bready, M00_AXI_awaddr, M00_AXI_awlen, M00_AXI_awsize,
M00_AXI_awburst, M00_AXI_awlock, M00_AXI_awcache, M00_AXI_awprot, M00_AXI_awqos,
M00_AXI_awvalid, M00_AXI_awready, M00_AXI_wdata, M00_AXI_wstrb, M00_AXI_wlast,
M00_AXI_wvalid, M00_AXI_wready, M00_AXI_bresp, M00_AXI_bvalid, M00_AXI_bready,
M00_AXI_araddr, M00_AXI_arlen, M00_AXI_arsize, M00_AXI_arburst, M00_AXI_arlock,
M00_AXI_arcache, M00_AXI_arprot, M00_AXI_arqos, M00_AXI_arvalid, M00_AXI_arready,
M00_AXI_rdata, M00_AXI_rresp, M00_AXI_rlast, M00_AXI_rvalid, M00_AXI_rready)
/* synthesis syn_black_box black_box_pad_pin="aresetn,S00_AXI_araddr[31:0],S00_AXI_arlen[7:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[0:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rdata[31:0],S00_AXI_rresp[1:0],S00_AXI_rlast,S00_AXI_rvalid,S00_AXI_rready,S01_AXI_awaddr[31:0],S01_AXI_awlen[7:0],S01_AXI_awsize[2:0],S01_AXI_awburst[1:0],S01_AXI_awlock[0:0],S01_AXI_awcache[3:0],S01_AXI_awprot[2:0],S01_AXI_awqos[3:0],S01_AXI_awvalid,S01_AXI_awready,S01_AXI_wdata[31:0],S01_AXI_wstrb[3:0],S01_AXI_wlast,S01_AXI_wvalid,S01_AXI_wready,S01_AXI_bresp[1:0],S01_AXI_bvalid,S01_AXI_bready,S02_AXI_awaddr[31:0],S02_AXI_awlen[7:0],S02_AXI_awsize[2:0],S02_AXI_awburst[1:0],S02_AXI_awlock[0:0],S02_AXI_awcache[3:0],S02_AXI_awprot[2:0],S02_AXI_awqos[3:0],S02_AXI_awvalid,S02_AXI_awready,S02_AXI_wdata[31:0],S02_AXI_wstrb[3:0],S02_AXI_wlast,S02_AXI_wvalid,S02_AXI_wready,S02_AXI_bresp[1:0],S02_AXI_bvalid,S02_AXI_bready,S03_AXI_awaddr[31:0],S03_AXI_awlen[7:0],S03_AXI_awsize[2:0],S03_AXI_awburst[1:0],S03_AXI_awlock[0:0],S03_AXI_awcache[3:0],S03_AXI_awprot[2:0],S03_AXI_awqos[3:0],S03_AXI_awvalid,S03_AXI_awready,S03_AXI_wdata[31:0],S03_AXI_wstrb[3:0],S03_AXI_wlast,S03_AXI_wvalid,S03_AXI_wready,S03_AXI_bresp[1:0],S03_AXI_bvalid,S03_AXI_bready,M00_AXI_awaddr[31:0],M00_AXI_awlen[3:0],M00_AXI_awsize[2:0],M00_AXI_awburst[1:0],M00_AXI_awlock[1:0],M00_AXI_awcache[3:0],M00_AXI_awprot[2:0],M00_AXI_awqos[3:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wlast,M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[31:0],M00_AXI_arlen[3:0],M00_AXI_arsize[2:0],M00_AXI_arburst[1:0],M00_AXI_arlock[1:0],M00_AXI_arcache[3:0],M00_AXI_arprot[2:0],M00_AXI_arqos[3:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rlast,M00_AXI_rvalid,M00_AXI_rready" */
/* synthesis syn_force_seq_prim="aclk" */;
input aclk /* synthesis syn_isclock = 1 */;
input aresetn;
input [31:0]S00_AXI_araddr;
input [7:0]S00_AXI_arlen;
input [2:0]S00_AXI_arsize;
input [1:0]S00_AXI_arburst;
input [0:0]S00_AXI_arlock;
input [3:0]S00_AXI_arcache;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
input S00_AXI_arvalid;
output S00_AXI_arready;
output [31:0]S00_AXI_rdata;
output [1:0]S00_AXI_rresp;
output S00_AXI_rlast;
output S00_AXI_rvalid;
input S00_AXI_rready;
input [31:0]S01_AXI_awaddr;
input [7:0]S01_AXI_awlen;
input [2:0]S01_AXI_awsize;
input [1:0]S01_AXI_awburst;
input [0:0]S01_AXI_awlock;
input [3:0]S01_AXI_awcache;
input [2:0]S01_AXI_awprot;
input [3:0]S01_AXI_awqos;
input S01_AXI_awvalid;
output S01_AXI_awready;
input [31:0]S01_AXI_wdata;
input [3:0]S01_AXI_wstrb;
input S01_AXI_wlast;
input S01_AXI_wvalid;
output S01_AXI_wready;
output [1:0]S01_AXI_bresp;
output S01_AXI_bvalid;
input S01_AXI_bready;
input [31:0]S02_AXI_awaddr;
input [7:0]S02_AXI_awlen;
input [2:0]S02_AXI_awsize;
input [1:0]S02_AXI_awburst;
input [0:0]S02_AXI_awlock;
input [3:0]S02_AXI_awcache;
input [2:0]S02_AXI_awprot;
input [3:0]S02_AXI_awqos;
input S02_AXI_awvalid;
output S02_AXI_awready;
input [31:0]S02_AXI_wdata;
input [3:0]S02_AXI_wstrb;
input S02_AXI_wlast;
input S02_AXI_wvalid;
output S02_AXI_wready;
output [1:0]S02_AXI_bresp;
output S02_AXI_bvalid;
input S02_AXI_bready;
input [31:0]S03_AXI_awaddr;
input [7:0]S03_AXI_awlen;
input [2:0]S03_AXI_awsize;
input [1:0]S03_AXI_awburst;
input [0:0]S03_AXI_awlock;
input [3:0]S03_AXI_awcache;
input [2:0]S03_AXI_awprot;
input [3:0]S03_AXI_awqos;
input S03_AXI_awvalid;
output S03_AXI_awready;
input [31:0]S03_AXI_wdata;
input [3:0]S03_AXI_wstrb;
input S03_AXI_wlast;
input S03_AXI_wvalid;
output S03_AXI_wready;
output [1:0]S03_AXI_bresp;
output S03_AXI_bvalid;
input S03_AXI_bready;
output [31:0]M00_AXI_awaddr;
output [3:0]M00_AXI_awlen;
output [2:0]M00_AXI_awsize;
output [1:0]M00_AXI_awburst;
output [1:0]M00_AXI_awlock;
output [3:0]M00_AXI_awcache;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
output M00_AXI_awvalid;
input M00_AXI_awready;
output [31:0]M00_AXI_wdata;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wlast;
output M00_AXI_wvalid;
input M00_AXI_wready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
output M00_AXI_bready;
output [31:0]M00_AXI_araddr;
output [3:0]M00_AXI_arlen;
output [2:0]M00_AXI_arsize;
output [1:0]M00_AXI_arburst;
output [1:0]M00_AXI_arlock;
output [3:0]M00_AXI_arcache;
output [2:0]M00_AXI_arprot;
output [3:0]M00_AXI_arqos;
output M00_AXI_arvalid;
input M00_AXI_arready;
input [31:0]M00_AXI_rdata;
input [1:0]M00_AXI_rresp;
input M00_AXI_rlast;
input M00_AXI_rvalid;
output M00_AXI_rready;
endmodule
c64_pro.cache/ip/2023.1/3/c/3c6bbcbcc9068e37/design_a9_1_smartconnect_0_0_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Thu Aug 20 10:17:20 2026
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_smartconnect_0_0_stub.vhdl
-- Design : design_a9_1_smartconnect_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_arready : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_awready : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wvalid : in STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awvalid : in STD_LOGIC;
S02_AXI_awready : out STD_LOGIC;
S02_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_wlast : in STD_LOGIC;
S02_AXI_wvalid : in STD_LOGIC;
S02_AXI_wready : out STD_LOGIC;
S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_bvalid : out STD_LOGIC;
S02_AXI_bready : in STD_LOGIC;
S03_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S03_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S03_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S03_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awvalid : in STD_LOGIC;
S03_AXI_awready : out STD_LOGIC;
S03_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S03_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_wlast : in STD_LOGIC;
S03_AXI_wvalid : in STD_LOGIC;
S03_AXI_wready : out STD_LOGIC;
S03_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_bvalid : out STD_LOGIC;
S03_AXI_bready : in STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_awready : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wvalid : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_arready : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,S00_AXI_araddr[31:0],S00_AXI_arlen[7:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[0:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rdata[31:0],S00_AXI_rresp[1:0],S00_AXI_rlast,S00_AXI_rvalid,S00_AXI_rready,S01_AXI_awaddr[31:0],S01_AXI_awlen[7:0],S01_AXI_awsize[2:0],S01_AXI_awburst[1:0],S01_AXI_awlock[0:0],S01_AXI_awcache[3:0],S01_AXI_awprot[2:0],S01_AXI_awqos[3:0],S01_AXI_awvalid,S01_AXI_awready,S01_AXI_wdata[31:0],S01_AXI_wstrb[3:0],S01_AXI_wlast,S01_AXI_wvalid,S01_AXI_wready,S01_AXI_bresp[1:0],S01_AXI_bvalid,S01_AXI_bready,S02_AXI_awaddr[31:0],S02_AXI_awlen[7:0],S02_AXI_awsize[2:0],S02_AXI_awburst[1:0],S02_AXI_awlock[0:0],S02_AXI_awcache[3:0],S02_AXI_awprot[2:0],S02_AXI_awqos[3:0],S02_AXI_awvalid,S02_AXI_awready,S02_AXI_wdata[31:0],S02_AXI_wstrb[3:0],S02_AXI_wlast,S02_AXI_wvalid,S02_AXI_wready,S02_AXI_bresp[1:0],S02_AXI_bvalid,S02_AXI_bready,S03_AXI_awaddr[31:0],S03_AXI_awlen[7:0],S03_AXI_awsize[2:0],S03_AXI_awburst[1:0],S03_AXI_awlock[0:0],S03_AXI_awcache[3:0],S03_AXI_awprot[2:0],S03_AXI_awqos[3:0],S03_AXI_awvalid,S03_AXI_awready,S03_AXI_wdata[31:0],S03_AXI_wstrb[3:0],S03_AXI_wlast,S03_AXI_wvalid,S03_AXI_wready,S03_AXI_bresp[1:0],S03_AXI_bvalid,S03_AXI_bready,M00_AXI_awaddr[31:0],M00_AXI_awlen[3:0],M00_AXI_awsize[2:0],M00_AXI_awburst[1:0],M00_AXI_awlock[1:0],M00_AXI_awcache[3:0],M00_AXI_awprot[2:0],M00_AXI_awqos[3:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wlast,M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[31:0],M00_AXI_arlen[3:0],M00_AXI_arsize[2:0],M00_AXI_arburst[1:0],M00_AXI_arlock[1:0],M00_AXI_arcache[3:0],M00_AXI_arprot[2:0],M00_AXI_arqos[3:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rlast,M00_AXI_rvalid,M00_AXI_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "bd_962a,Vivado 2023.1";
begin
end;
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NumberHits:1
Timestamp: Thu Aug 20 05:41:41 UTC 2026
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<spirit:instanceName>dbg_hub</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xsdbm" spirit:version="3.0"/>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XSDB_NUM_SLAVES">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XSDB_PERIOD_INT">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">dbg_hub</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Nov 12 17:34:50 2025
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_hub_stub.v
// Design : dbg_hub
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "xsdbm_v3_0_0_xsdbm,Vivado 2023.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sl_iport0_o, sl_oport0_i, clk)
/* synthesis syn_black_box black_box_pad_pin="sl_iport0_o[36:0],sl_oport0_i[16:0]" */
/* synthesis syn_force_seq_prim="clk" */;
output [36:0]sl_iport0_o;
input [16:0]sl_oport0_i;
input clk /* synthesis syn_isclock = 1 */;
endmodule
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Wed Nov 12 17:34:50 2025
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_hub_stub.vhdl
-- Design : dbg_hub
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
sl_iport0_o : out STD_LOGIC_VECTOR ( 36 downto 0 );
sl_oport0_i : in STD_LOGIC_VECTOR ( 16 downto 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "sl_iport0_o[36:0],sl_oport0_i[16:0],clk";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "xsdbm_v3_0_0_xsdbm,Vivado 2023.1";
begin
end;
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NumberHits:18
Timestamp: Fri Apr 24 07:42:06 UTC 2026
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Nov 25 17:24:34 2025
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
// Design : u_ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
probe51, probe52, probe53, probe54)
/* synthesis syn_black_box black_box_pad_pin="probe0[7:0],probe1[8:0],probe2[7:0],probe3[7:0],probe4[15:0],probe5[7:0],probe6[15:0],probe7[7:0],probe8[8:0],probe9[15:0],probe10[15:0],probe11[31:0],probe12[31:0],probe13[31:0],probe14[31:0],probe15[7:0],probe16[15:0],probe17[1:0],probe18[0:0],probe19[23:0],probe20[15:0],probe21[7:0],probe22[7:0],probe23[23:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0]" */
/* synthesis syn_force_seq_prim="clk" */;
input clk /* synthesis syn_isclock = 1 */;
input [7:0]probe0;
input [8:0]probe1;
input [7:0]probe2;
input [7:0]probe3;
input [15:0]probe4;
input [7:0]probe5;
input [15:0]probe6;
input [7:0]probe7;
input [8:0]probe8;
input [15:0]probe9;
input [15:0]probe10;
input [31:0]probe11;
input [31:0]probe12;
input [31:0]probe13;
input [31:0]probe14;
input [7:0]probe15;
input [15:0]probe16;
input [1:0]probe17;
input [0:0]probe18;
input [23:0]probe19;
input [15:0]probe20;
input [7:0]probe21;
input [7:0]probe22;
input [23:0]probe23;
input [0:0]probe24;
input [0:0]probe25;
input [0:0]probe26;
input [0:0]probe27;
input [0:0]probe28;
input [0:0]probe29;
input [0:0]probe30;
input [0:0]probe31;
input [0:0]probe32;
input [0:0]probe33;
input [0:0]probe34;
input [0:0]probe35;
input [0:0]probe36;
input [0:0]probe37;
input [0:0]probe38;
input [0:0]probe39;
input [0:0]probe40;
input [0:0]probe41;
input [0:0]probe42;
input [0:0]probe43;
input [0:0]probe44;
input [0:0]probe45;
input [0:0]probe46;
input [0:0]probe47;
input [0:0]probe48;
input [0:0]probe49;
input [0:0]probe50;
input [0:0]probe51;
input [0:0]probe52;
input [0:0]probe53;
input [0:0]probe54;
endmodule
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Tue Nov 25 17:24:34 2025
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
-- Design : u_ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe4 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe6 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe7 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe9 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe12 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe14 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe15 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe19 : in STD_LOGIC_VECTOR ( 23 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe21 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe23 : in STD_LOGIC_VECTOR ( 23 downto 0 );
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe26 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[7:0],probe1[8:0],probe2[7:0],probe3[7:0],probe4[15:0],probe5[7:0],probe6[15:0],probe7[7:0],probe8[8:0],probe9[15:0],probe10[15:0],probe11[31:0],probe12[31:0],probe13[31:0],probe14[31:0],probe15[7:0],probe16[15:0],probe17[1:0],probe18[0:0],probe19[23:0],probe20[15:0],probe21[7:0],probe22[7:0],probe23[23:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
begin
end;
c64_pro.cache/ip/2023.1/3/e/3e3450abf990a58e/3e3450abf990a58e.xci
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TREADY">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Jun 24 13:53:38 2026
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axis_data_fifo_2_0_stub.v
// Design : design_a9_1_axis_data_fifo_2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axis_data_fifo_v2_0_10_top,Vivado 2023.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axis_aresetn, s_axis_aclk, s_axis_tvalid,
s_axis_tready, s_axis_tdata, s_axis_tkeep, s_axis_tlast, m_axis_tvalid, m_axis_tready,
m_axis_tdata, m_axis_tkeep, m_axis_tlast, prog_full)
/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],s_axis_tkeep[3:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0],m_axis_tkeep[3:0],m_axis_tlast,prog_full" */
/* synthesis syn_force_seq_prim="s_axis_aclk" */;
input s_axis_aresetn;
input s_axis_aclk /* synthesis syn_isclock = 1 */;
input s_axis_tvalid;
output s_axis_tready;
input [31:0]s_axis_tdata;
input [3:0]s_axis_tkeep;
input s_axis_tlast;
output m_axis_tvalid;
input m_axis_tready;
output [31:0]m_axis_tdata;
output [3:0]m_axis_tkeep;
output m_axis_tlast;
output prog_full;
endmodule
c64_pro.cache/ip/2023.1/3/e/3e3450abf990a58e/design_a9_1_axis_data_fifo_2_0_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Wed Jun 24 13:53:38 2026
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axis_data_fifo_2_0_stub.vhdl
-- Design : design_a9_1_axis_data_fifo_2_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
s_axis_aresetn : in STD_LOGIC;
s_axis_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
prog_full : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],s_axis_tkeep[3:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0],m_axis_tkeep[3:0],m_axis_tlast,prog_full";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axis_data_fifo_v2_0_10_top,Vivado 2023.1";
begin
end;
c64_pro.cache/ip/2023.1/3/e/3e3450abf990a58e/stats.txt
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NumberHits:1
Timestamp: Wed Jun 24 05:54:02 UTC 2026