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chunk-sync
2026-09-11 16:18:23 +08:00
parent e4ba5f5837
commit c315cef09e
1297 changed files with 1380453 additions and 221838 deletions
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c64_pro.runs/axis_data_fifo_w8_d128_synth_1/.vivado.begin.rst
+1 -1
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@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="wenlibin" Host="840-5CG14025H4" Pid="169844" HostCore="8" HostMemory="034024464384">
<Process Command="vivado.bat" Owner="lixiangfu" Host="DESKTOP-VN054CM" Pid="36744" HostCore="20" HostMemory="0171579760640">
</Process>
</ProcessHandle>
c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp
BIN
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c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.tcl
+23 -25
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@@ -4,7 +4,7 @@
set TIME_start [clock seconds]
namespace eval ::optrace {
variable script "D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.tcl"
variable script "D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.tcl"
variable category "vivado_synth"
}
@@ -70,28 +70,26 @@ proc create_report { reportName command } {
}
}
OPTRACE "axis_data_fifo_w8_d128_synth_1" START { ROLLUP_AUTO }
set_param chipscope.maxJobs 2
set_msg_config -id {Common 17-41} -limit 10000000
set_param project.vivado.isBlockSynthRun true
set_msg_config -msgmgr_mode ooc_run
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7z010clg400-2
create_project -in_memory -part xc7z020clg400-2
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir D:/projects/vivadoPrj/c64_pro/c64_pro.cache/wt [current_project]
set_property parent.project_path D:/projects/vivadoPrj/c64_pro/c64_pro.xpr [current_project]
set_property webtalk.parent_dir D:/Project/A64/pl/a64_v0/c64_pro.cache/wt [current_project]
set_property parent.project_path D:/Project/A64/pl/a64_v0/c64_pro.xpr [current_project]
set_property XPM_LIBRARIES {XPM_CDC XPM_FIFO XPM_MEMORY} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo d:/projects/vivadoPrj/c64_pro/c64_pro.cache/ip [current_project]
set_property ip_output_repo d:/Project/A64/pl/a64_v0/c64_pro.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
OPTRACE "Adding files" START { }
read_ip -quiet d:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.xci
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc]
read_ip -quiet D:/Project/A64/pl/a64_v0/c64_pro.srcs/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.xci
set_property used_in_implementation false [get_files -all d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc]
OPTRACE "Adding files" END { }
# Mark all dcp files as not used in implementation to prevent them from being
@@ -107,14 +105,14 @@ set_property used_in_implementation false [get_files dont_touch.xdc]
set_param ips.enableIPCacheLiteLoad 1
OPTRACE "Configure IP Cache" START { }
set cacheID [config_ip_cache -export -no_bom -dir D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1 -new_name axis_data_fifo_w8_d128 -ip [get_ips axis_data_fifo_w8_d128]]
set cacheID [config_ip_cache -export -no_bom -dir D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1 -new_name axis_data_fifo_w8_d128 -ip [get_ips axis_data_fifo_w8_d128]]
OPTRACE "Configure IP Cache" END { }
if { $cacheID == "" } {
close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { }
synth_design -top axis_data_fifo_w8_d128 -part xc7z010clg400-2 -incremental_mode off -mode out_of_context
synth_design -top axis_data_fifo_w8_d128 -part xc7z020clg400-2 -incremental_mode off -mode out_of_context
OPTRACE "synth_design" END { }
OPTRACE "Write IP Cache" START { }
@@ -162,32 +160,32 @@ create_report "axis_data_fifo_w8_d128_synth_1_synth_report_utilization_0" "repor
OPTRACE "synth reports" END { }
if { [catch {
file copy -force D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.dcp
file copy -force D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.dcp
} _RESULT ] } {
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
write_verilog -force -mode synth_stub d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.v
write_verilog -force -mode synth_stub d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode synth_stub d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.vhdl
write_vhdl -force -mode synth_stub d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_verilog -force -mode funcsim d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_sim_netlist.v
write_verilog -force -mode funcsim d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode funcsim d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_sim_netlist.vhdl
write_vhdl -force -mode funcsim d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
@@ -197,32 +195,32 @@ if { [catch {
if { [catch {
file copy -force D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.dcp
file copy -force D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.dcp
} _RESULT ] } {
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
file rename -force D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128_stub.v d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.v
file rename -force D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128_stub.v d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128_stub.vhdl d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.vhdl
file rename -force D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128_stub.vhdl d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128_sim_netlist.v d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_sim_netlist.v
file rename -force D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128_sim_netlist.v d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128_sim_netlist.vhdl d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_sim_netlist.vhdl
file rename -force D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128_sim_netlist.vhdl d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
@@ -230,15 +228,15 @@ if { [catch {
close [open .end.used_ip_cache.rst w]
}; # end if cacheID
if {[file isdir D:/projects/vivadoPrj/c64_pro/c64_pro.ip_user_files/ip/axis_data_fifo_w8_d128]} {
if {[file isdir D:/Project/A64/pl/a64_v0/c64_pro.ip_user_files/ip/axis_data_fifo_w8_d128]} {
catch {
file copy -force d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.v D:/projects/vivadoPrj/c64_pro/c64_pro.ip_user_files/ip/axis_data_fifo_w8_d128
file copy -force d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.v D:/Project/A64/pl/a64_v0/c64_pro.ip_user_files/ip/axis_data_fifo_w8_d128
}
}
if {[file isdir D:/projects/vivadoPrj/c64_pro/c64_pro.ip_user_files/ip/axis_data_fifo_w8_d128]} {
if {[file isdir D:/Project/A64/pl/a64_v0/c64_pro.ip_user_files/ip/axis_data_fifo_w8_d128]} {
catch {
file copy -force d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.vhdl D:/projects/vivadoPrj/c64_pro/c64_pro.ip_user_files/ip/axis_data_fifo_w8_d128
file copy -force d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.vhdl D:/Project/A64/pl/a64_v0/c64_pro.ip_user_files/ip/axis_data_fifo_w8_d128
}
}
file delete __synthesis_is_running__
c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.vds
+61 -61
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@@ -3,36 +3,36 @@
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Fri Mar 29 11:58:36 2024
# Process ID: 45500
# Current directory: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1
# Start of session at: Tue Oct 28 20:59:13 2025
# Process ID: 49460
# Current directory: D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1
# Command line: vivado.exe -log axis_data_fifo_w8_d128.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source axis_data_fifo_w8_d128.tcl
# Log file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.vds
# Journal file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1\vivado.jou
# Running On: 840-5CG14025H4, OS: Windows, CPU Frequency: 2803 MHz, CPU Physical cores: 4, Host memory: 34024 MB
# Log file: D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.vds
# Journal file: D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1\vivado.jou
# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
#-----------------------------------------------------------
source axis_data_fifo_w8_d128.tcl -notrace
create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1385.828 ; gain = 160.668
create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1467.398 ; gain = 161.281
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: axis_data_fifo_w8_d128
Command: synth_design -top axis_data_fifo_w8_d128 -part xc7z010clg400-2 -incremental_mode off -mode out_of_context
Command: synth_design -top axis_data_fifo_w8_d128 -part xc7z020clg400-2 -incremental_mode off -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Device 21-403] Loading part xc7z010clg400-2
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 27696
INFO: [Synth 8-7075] Helper process launched with PID 42852
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 2211.453 ; gain = 409.789
Starting RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2320.645 ; gain = 408.867
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_w8_d128' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/synth/axis_data_fifo_w8_d128.v:53]
INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_v2_0_10_top' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_data_fifo_v2_0_vl_rfs.v:54]
INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_aclken_converter_wrapper' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:599]
INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:809]
INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:809]
INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:991]
INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:991]
INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_aclken_converter_wrapper' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:599]
INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_w8_d128' [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/synth/axis_data_fifo_w8_d128.v:53]
INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_v2_0_10_top' [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_data_fifo_v2_0_vl_rfs.v:54]
INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_aclken_converter_wrapper' [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:599]
INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector' [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:809]
INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector' (0#1) [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:809]
INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis' [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:991]
INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis' (0#1) [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:991]
INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_aclken_converter_wrapper' (0#1) [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:599]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_axis' [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2349]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1058]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (0#1) [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1058]
@@ -57,8 +57,8 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [C:/
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (0#1) [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1859]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (0#1) [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:55]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_axis' (0#1) [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2349]
INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_v2_0_10_top' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_data_fifo_v2_0_vl_rfs.v:54]
INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_w8_d128' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/synth/axis_data_fifo_w8_d128.v:53]
INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_v2_0_10_top' (0#1) [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_data_fifo_v2_0_vl_rfs.v:54]
INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_w8_d128' (0#1) [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/synth/axis_data_fifo_w8_d128.v:53]
WARNING: [Synth 8-6014] Unused sequential element gen_rd_b.gen_doutb_pipe.enb_pipe_reg[0] was removed. [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:3071]
WARNING: [Synth 8-6014] Unused sequential element gdvld.data_valid_std_reg was removed. [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:537]
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1391]
@@ -92,55 +92,55 @@ WARNING: [Synth 8-7129] Port injectdbiterrb in module xpm_memory_base is either
WARNING: [Synth 8-7129] Port m_aclk in module xpm_fifo_axis is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axis_aclk in module axis_data_fifo_v2_0_10_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 2310.840 ; gain = 509.176
Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 2418.816 ; gain = 507.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 2328.754 ; gain = 527.090
Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 2436.738 ; gain = 524.961
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 2328.754 ; gain = 527.090
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 2436.738 ; gain = 524.961
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2328.754 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2436.738 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc] for cell 'inst'
Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc] for cell 'inst'
Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc]
Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc]
Parsing XDC File [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc] for cell 'inst'
Finished Parsing XDC File [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc] for cell 'inst'
Parsing XDC File [D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc]
Finished Parsing XDC File [D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/axis_data_fifo_w8_d128_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/axis_data_fifo_w8_d128_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
INFO: [Project 1-1714] 2 XPM XDC files have been applied to the design.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2441.469 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2549.336 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 2441.469 ; gain = 0.000
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 2549.355 ; gain = 0.020
INFO: [Designutils 20-5008] Incremental synthesis strategy off
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Constraint Validation : Time (s): cpu = 00:00:26 ; elapsed = 00:00:35 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z010clg400-2
Loading part: xc7z020clg400-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:26 ; elapsed = 00:00:35 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc, line 9).
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc, line 9).
Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst /\gaxis_rst_sync.xpm_cdc_sync_rst_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst . (constraint file auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:35 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base'
---------------------------------------------------------------------------------------------------
@@ -153,7 +153,7 @@ INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_re
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
@@ -185,8 +185,8 @@ Finished RTL Component Statistics
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 80 (col length:40)
BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
@@ -225,7 +225,7 @@ WARNING: [Synth 8-7129] Port s_axis_tuser[0] in module axis_data_fifo_v2_0_10_to
WARNING: [Synth 8-7129] Port m_axis_aclk in module axis_data_fifo_v2_0_10_top is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axis_aclken in module axis_data_fifo_v2_0_10_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:19 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
@@ -246,13 +246,13 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Timing Optimization : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
@@ -272,7 +272,7 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Technology Mapping : Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@@ -290,37 +290,37 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished IO Insertion : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Renaming Generated Instances : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Renaming Generated Ports : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Handling Custom Attributes : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Renaming Generated Nets : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -347,18 +347,18 @@ Report Cell Usage:
|9 |FDSE | 8|
+------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Writing Synthesis Report : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 31 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 2441.469 ; gain = 527.090
Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:30 . Memory (MB): peak = 2441.469 ; gain = 639.805
Synthesis Optimization Runtime : Time (s): cpu = 00:00:33 ; elapsed = 00:00:56 . Memory (MB): peak = 2549.355 ; gain = 524.961
Synthesis Optimization Complete : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2441.469 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2549.355 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2441.469 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2549.355 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
@@ -366,10 +366,10 @@ Synth Design complete | Checksum: 3e2929b0
INFO: [Common 17-83] Releasing license: Synthesis
54 Infos, 63 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:42 . Memory (MB): peak = 2441.469 ; gain = 1016.520
INFO: [Common 17-1381] The checkpoint 'D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP axis_data_fifo_w8_d128, cache-ID = 2d33c11f77ef32b5
synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:13 . Memory (MB): peak = 2549.355 ; gain = 1043.230
INFO: [Common 17-1381] The checkpoint 'D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP axis_data_fifo_w8_d128, cache-ID = 53ac5cb930f6d39d
INFO: [Coretcl 2-1174] Renamed 11 cell refs.
INFO: [Common 17-1381] The checkpoint 'D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp' has been generated.
INFO: [Common 17-1381] The checkpoint 'D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file axis_data_fifo_w8_d128_utilization_synth.rpt -pb axis_data_fifo_w8_d128_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Mar 29 11:59:39 2024...
INFO: [Common 17-206] Exiting Vivado at Tue Oct 28 21:00:59 2025...
c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128_utilization_synth.pb
BIN
View File
Binary file not shown.
c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128_utilization_synth.rpt
+33 -33
View File
@@ -1,11 +1,11 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Fri Mar 29 11:59:39 2024
| Host : 840-5CG14025H4 running 64-bit major release (build 9200)
| Date : Tue Oct 28 21:00:59 2025
| Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
| Command : report_utilization -file axis_data_fifo_w8_d128_utilization_synth.rpt -pb axis_data_fifo_w8_d128_utilization_synth.pb
| Design : axis_data_fifo_w8_d128
| Device : xc7z010clg400-2
| Device : xc7z020clg400-2
| Speed File : -2
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------------------------
@@ -31,14 +31,14 @@ Table of Contents
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 47 | 0 | 0 | 17600 | 0.27 |
| LUT as Logic | 47 | 0 | 0 | 17600 | 0.27 |
| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 |
| Slice Registers | 45 | 0 | 0 | 35200 | 0.13 |
| Register as Flip Flop | 45 | 0 | 0 | 35200 | 0.13 |
| Register as Latch | 0 | 0 | 0 | 35200 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 |
| Slice LUTs* | 47 | 0 | 0 | 53200 | 0.09 |
| LUT as Logic | 47 | 0 | 0 | 53200 | 0.09 |
| LUT as Memory | 0 | 0 | 0 | 17400 | 0.00 |
| Slice Registers | 45 | 0 | 0 | 106400 | 0.04 |
| Register as Flip Flop | 45 | 0 | 0 | 106400 | 0.04 |
| Register as Latch | 0 | 0 | 0 | 106400 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 26600 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 13300 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
@@ -69,9 +69,9 @@ Warning! LUT value is adjusted to account for LUT combining.
+-------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0.5 | 0 | 0 | 60 | 0.83 |
| RAMB36/FIFO* | 0 | 0 | 0 | 60 | 0.00 |
| RAMB18 | 1 | 0 | 0 | 120 | 0.83 |
| Block RAM Tile | 0.5 | 0 | 0 | 140 | 0.36 |
| RAMB36/FIFO* | 0 | 0 | 0 | 140 | 0.00 |
| RAMB18 | 1 | 0 | 0 | 280 | 0.36 |
| RAMB18E1 only | 1 | | | | |
+-------------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -83,7 +83,7 @@ Warning! LUT value is adjusted to account for LUT combining.
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 80 | 0.00 |
| DSPs | 0 | 0 | 0 | 220 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
@@ -93,20 +93,20 @@ Warning! LUT value is adjusted to account for LUT combining.
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 100 | 0.00 |
| Bonded IOB | 0 | 0 | 0 | 125 | 0.00 |
| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 96 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 100 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 100 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 4 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 121 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 125 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 125 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
@@ -117,12 +117,12 @@ Warning! LUT value is adjusted to account for LUT combining.
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
| BUFIO | 0 | 0 | 0 | 8 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 48 | 0.00 |
| BUFR | 0 | 0 | 0 | 8 | 0.00 |
| BUFIO | 0 | 0 | 0 | 16 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 8 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 0 | 16 | 0.00 |
+------------+------+-------+------------+-----------+-------+
c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc
+4 -4
View File
@@ -1,16 +1,16 @@
# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.
# IP: d:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.xci
# IP: D:/Project/A64/pl/a64_v0/c64_pro.srcs/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.xci
# IP: The module: 'axis_data_fifo_w8_d128' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc
# XDC: d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'axis_data_fifo_w8_d128'. Do not add the DONT_TOUCH constraint.
set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# IP: d:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.xci
# IP: D:/Project/A64/pl/a64_v0/c64_pro.srcs/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.xci
# IP: The module: 'axis_data_fifo_w8_d128' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc
# XDC: d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'axis_data_fifo_w8_d128'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
c64_pro.runs/axis_data_fifo_w8_d128_synth_1/gen_run.xml
+1 -1
View File
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="axis_data_fifo_w8_d128_synth_1" LaunchPart="xc7z010clg400-2" LaunchTime="1711684713">
<GenRun Id="axis_data_fifo_w8_d128_synth_1" LaunchPart="xc7z020clg400-2" LaunchTime="1761656301">
<File Type="PA-TCL" Name="axis_data_fifo_w8_d128.tcl"/>
<File Type="REPORTS-TCL" Name="axis_data_fifo_w8_d128_reports.tcl"/>
<File Type="RDS-RDS" Name="axis_data_fifo_w8_d128.vds"/>
c64_pro.runs/axis_data_fifo_w8_d128_synth_1/runme.log
+55 -55
View File
@@ -12,27 +12,27 @@
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source axis_data_fifo_w8_d128.tcl -notrace
create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1385.828 ; gain = 160.668
create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1467.398 ; gain = 161.281
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: axis_data_fifo_w8_d128
Command: synth_design -top axis_data_fifo_w8_d128 -part xc7z010clg400-2 -incremental_mode off -mode out_of_context
Command: synth_design -top axis_data_fifo_w8_d128 -part xc7z020clg400-2 -incremental_mode off -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Device 21-403] Loading part xc7z010clg400-2
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 27696
INFO: [Synth 8-7075] Helper process launched with PID 42852
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 2211.453 ; gain = 409.789
Starting RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2320.645 ; gain = 408.867
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_w8_d128' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/synth/axis_data_fifo_w8_d128.v:53]
INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_v2_0_10_top' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_data_fifo_v2_0_vl_rfs.v:54]
INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_aclken_converter_wrapper' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:599]
INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:809]
INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:809]
INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:991]
INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:991]
INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_aclken_converter_wrapper' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:599]
INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_w8_d128' [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/synth/axis_data_fifo_w8_d128.v:53]
INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_v2_0_10_top' [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_data_fifo_v2_0_vl_rfs.v:54]
INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_aclken_converter_wrapper' [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:599]
INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector' [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:809]
INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector' (0#1) [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:809]
INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis' [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:991]
INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis' (0#1) [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:991]
INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_aclken_converter_wrapper' (0#1) [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_infrastructure_v1_1_vl_rfs.v:599]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_axis' [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2349]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1058]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (0#1) [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1058]
@@ -57,8 +57,8 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [C:/
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (0#1) [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1859]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (0#1) [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:55]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_axis' (0#1) [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2349]
INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_v2_0_10_top' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_data_fifo_v2_0_vl_rfs.v:54]
INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_w8_d128' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/synth/axis_data_fifo_w8_d128.v:53]
INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_v2_0_10_top' (0#1) [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/hdl/axis_data_fifo_v2_0_vl_rfs.v:54]
INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_w8_d128' (0#1) [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/synth/axis_data_fifo_w8_d128.v:53]
WARNING: [Synth 8-6014] Unused sequential element gen_rd_b.gen_doutb_pipe.enb_pipe_reg[0] was removed. [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:3071]
WARNING: [Synth 8-6014] Unused sequential element gdvld.data_valid_std_reg was removed. [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:537]
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1391]
@@ -92,55 +92,55 @@ WARNING: [Synth 8-7129] Port injectdbiterrb in module xpm_memory_base is either
WARNING: [Synth 8-7129] Port m_aclk in module xpm_fifo_axis is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axis_aclk in module axis_data_fifo_v2_0_10_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 2310.840 ; gain = 509.176
Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 2418.816 ; gain = 507.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 2328.754 ; gain = 527.090
Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 2436.738 ; gain = 524.961
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 2328.754 ; gain = 527.090
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 2436.738 ; gain = 524.961
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2328.754 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2436.738 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc] for cell 'inst'
Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc] for cell 'inst'
Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc]
Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc]
Parsing XDC File [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc] for cell 'inst'
Finished Parsing XDC File [d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc] for cell 'inst'
Parsing XDC File [D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc]
Finished Parsing XDC File [D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/axis_data_fifo_w8_d128_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/axis_data_fifo_w8_d128_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
INFO: [Project 1-1714] 2 XPM XDC files have been applied to the design.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2441.469 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2549.336 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 2441.469 ; gain = 0.000
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 2549.355 ; gain = 0.020
INFO: [Designutils 20-5008] Incremental synthesis strategy off
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Constraint Validation : Time (s): cpu = 00:00:26 ; elapsed = 00:00:35 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z010clg400-2
Loading part: xc7z020clg400-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:26 ; elapsed = 00:00:35 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc, line 9).
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/dont_touch.xdc, line 9).
Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst /\gaxis_rst_sync.xpm_cdc_sync_rst_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst . (constraint file auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:35 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base'
---------------------------------------------------------------------------------------------------
@@ -153,7 +153,7 @@ INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_re
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
@@ -185,8 +185,8 @@ Finished RTL Component Statistics
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 80 (col length:40)
BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
@@ -225,7 +225,7 @@ WARNING: [Synth 8-7129] Port s_axis_tuser[0] in module axis_data_fifo_v2_0_10_to
WARNING: [Synth 8-7129] Port m_axis_aclk in module axis_data_fifo_v2_0_10_top is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axis_aclken in module axis_data_fifo_v2_0_10_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:19 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
@@ -246,13 +246,13 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 2549.355 ; gain = 637.578
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Timing Optimization : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 2549.355 ; gain = 637.578
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Start ROM, RAM, DSP, Shift Register and Retiming Reporting
@@ -272,7 +272,7 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
Start Technology Mapping
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---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Technology Mapping : Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2549.355 ; gain = 637.578
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Start IO Insertion
@@ -290,37 +290,37 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
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---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished IO Insertion : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
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Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Renaming Generated Instances : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
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Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
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Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Renaming Generated Ports : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Handling Custom Attributes : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
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Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Renaming Generated Nets : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -347,18 +347,18 @@ Report Cell Usage:
|9 |FDSE | 8|
+------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2441.469 ; gain = 639.805
Finished Writing Synthesis Report : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 31 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 2441.469 ; gain = 527.090
Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:30 . Memory (MB): peak = 2441.469 ; gain = 639.805
Synthesis Optimization Runtime : Time (s): cpu = 00:00:33 ; elapsed = 00:00:56 . Memory (MB): peak = 2549.355 ; gain = 524.961
Synthesis Optimization Complete : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2549.355 ; gain = 637.578
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2441.469 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2549.355 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2441.469 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2549.355 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
@@ -366,10 +366,10 @@ Synth Design complete | Checksum: 3e2929b0
INFO: [Common 17-83] Releasing license: Synthesis
54 Infos, 63 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:42 . Memory (MB): peak = 2441.469 ; gain = 1016.520
INFO: [Common 17-1381] The checkpoint 'D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP axis_data_fifo_w8_d128, cache-ID = 2d33c11f77ef32b5
synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:13 . Memory (MB): peak = 2549.355 ; gain = 1043.230
INFO: [Common 17-1381] The checkpoint 'D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP axis_data_fifo_w8_d128, cache-ID = 53ac5cb930f6d39d
INFO: [Coretcl 2-1174] Renamed 11 cell refs.
INFO: [Common 17-1381] The checkpoint 'D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp' has been generated.
INFO: [Common 17-1381] The checkpoint 'D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file axis_data_fifo_w8_d128_utilization_synth.rpt -pb axis_data_fifo_w8_d128_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Mar 29 11:59:39 2024...
INFO: [Common 17-206] Exiting Vivado at Tue Oct 28 21:00:59 2025...
c64_pro.runs/axis_data_fifo_w8_d128_synth_1/runme.sh
+1 -1
View File
@@ -25,7 +25,7 @@ else
fi
export LD_LIBRARY_PATH
HD_PWD='D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1'
HD_PWD='D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1'
cd "$HD_PWD"
HD_LOG=runme.log
c64_pro.runs/axis_data_fifo_w8_d128_synth_1/vivado.jou
+6 -6
View File
@@ -3,12 +3,12 @@
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Fri Mar 29 11:58:36 2024
# Process ID: 45500
# Current directory: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1
# Start of session at: Tue Oct 28 20:59:13 2025
# Process ID: 49460
# Current directory: D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1
# Command line: vivado.exe -log axis_data_fifo_w8_d128.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source axis_data_fifo_w8_d128.tcl
# Log file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.vds
# Journal file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/axis_data_fifo_w8_d128_synth_1\vivado.jou
# Running On: 840-5CG14025H4, OS: Windows, CPU Frequency: 2803 MHz, CPU Physical cores: 4, Host memory: 34024 MB
# Log file: D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1/axis_data_fifo_w8_d128.vds
# Journal file: D:/Project/A64/pl/a64_v0/c64_pro.runs/axis_data_fifo_w8_d128_synth_1\vivado.jou
# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
#-----------------------------------------------------------
source axis_data_fifo_w8_d128.tcl -notrace
c64_pro.runs/axis_data_fifo_w8_d128_synth_1/vivado.pb
BIN
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