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c64_pro.ip_user_files/sim_scripts/fifo_generator_0/activehdl/README.txt
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################################################################################
# Vivado (TM) v2023.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Wed Oct 22 13:40:22 +0800 2025
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./fifo_generator_0.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './fifo_generator_0.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/activehdl/compile.do
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transcript off
onbreak {quit -force}
onerror {quit -force}
transcript on
vlib work
vmap -link {D:/Project/A64/pl/a64_v0/c64_pro.cache/compile_simlib/activehdl}
vlib activehdl/xilinx_vip
vlib activehdl/xpm
vlib activehdl/fifo_generator_v13_2_8
vlib activehdl/xil_defaultlib
vlog -work xilinx_vip -sv2k12 "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -l xilinx_vip -l xpm -l fifo_generator_v13_2_8 -l xil_defaultlib \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv" \
vlog -work xpm -sv2k12 "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -l xilinx_vip -l xpm -l fifo_generator_v13_2_8 -l xil_defaultlib \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work fifo_generator_v13_2_8 -v2k5 "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -l xilinx_vip -l xpm -l fifo_generator_v13_2_8 -l xil_defaultlib \
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_2_8 -93 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
vlog -work fifo_generator_v13_2_8 -v2k5 "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -l xilinx_vip -l xpm -l fifo_generator_v13_2_8 -l xil_defaultlib \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
vlog -work xil_defaultlib -v2k5 "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -l xilinx_vip -l xpm -l fifo_generator_v13_2_8 -l xil_defaultlib \
"../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v" \
vlog -work xil_defaultlib \
"glbl.v"
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/activehdl/fifo_generator_0.sh
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#!/bin/bash -f
#**********************************************************************************************************
# Vivado (TM) v2023.1 (64-bit)
#
# Script generated by Vivado on Wed Oct 22 13:40:22 +0800 2025
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
#
# Tool Version Limit: 2023.05
#
# Filename : fifo_generator_0.sh
# Simulator : Aldec Active-HDL Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : fifo_generator_0.sh
# fifo_generator_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# fifo_generator_0.sh [-reset_run]
# fifo_generator_0.sh [-reset_log]
# fifo_generator_0.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
# Prerequisite : Before running export_simulation, you must first compile the Xilinx simulation library
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
# switch with the directory path where the library is created while generating the script
# with export_simulation.
#
# Alternatively, you can set the library path by setting the following project property:-
#
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
#
# You can also point to the simulation library by either setting the 'lib_map_path' global
# variable in this script or specify it with the '-lib_map_path' switch while executing this
# script (type 'fifo_generator_0.sh -help' for more information).
#
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
# sources, then the library path MUST be specified upfront when calling export_simulation.
#
# For more information, refer 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#**********************************************************************************************************
# script info
echo -e "fifo_generator_0.sh - Script generated by export_simulation (Vivado v2023.1 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
runvsimsa -do "do {compile.do}" 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
runvsimsa -l simulate.log -do "do {simulate.do}"
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous design library mappings
true
else
# map simulator index file
map_setup_file
fi
}
# map library.cfg file
map_setup_file()
{
file="library.cfg"
if [[ ($lib_map_path == "") ]]; then
lib_map_path="D:/Project/A64/pl/a64_v0/c64_pro.cache/compile_simlib/activehdl"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
vmap -link $lib_map_path
else
echo -e "ERROR: File does not exist '$src_file'\n"
exit 1
fi
fi
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: fifo_generator_0.sh [-help]\n\
Usage: fifo_generator_0.sh [-step]\n\
Usage: fifo_generator_0.sh [-lib_map_path]\n\
Usage: fifo_generator_0.sh [-reset_run]\n\
Usage: fifo_generator_0.sh [-reset_log]\n\
Usage: fifo_generator_0.sh [-keep_index]\n\
Usage: fifo_generator_0.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (compile, simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/activehdl/fifo_generator_0.udo
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c64_pro.ip_user_files/sim_scripts/fifo_generator_0/activehdl/file_info.txt
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axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
axi_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv,
axi4stream_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
axi_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv,
clk_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv,
rst_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv,
xpm_cdc.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_fifo.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
xpm_memory.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_8,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_8,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_8,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
fifo_generator_0.v,verilog,xil_defaultlib,../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/activehdl/glbl.v
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/activehdl/simulate.do
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transcript off
onbreak {quit -force}
onerror {quit -force}
transcript on
asim +access +r +m+fifo_generator_0 -L xilinx_vip -L xpm -L fifo_generator_v13_2_8 -L xil_defaultlib -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fifo_generator_0 xil_defaultlib.glbl
do {fifo_generator_0.udo}
run 1000ns
endsim
quit -force
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/modelsim/README.txt
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################################################################################
# Vivado (TM) v2023.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Wed Oct 22 13:40:22 +0800 2025
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./fifo_generator_0.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './fifo_generator_0.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/modelsim/compile.do
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vlib modelsim_lib/work
vlib modelsim_lib/msim
vlib modelsim_lib/msim/xilinx_vip
vlib modelsim_lib/msim/xpm
vlib modelsim_lib/msim/fifo_generator_v13_2_8
vlib modelsim_lib/msim/xil_defaultlib
vmap xilinx_vip modelsim_lib/msim/xilinx_vip
vmap xpm modelsim_lib/msim/xpm
vmap fifo_generator_v13_2_8 modelsim_lib/msim/fifo_generator_v13_2_8
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
vlog -work xilinx_vip -incr -mfcu -sv -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv" \
vlog -work xpm -incr -mfcu -sv -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work fifo_generator_v13_2_8 -incr -mfcu "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_2_8 -93 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
vlog -work fifo_generator_v13_2_8 -incr -mfcu "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
vlog -work xil_defaultlib -incr -mfcu "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v" \
vlog -work xil_defaultlib \
"glbl.v"
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/modelsim/fifo_generator_0.sh
+289
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#!/bin/bash -f
#**********************************************************************************************************
# Vivado (TM) v2023.1 (64-bit)
#
# Script generated by Vivado on Wed Oct 22 13:40:22 +0800 2025
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
#
# Tool Version Limit: 2023.05
#
# Filename : fifo_generator_0.sh
# Simulator : Siemens ModelSim Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : fifo_generator_0.sh
# fifo_generator_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# fifo_generator_0.sh [-reset_run]
# fifo_generator_0.sh [-reset_log]
# fifo_generator_0.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
# Prerequisite : Before running export_simulation, you must first compile the Xilinx simulation library
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
# switch with the directory path where the library is created while generating the script
# with export_simulation.
#
# Alternatively, you can set the library path by setting the following project property:-
#
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
#
# You can also point to the simulation library by either setting the 'lib_map_path' global
# variable in this script or specify it with the '-lib_map_path' switch while executing this
# script (type 'fifo_generator_0.sh -help' for more information).
#
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
# sources, then the library path MUST be specified upfront when calling export_simulation.
#
# For more information, refer 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#**********************************************************************************************************
# catch pipeline exit status
set -Eeuo pipefail
# script info
echo -e "fifo_generator_0.sh - Script generated by export_simulation (Vivado v2023.1 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
vsim -c -do "do {simulate.do}" -l simulate.log
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous simulator index file
true
else
# copy simulator index file to current directory
copy_setup_file
fi
if [[ ($lib_map_path != "") ]]; then
ref_lib_dir=$lib_map_path
fi
if [[ ($b_keep_index == 1) ]]; then
# do not recreate design library directories
true
else
# create design library directories
create_lib_dir
fi
}
# copy modelsim.ini file
copy_setup_file()
{
file="modelsim.ini"
if [[ ($lib_map_path == "") ]]; then
lib_map_path="D:/Project/A64/pl/a64_v0/c64_pro.cache/compile_simlib/modelsim"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
cp $src_file .
else
echo -e "ERROR: File does not exist '$src_file'\n"
exit 1
fi
fi
}
# create design library directory
create_lib_dir()
{
lib_dir="modelsim_lib"
if [[ -e $lib_dir ]]; then
rm -rf $lib_dir
fi
mkdir $lib_dir
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(compile.log elaborate.log simulate.log)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: fifo_generator_0.sh [-help]\n\
Usage: fifo_generator_0.sh [-step]\n\
Usage: fifo_generator_0.sh [-lib_map_path]\n\
Usage: fifo_generator_0.sh [-reset_run]\n\
Usage: fifo_generator_0.sh [-reset_log]\n\
Usage: fifo_generator_0.sh [-keep_index]\n\
Usage: fifo_generator_0.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (compile, simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/modelsim/fifo_generator_0.udo
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c64_pro.ip_user_files/sim_scripts/fifo_generator_0/modelsim/file_info.txt
+18
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axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
axi_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv,
axi4stream_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
axi_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv,
clk_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv,
rst_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv,
xpm_cdc.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_fifo.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
xpm_memory.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_8,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_8,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_8,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
fifo_generator_0.v,verilog,xil_defaultlib,../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/modelsim/glbl.v
+84
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/modelsim/simulate.do
+19
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@@ -0,0 +1,19 @@
onbreak {quit -f}
onerror {quit -f}
vsim -voptargs="+acc" -L xilinx_vip -L xpm -L fifo_generator_v13_2_8 -L xil_defaultlib -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.fifo_generator_0 xil_defaultlib.glbl
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do {wave.do}
view wave
view structure
view signals
do {fifo_generator_0.udo}
run 1000ns
quit -force
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/modelsim/wave.do
+2
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@@ -0,0 +1,2 @@
add wave *
add wave /glbl/GSR
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/questa/README.txt
+50
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@@ -0,0 +1,50 @@
################################################################################
# Vivado (TM) v2023.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Wed Oct 22 13:40:22 +0800 2025
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./fifo_generator_0.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './fifo_generator_0.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/questa/compile.do
+47
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@@ -0,0 +1,47 @@
vlib questa_lib/work
vlib questa_lib/msim
vlib questa_lib/msim/xilinx_vip
vlib questa_lib/msim/xpm
vlib questa_lib/msim/fifo_generator_v13_2_8
vlib questa_lib/msim/xil_defaultlib
vmap xilinx_vip questa_lib/msim/xilinx_vip
vmap xpm questa_lib/msim/xpm
vmap fifo_generator_v13_2_8 questa_lib/msim/fifo_generator_v13_2_8
vmap xil_defaultlib questa_lib/msim/xil_defaultlib
vlog -work xilinx_vip -incr -mfcu -sv -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv" \
vlog -work xpm -incr -mfcu -sv -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work fifo_generator_v13_2_8 -incr -mfcu "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_2_8 -93 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
vlog -work fifo_generator_v13_2_8 -incr -mfcu "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
vlog -work xil_defaultlib -incr -mfcu "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v" \
vlog -work xil_defaultlib \
"glbl.v"
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/questa/elaborate.do
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vopt +acc=npr -l elaborate.log +acc=npr -suppress 10016 -L xil_defaultlib -L xilinx_vip -L xpm -L fifo_generator_v13_2_8 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.fifo_generator_0 xil_defaultlib.glbl -o fifo_generator_0_opt
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/questa/fifo_generator_0.sh
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#!/bin/bash -f
#**********************************************************************************************************
# Vivado (TM) v2023.1 (64-bit)
#
# Script generated by Vivado on Wed Oct 22 13:40:22 +0800 2025
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
#
# Tool Version Limit: 2023.05
#
# Filename : fifo_generator_0.sh
# Simulator : Siemens Questa Advanced Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : fifo_generator_0.sh
# fifo_generator_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# fifo_generator_0.sh [-reset_run]
# fifo_generator_0.sh [-reset_log]
# fifo_generator_0.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
# Prerequisite : Before running export_simulation, you must first compile the Xilinx simulation library
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
# switch with the directory path where the library is created while generating the script
# with export_simulation.
#
# Alternatively, you can set the library path by setting the following project property:-
#
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
#
# You can also point to the simulation library by either setting the 'lib_map_path' global
# variable in this script or specify it with the '-lib_map_path' switch while executing this
# script (type 'fifo_generator_0.sh -help' for more information).
#
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
# sources, then the library path MUST be specified upfront when calling export_simulation.
#
# For more information, refer 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#**********************************************************************************************************
# catch pipeline exit status
set -Eeuo pipefail
# script info
echo -e "fifo_generator_0.sh - Script generated by export_simulation (Vivado v2023.1 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"elaborate" )
elaborate
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
elaborate
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <elaborate>
elaborate()
{
source elaborate.do 2>&1 | tee elaborate.log
}
# RUN_STEP: <simulate>
simulate()
{
vsim -c -do "do {simulate.do}" -l simulate.log
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous simulator index file
true
else
# copy simulator index file to current directory
copy_setup_file
fi
if [[ ($lib_map_path != "") ]]; then
ref_lib_dir=$lib_map_path
fi
if [[ ($b_keep_index == 1) ]]; then
# do not recreate design library directories
true
else
# create design library directories
create_lib_dir
fi
}
# copy modelsim.ini file
copy_setup_file()
{
file="modelsim.ini"
if [[ ($lib_map_path == "") ]]; then
lib_map_path="D:/Project/A64/pl/a64_v0/c64_pro.cache/compile_simlib/questa"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
cp $src_file .
else
echo -e "ERROR: File does not exist '$src_file'\n"
exit 1
fi
fi
}
# create design library directory
create_lib_dir()
{
lib_dir="questa_lib"
if [[ -e $lib_dir ]]; then
rm -rf $lib_dir
fi
mkdir $lib_dir
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(compile.log elaborate.log simulate.log)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: fifo_generator_0.sh [-help]\n\
Usage: fifo_generator_0.sh [-step]\n\
Usage: fifo_generator_0.sh [-lib_map_path]\n\
Usage: fifo_generator_0.sh [-reset_run]\n\
Usage: fifo_generator_0.sh [-reset_log]\n\
Usage: fifo_generator_0.sh [-keep_index]\n\
Usage: fifo_generator_0.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (compile, elaborate, simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/questa/fifo_generator_0.udo
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c64_pro.ip_user_files/sim_scripts/fifo_generator_0/questa/file_info.txt
+18
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axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
axi_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv,
axi4stream_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
axi_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv,
clk_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv,
rst_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv,
xpm_cdc.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_fifo.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
xpm_memory.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_8,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_8,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_8,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
fifo_generator_0.v,verilog,xil_defaultlib,../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/questa/glbl.v
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/questa/simulate.do
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onbreak {quit -f}
onerror {quit -f}
vsim -lib xil_defaultlib fifo_generator_0_opt
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do {wave.do}
view wave
view structure
view signals
do {fifo_generator_0.udo}
run 1000ns
quit -force
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/questa/wave.do
+2
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add wave *
add wave /glbl/GSR
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/riviera/README.txt
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################################################################################
# Vivado (TM) v2023.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Wed Oct 22 13:40:22 +0800 2025
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./fifo_generator_0.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './fifo_generator_0.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/riviera/compile.do
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transcript off
onbreak {quit -force}
onerror {quit -force}
transcript on
vlib work
vmap -link {D:/Project/A64/pl/a64_v0/c64_pro.cache/compile_simlib/riviera}
vlib riviera/xilinx_vip
vlib riviera/xpm
vlib riviera/fifo_generator_v13_2_8
vlib riviera/xil_defaultlib
vlog -work xilinx_vip -incr -l axi_vip_v1_1_14 -l smartconnect_v1_0 -l processing_system7_vip_v1_0_16 "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -l xilinx_vip -l xpm -l fifo_generator_v13_2_8 -l xil_defaultlib \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv" \
vlog -work xpm -incr -l axi_vip_v1_1_14 -l smartconnect_v1_0 -l processing_system7_vip_v1_0_16 "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -l xilinx_vip -l xpm -l fifo_generator_v13_2_8 -l xil_defaultlib \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 -incr \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work fifo_generator_v13_2_8 -incr -v2k5 "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -l xilinx_vip -l xpm -l fifo_generator_v13_2_8 -l xil_defaultlib \
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_2_8 -93 -incr \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
vlog -work fifo_generator_v13_2_8 -incr -v2k5 "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -l xilinx_vip -l xpm -l fifo_generator_v13_2_8 -l xil_defaultlib \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
vlog -work xil_defaultlib -incr -v2k5 "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -l xilinx_vip -l xpm -l fifo_generator_v13_2_8 -l xil_defaultlib \
"../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v" \
vlog -work xil_defaultlib \
"glbl.v"
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/riviera/fifo_generator_0.sh
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#!/bin/bash -f
#**********************************************************************************************************
# Vivado (TM) v2023.1 (64-bit)
#
# Script generated by Vivado on Wed Oct 22 13:40:22 +0800 2025
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
#
# Tool Version Limit: 2023.05
#
# Filename : fifo_generator_0.sh
# Simulator : Aldec Riviera-PRO Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : fifo_generator_0.sh
# fifo_generator_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# fifo_generator_0.sh [-reset_run]
# fifo_generator_0.sh [-reset_log]
# fifo_generator_0.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
# Prerequisite : Before running export_simulation, you must first compile the Xilinx simulation library
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
# switch with the directory path where the library is created while generating the script
# with export_simulation.
#
# Alternatively, you can set the library path by setting the following project property:-
#
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
#
# You can also point to the simulation library by either setting the 'lib_map_path' global
# variable in this script or specify it with the '-lib_map_path' switch while executing this
# script (type 'fifo_generator_0.sh -help' for more information).
#
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
# sources, then the library path MUST be specified upfront when calling export_simulation.
#
# For more information, refer 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#**********************************************************************************************************
# catch pipeline exit status
set -Eeuo pipefail
# script info
echo -e "fifo_generator_0.sh - Script generated by export_simulation (Vivado v2023.1 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
runvsimsa -do "do {compile.do}" 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
runvsimsa -l simulate.log -do "do {simulate.do}"
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous design library mappings
true
else
# map simulator index file
map_setup_file
fi
}
# map library.cfg file
map_setup_file()
{
file="library.cfg"
if [[ ($lib_map_path == "") ]]; then
lib_map_path="D:/Project/A64/pl/a64_v0/c64_pro.cache/compile_simlib/riviera"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
vmap -link $lib_map_path
else
echo -e "ERROR: File does not exist '$src_file'\n"
exit 1
fi
fi
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: fifo_generator_0.sh [-help]\n\
Usage: fifo_generator_0.sh [-step]\n\
Usage: fifo_generator_0.sh [-lib_map_path]\n\
Usage: fifo_generator_0.sh [-reset_run]\n\
Usage: fifo_generator_0.sh [-reset_log]\n\
Usage: fifo_generator_0.sh [-keep_index]\n\
Usage: fifo_generator_0.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (compile, simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/riviera/fifo_generator_0.udo
View File
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/riviera/file_info.txt
+18
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@@ -0,0 +1,18 @@
axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
axi_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv,
axi4stream_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
axi_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv,
clk_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv,
rst_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv,
xpm_cdc.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_fifo.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
xpm_memory.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_8,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_8,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_8,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
fifo_generator_0.v,verilog,xil_defaultlib,../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/riviera/glbl.v
+84
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/riviera/simulate.do
+14
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transcript off
onbreak {quit -force}
onerror {quit -force}
transcript on
asim +access +r +m+fifo_generator_0 -L xilinx_vip -L xpm -L fifo_generator_v13_2_8 -L xil_defaultlib -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fifo_generator_0 xil_defaultlib.glbl
do {fifo_generator_0.udo}
run 1000ns
endsim
quit -force
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/vcs/README.txt
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################################################################################
# Vivado (TM) v2023.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Wed Oct 22 13:40:22 +0800 2025
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./fifo_generator_0.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './fifo_generator_0.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/vcs/fifo_generator_0.sh
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#!/bin/bash -f
#**********************************************************************************************************
# Vivado (TM) v2023.1 (64-bit)
#
# Script generated by Vivado on Wed Oct 22 13:40:22 +0800 2025
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
#
# Tool Version Limit: 2023.05
#
# Filename : fifo_generator_0.sh
# Simulator : Synopsys Verilog Compiler Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : fifo_generator_0.sh
# fifo_generator_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# fifo_generator_0.sh [-reset_run]
# fifo_generator_0.sh [-reset_log]
# fifo_generator_0.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
# Prerequisite : Before running export_simulation, you must first compile the Xilinx simulation library
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
# switch with the directory path where the library is created while generating the script
# with export_simulation.
#
# Alternatively, you can set the library path by setting the following project property:-
#
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
#
# You can also point to the simulation library by either setting the 'lib_map_path' global
# variable in this script or specify it with the '-lib_map_path' switch while executing this
# script (type 'fifo_generator_0.sh -help' for more information).
#
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
# sources, then the library path MUST be specified upfront when calling export_simulation.
#
# For more information, refer 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#**********************************************************************************************************
# catch pipeline exit status
set -Eeuo pipefail
# set vhdlan compile options
vhdlan_opts="-full64 -l .tmp_log"
# set vlogan compile options
vlogan_opts="-full64 -l .tmp_log"
# set vcs elaboration options
vcs_elab_opts="-full64 -t ps -licqueue -l elaborate.log"
# set vcs simulation options
vcs_sim_opts="-ucli -licqueue -l simulate.log "
# set design libraries
design_libs=(xilinx_vip xpm fifo_generator_v13_2_8 xil_defaultlib)
# simulation root library directory
sim_lib_dir="vcs_lib"
# script info
echo -e "fifo_generator_0.sh - Script generated by export_simulation (Vivado v2023.1 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"elaborate" )
elaborate
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
elaborate
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv" \
2>&1 | tee compile.log; cat .tmp_log > vlogan.log 2>/dev/null
vlogan -work xpm $vlogan_opts -sverilog +incdir+"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vhdlan -work xpm $vhdlan_opts \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd" \
2>&1 | tee -a compile.log; cat .tmp_log > vhdlan.log 2>/dev/null
vlogan -work fifo_generator_v13_2_8 $vlogan_opts +v2k +incdir+"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vhdlan -work fifo_generator_v13_2_8 $vhdlan_opts \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
2>&1 | tee -a compile.log; cat .tmp_log >> vhdlan.log 2>/dev/null
vlogan -work fifo_generator_v13_2_8 $vlogan_opts +v2k +incdir+"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vlogan -work xil_defaultlib $vlogan_opts +v2k \
glbl.v \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
}
# RUN_STEP: <elaborate>
elaborate()
{
vcs $vcs_elab_opts xil_defaultlib.fifo_generator_0 xil_defaultlib.glbl -o fifo_generator_0_simv
}
# RUN_STEP: <simulate>
simulate()
{
./fifo_generator_0_simv $vcs_sim_opts -do simulate.do
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous design library mappings
true
else
# define design library mappings
create_lib_mappings
fi
if [[ ($b_keep_index == 1) ]]; then
# do not recreate design library directories
true
else
# create design library directories
create_lib_dir
fi
}
# define design library mappings
create_lib_mappings()
{
file="synopsys_sim.setup"
if [[ -e $file ]]; then
if [[ ($lib_map_path == "") ]]; then
return
else
rm -rf $file
fi
fi
touch $file
for (( i=0; i<${#design_libs[*]}; i++ )); do
lib="${design_libs[i]}"
mapping="$lib:$sim_lib_dir/$lib"
echo $mapping >> $file
done
if [[ ($lib_map_path != "") ]]; then
incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
echo $incl_ref >> $file
fi
}
# create design library directory
create_lib_dir()
{
if [[ -e $sim_lib_dir ]]; then
rm -rf $sim_lib_dir
fi
for (( i=0; i<${#design_libs[*]}; i++ )); do
lib="${design_libs[i]}"
lib_dir="$sim_lib_dir/$lib"
if [[ ! -e $lib_dir ]]; then
mkdir -p $lib_dir
fi
done
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(ucli.key fifo_generator_0_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .tmp_log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log lib_sc.so 64 AN.DB csrc fifo_generator_0_simv.daidir vcs_lib c.obj)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(vlogan.log vhdlan.log compile.log elaborate.log simulate.log .tmp_log)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: fifo_generator_0.sh [-help]\n\
Usage: fifo_generator_0.sh [-step]\n\
Usage: fifo_generator_0.sh [-lib_map_path]\n\
Usage: fifo_generator_0.sh [-reset_run]\n\
Usage: fifo_generator_0.sh [-reset_log]\n\
Usage: fifo_generator_0.sh [-keep_index]\n\
Usage: fifo_generator_0.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (compile, elaborate, simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/vcs/file_info.txt
+18
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@@ -0,0 +1,18 @@
axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
axi_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv,
axi4stream_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
axi_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv,
clk_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv,
rst_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv,
xpm_cdc.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_fifo.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
xpm_memory.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_8,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_8,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_8,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
fifo_generator_0.v,verilog,xil_defaultlib,../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/vcs/glbl.v
+84
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@@ -0,0 +1,84 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/vcs/simulate.do
+2
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@@ -0,0 +1,2 @@
run
quit
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xcelium/README.txt
+50
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@@ -0,0 +1,50 @@
################################################################################
# Vivado (TM) v2023.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Wed Oct 22 13:40:22 +0800 2025
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./fifo_generator_0.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './fifo_generator_0.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xcelium/fifo_generator_0.sh
+372
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@@ -0,0 +1,372 @@
#!/bin/bash -f
#**********************************************************************************************************
# Vivado (TM) v2023.1 (64-bit)
#
# Script generated by Vivado on Wed Oct 22 13:40:22 +0800 2025
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
#
# Tool Version Limit: 2023.05
#
# Filename : fifo_generator_0.sh
# Simulator : Cadence Xcelium Parallel Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : fifo_generator_0.sh
# fifo_generator_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# fifo_generator_0.sh [-reset_run]
# fifo_generator_0.sh [-reset_log]
# fifo_generator_0.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
# Prerequisite : Before running export_simulation, you must first compile the Xilinx simulation library
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
# switch with the directory path where the library is created while generating the script
# with export_simulation.
#
# Alternatively, you can set the library path by setting the following project property:-
#
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
#
# You can also point to the simulation library by either setting the 'lib_map_path' global
# variable in this script or specify it with the '-lib_map_path' switch while executing this
# script (type 'fifo_generator_0.sh -help' for more information).
#
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
# sources, then the library path MUST be specified upfront when calling export_simulation.
#
# For more information, refer 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#**********************************************************************************************************
# catch pipeline exit status
set -Eeuo pipefail
# set xmvhdl compile options
xmvhdl_opts="-64bit -messages -logfile .tmp_log -update"
# set xmvlog compile options
xmvlog_opts="-64bit -messages -logfile .tmp_log -update"
# set xmelab elaboration options
xmelab_opts="-64bit -relax -access +rwc -namemap_mixgen -messages -logfile elaborate.log"
# set xmsim simulation options
xmsim_opts="-64bit -logfile simulate.log"
# set design libraries for elaboration
design_libs_elab="-libname xilinx_vip -libname xpm -libname fifo_generator_v13_2_8 -libname xil_defaultlib -libname xilinx_vip -libname unisims_ver -libname unimacro_ver -libname secureip"
# set design libraries
design_libs=(simprims_ver xilinx_vip xpm fifo_generator_v13_2_8 xil_defaultlib)
# simulation root library directory
sim_lib_dir="xcelium_lib"
# script info
echo -e "fifo_generator_0.sh - Script generated by export_simulation (Vivado v2023.1 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"elaborate" )
elaborate
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
elaborate
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
xmvlog -work xilinx_vip $xmvlog_opts -sv +incdir+"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv" \
"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv" \
2>&1 | tee compile.log; cat .tmp_log > xmvlog.log 2>/dev/null
xmvlog -work xpm $xmvlog_opts -sv +incdir+"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null
xmvhdl -work xpm $xmvhdl_opts \
"C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd" \
2>&1 | tee -a compile.log; cat .tmp_log > xmvhdl.log 2>/dev/null
xmvlog -work fifo_generator_v13_2_8 $xmvlog_opts +incdir+"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null
xmvhdl -work fifo_generator_v13_2_8 $xmvhdl_opts \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
2>&1 | tee -a compile.log; cat .tmp_log >> xmvhdl.log 2>/dev/null
xmvlog -work fifo_generator_v13_2_8 $xmvlog_opts +incdir+"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null
xmvlog -work xil_defaultlib $xmvlog_opts +incdir+"C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null
xmvlog -work xil_defaultlib $xmvlog_opts \
glbl.v \
2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null
}
# RUN_STEP: <elaborate>
elaborate()
{
xmelab $xmelab_opts $design_libs_elab xil_defaultlib.fifo_generator_0 xil_defaultlib.glbl
}
# RUN_STEP: <simulate>
simulate()
{
xmsim $xmsim_opts xil_defaultlib.fifo_generator_0 -input simulate.do
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous design library mappings
true
else
# define design library mappings
create_lib_mappings
fi
if [[ ($b_keep_index == 1) ]]; then
# do not recreate design library directories
true
else
# create design library directories
create_lib_dir
fi
}
# define design library mappings
create_lib_mappings()
{
file="hdl.var"
touch $file
file="cds.lib"
if [[ -e $file ]]; then
if [[ ($lib_map_path == "") ]]; then
return
else
rm -rf $file
fi
fi
touch $file
if [[ ($lib_map_path != "") ]]; then
incl_ref="INCLUDE $lib_map_path/cds.lib"
echo $incl_ref >> $file
fi
for (( i=0; i<${#design_libs[*]}; i++ )); do
lib="${design_libs[i]}"
mapping="DEFINE $lib $sim_lib_dir/$lib"
echo $mapping >> $file
done
}
# create design library directory
create_lib_dir()
{
if [[ -e $sim_lib_dir ]]; then
rm -rf $sim_lib_dir
fi
for (( i=0; i<${#design_libs[*]}; i++ )); do
lib="${design_libs[i]}"
lib_dir="$sim_lib_dir/$lib"
if [[ ! -e $lib_dir ]]; then
mkdir -p $lib_dir
fi
done
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(xmvlog.log xmvhdl.log xmsc.log compile.log elaborate.log simulate.log diag_report.log xsc_report.log fifo_generator_0_sc.so .tmp_log xcelium_lib waves.shm c.obj)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(xmvlog.log xmvhdl.log xmsc.log compile.log elaborate.log simulate.log diag_report.log xsc_report.log .tmp_log)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: fifo_generator_0.sh [-help]\n\
Usage: fifo_generator_0.sh [-step]\n\
Usage: fifo_generator_0.sh [-lib_map_path]\n\
Usage: fifo_generator_0.sh [-reset_run]\n\
Usage: fifo_generator_0.sh [-reset_log]\n\
Usage: fifo_generator_0.sh [-keep_index]\n\
Usage: fifo_generator_0.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xcelium/file_info.txt
+18
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@@ -0,0 +1,18 @@
axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
axi_vip_pkg.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv,
axi4stream_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
axi_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv,
clk_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv,
rst_vip_if.sv,systemverilog,xilinx_vip,C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv,
xpm_cdc.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_fifo.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
xpm_memory.sv,systemverilog,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_8,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_8,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_8,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
fifo_generator_0.v,verilog,xil_defaultlib,../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xcelium/glbl.v
+84
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xcelium/hdl.var
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c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xcelium/simulate.do
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database -open waves -into waves.shm -default
catch {probe -create -shm -all -variables -depth 1} msg
run
exit
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xsim/README.txt
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@@ -0,0 +1,50 @@
################################################################################
# Vivado (TM) v2023.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Wed Oct 22 13:40:22 +0800 2025
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./fifo_generator_0.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './fifo_generator_0.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xsim/cmd.tcl
+12
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set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns
quit
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xsim/elab.opt
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@@ -0,0 +1 @@
--incr --debug typical --relax --mt 2 -L fifo_generator_v13_2_8 -L xil_defaultlib -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot fifo_generator_0 xil_defaultlib.fifo_generator_0 xil_defaultlib.glbl -log elaborate.log
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xsim/fifo_generator_0.sh
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#!/bin/bash -f
#**********************************************************************************************************
# Vivado (TM) v2023.1 (64-bit)
#
# Script generated by Vivado on Wed Oct 22 13:40:22 +0800 2025
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
#
# Tool Version Limit: 2023.05
#
# Filename : fifo_generator_0.sh
# Simulator : Xilinx Vivado Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : fifo_generator_0.sh
# fifo_generator_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# fifo_generator_0.sh [-reset_run]
# fifo_generator_0.sh [-reset_log]
# fifo_generator_0.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
#**********************************************************************************************************
# catch pipeline exit status
set -Eeuo pipefail
# set xvlog options
xvlog_opts="--incr --relax -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip"
# set xvhdl options
xvhdl_opts="--incr --relax "
# script info
echo -e "fifo_generator_0.sh - Script generated by export_simulation (Vivado v2023.1 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"elaborate" )
elaborate
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
elaborate
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log
}
# RUN_STEP: <elaborate>
elaborate()
{
xelab --incr --debug typical --relax --mt 2 -L fifo_generator_v13_2_8 -L xil_defaultlib -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot fifo_generator_0 xil_defaultlib.fifo_generator_0 xil_defaultlib.glbl -log elaborate.log
}
# RUN_STEP: <simulate>
simulate()
{
xsim fifo_generator_0 -key {Behavioral:sim_1:Functional:fifo_generator_0} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -log simulate.log
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous simulator index file
true
else
# copy simulator index file to current directory
copy_setup_file
fi
if [[ ($lib_map_path != "") ]]; then
ref_lib_dir=$lib_map_path
fi
}
# copy xsim.ini file
copy_setup_file()
{
file="xsim.ini"
if [[ ($lib_map_path == "") ]]; then
lib_map_path="C:/Xilinx/Vivado/2023.1/data/xsim"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
cp $src_file .
else
echo -e "ERROR: File does not exist '$src_file'\n"
exit 1
fi
# map local design libraries to xsim.ini
map_local_libs
fi
}
# map local design libraries
map_local_libs()
{
updated_mappings=()
local_mappings=()
# local design libraries
local_libs=()
if [[ 0 == ${#local_libs[@]} ]]; then
return
fi
file="xsim.ini"
file_backup="xsim.ini.bak"
if [[ -e $file ]]; then
rm -f $file_backup
# create a backup copy of the xsim.ini file
cp $file $file_backup
# read libraries from backup file and search in local library collection
while read -r line
do
IN=$line
# split mapping entry with '=' delimiter to fetch library name and mapping
read lib_name mapping <<<$(IFS="="; echo $IN)
# if local library found, then construct the local mapping and add to local mapping collection
if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
line="$lib_name=xsim.dir/$lib_name"
local_mappings+=("$lib_name")
fi
# add to updated library mapping collection
updated_mappings+=("$line")
done < "$file_backup"
# append local libraries not found originally from xsim.ini
for (( i=0; i<${#local_libs[*]}; i++ )); do
lib_name="${local_libs[i]}"
if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
line="$lib_name=xsim.dir/$lib_name"
updated_mappings+=("$line")
fi
done
# write updated mappings in xsim.ini
rm -f $file
for (( i=0; i<${#updated_mappings[*]}; i++ )); do
lib_name="${updated_mappings[i]}"
echo $lib_name >> $file
done
else
for (( i=0; i<${#local_libs[*]}; i++ )); do
lib_name="${local_libs[i]}"
mapping="$lib_name=xsim.dir/$lib_name"
echo $mapping >> $file
done
fi
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb fifo_generator_0.wdb xsim.dir libdpi.so)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_generator_0.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: fifo_generator_0.sh [-help]\n\
Usage: fifo_generator_0.sh [-step]\n\
Usage: fifo_generator_0.sh [-lib_map_path]\n\
Usage: fifo_generator_0.sh [-reset_run]\n\
Usage: fifo_generator_0.sh [-reset_log]\n\
Usage: fifo_generator_0.sh [-keep_index]\n\
Usage: fifo_generator_0.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (compile, elaborate, simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xsim/file_info.txt
+2
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@@ -0,0 +1,2 @@
fifo_generator_0.v,verilog,xil_defaultlib,../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xsim/glbl.v
+84
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xsim/protoinst_files/bd_6e35.protoinst
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c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xsim/protoinst_files/bd_962a.protoinst
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{
"version": "1.0",
"modules": {
"bd_962a": {
"proto_instances": {
"/m00_exit_pipeline/m00_exit/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr"},
"ARBURST": { "actual": "m_axi_arburst"},
"ARCACHE": { "actual": "m_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARLEN": { "actual": "m_axi_arlen"},
"ARLOCK": { "actual": "m_axi_arlock"},
"ARPROT": { "actual": "m_axi_arprot"},
"ARQOS": { "actual": "m_axi_arqos"},
"ARREADY": { "actual": "m_axi_arready"},
"ARSIZE": { "actual": "m_axi_arsize"},
"ARVALID": { "actual": "m_axi_arvalid"},
"AWADDR": { "actual": "m_axi_awaddr"},
"AWBURST": { "actual": "m_axi_awburst"},
"AWCACHE": { "actual": "m_axi_awcache"},
"AWLEN": { "actual": "m_axi_awlen"},
"AWLOCK": { "actual": "m_axi_awlock"},
"AWPROT": { "actual": "m_axi_awprot"},
"AWQOS": { "actual": "m_axi_awqos"},
"AWREADY": { "actual": "m_axi_awready"},
"AWSIZE": { "actual": "m_axi_awsize"},
"AWVALID": { "actual": "m_axi_awvalid"},
"BREADY": { "actual": "m_axi_bready"},
"BRESP": { "actual": "m_axi_bresp"},
"BVALID": { "actual": "m_axi_bvalid"},
"RDATA": { "actual": "m_axi_rdata"},
"RLAST": { "actual": "m_axi_rlast"},
"RREADY": { "actual": "m_axi_rready"},
"RRESP": { "actual": "m_axi_rresp"},
"RVALID": { "actual": "m_axi_rvalid"},
"WDATA": { "actual": "m_axi_wdata"},
"WLAST": { "actual": "m_axi_wlast"},
"WREADY": { "actual": "m_axi_wready"},
"WSTRB": { "actual": "m_axi_wstrb"},
"WVALID": { "actual": "m_axi_wvalid"}
}
},
"/m00_exit_pipeline/m00_exit/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARCACHE": { "actual": "s_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARID": { "actual": "s_axi_arid"},
"ARLEN": { "actual": "s_axi_arlen"},
"ARLOCK": { "actual": "s_axi_arlock"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARQOS": { "actual": "s_axi_arqos"},
"ARREADY": { "actual": "s_axi_arready"},
"ARUSER": { "actual": "s_axi_aruser"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWCACHE": { "actual": "s_axi_awcache"},
"AWID": { "actual": "s_axi_awid"},
"AWLEN": { "actual": "s_axi_awlen"},
"AWLOCK": { "actual": "s_axi_awlock"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWQOS": { "actual": "s_axi_awqos"},
"AWREADY": { "actual": "s_axi_awready"},
"AWUSER": { "actual": "s_axi_awuser"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BID": { "actual": "s_axi_bid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BUSER": { "actual": "s_axi_buser"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RID": { "actual": "s_axi_rid"},
"RLAST": { "actual": "s_axi_rlast"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RUSER": { "actual": "s_axi_ruser"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WLAST": { "actual": "s_axi_wlast"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WUSER": { "actual": "s_axi_wuser"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/m00_exit_pipeline/m_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr"},
"ARBURST": { "actual": "m_axi_arburst"},
"ARCACHE": { "actual": "m_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARLEN": { "actual": "m_axi_arlen"},
"ARLOCK": { "actual": "m_axi_arlock"},
"ARPROT": { "actual": "m_axi_arprot"},
"ARQOS": { "actual": "m_axi_arqos"},
"ARREADY": { "actual": "m_axi_arready"},
"ARSIZE": { "actual": "m_axi_arsize"},
"ARVALID": { "actual": "m_axi_arvalid"},
"AWADDR": { "actual": "m_axi_awaddr"},
"AWBURST": { "actual": "m_axi_awburst"},
"AWCACHE": { "actual": "m_axi_awcache"},
"AWLEN": { "actual": "m_axi_awlen"},
"AWLOCK": { "actual": "m_axi_awlock"},
"AWPROT": { "actual": "m_axi_awprot"},
"AWQOS": { "actual": "m_axi_awqos"},
"AWREADY": { "actual": "m_axi_awready"},
"AWSIZE": { "actual": "m_axi_awsize"},
"AWVALID": { "actual": "m_axi_awvalid"},
"BREADY": { "actual": "m_axi_bready"},
"BRESP": { "actual": "m_axi_bresp"},
"BVALID": { "actual": "m_axi_bvalid"},
"RDATA": { "actual": "m_axi_rdata"},
"RLAST": { "actual": "m_axi_rlast"},
"RREADY": { "actual": "m_axi_rready"},
"RRESP": { "actual": "m_axi_rresp"},
"RVALID": { "actual": "m_axi_rvalid"},
"WDATA": { "actual": "m_axi_wdata"},
"WLAST": { "actual": "m_axi_wlast"},
"WREADY": { "actual": "m_axi_wready"},
"WSTRB": { "actual": "m_axi_wstrb"},
"WVALID": { "actual": "m_axi_wvalid"}
}
},
"/m00_exit_pipeline/s_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARCACHE": { "actual": "s_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARID": { "actual": "s_axi_arid"},
"ARLEN": { "actual": "s_axi_arlen"},
"ARLOCK": { "actual": "s_axi_arlock"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARQOS": { "actual": "s_axi_arqos"},
"ARREADY": { "actual": "s_axi_arready"},
"ARUSER": { "actual": "s_axi_aruser"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWCACHE": { "actual": "s_axi_awcache"},
"AWID": { "actual": "s_axi_awid"},
"AWLEN": { "actual": "s_axi_awlen"},
"AWLOCK": { "actual": "s_axi_awlock"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWQOS": { "actual": "s_axi_awqos"},
"AWREADY": { "actual": "s_axi_awready"},
"AWUSER": { "actual": "s_axi_awuser"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BID": { "actual": "s_axi_bid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BUSER": { "actual": "s_axi_buser"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RID": { "actual": "s_axi_rid"},
"RLAST": { "actual": "s_axi_rlast"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RUSER": { "actual": "s_axi_ruser"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WLAST": { "actual": "s_axi_wlast"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WUSER": { "actual": "s_axi_wuser"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/m00_nodes/m00_aw_node/M_AXIS_ARB": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "s_sc_aclk"},
"ARESETN": { "actual": "s_sc_aresetn"},
"TDATA": { "actual": "m_axis_arb_tdata"},
"TREADY": { "actual": "m_axis_arb_tready"},
"TVALID": { "actual": "m_axis_arb_tvalid"}
}
},
"/m00_nodes/m00_w_node/S_AXIS_ARB": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "s_sc_aclk"},
"ARESETN": { "actual": "s_sc_aresetn"},
"TDATA": { "actual": "s_axis_arb_tdata"},
"TREADY": { "actual": "s_axis_arb_tready"},
"TVALID": { "actual": "s_axis_arb_tvalid"}
}
},
"/m00_sc2axi/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr"},
"ARCACHE": { "actual": "m_axi_arcache"},
"ARID": { "actual": "m_axi_arid"},
"ARLEN": { "actual": "m_axi_arlen"},
"ARLOCK": { "actual": "m_axi_arlock"},
"ARPROT": { "actual": "m_axi_arprot"},
"ARQOS": { "actual": "m_axi_arqos"},
"ARREADY": { "actual": "m_axi_arready"},
"ARUSER": { "actual": "m_axi_aruser"},
"ARVALID": { "actual": "m_axi_arvalid"},
"AWADDR": { "actual": "m_axi_awaddr"},
"AWCACHE": { "actual": "m_axi_awcache"},
"AWID": { "actual": "m_axi_awid"},
"AWLEN": { "actual": "m_axi_awlen"},
"AWLOCK": { "actual": "m_axi_awlock"},
"AWPROT": { "actual": "m_axi_awprot"},
"AWQOS": { "actual": "m_axi_awqos"},
"AWREADY": { "actual": "m_axi_awready"},
"AWUSER": { "actual": "m_axi_awuser"},
"AWVALID": { "actual": "m_axi_awvalid"},
"BID": { "actual": "m_axi_bid"},
"BREADY": { "actual": "m_axi_bready"},
"BRESP": { "actual": "m_axi_bresp"},
"BUSER": { "actual": "m_axi_buser"},
"BVALID": { "actual": "m_axi_bvalid"},
"RDATA": { "actual": "m_axi_rdata"},
"RID": { "actual": "m_axi_rid"},
"RLAST": { "actual": "m_axi_rlast"},
"RREADY": { "actual": "m_axi_rready"},
"RRESP": { "actual": "m_axi_rresp"},
"RUSER": { "actual": "m_axi_ruser"},
"RVALID": { "actual": "m_axi_rvalid"},
"WDATA": { "actual": "m_axi_wdata"},
"WLAST": { "actual": "m_axi_wlast"},
"WREADY": { "actual": "m_axi_wready"},
"WSTRB": { "actual": "m_axi_wstrb"},
"WUSER": { "actual": "m_axi_wuser"},
"WVALID": { "actual": "m_axi_wvalid"}
}
},
"/s00_axi2sc/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARCACHE": { "actual": "s_axi_arcache"},
"ARID": { "actual": "s_axi_arid"},
"ARLEN": { "actual": "s_axi_arlen"},
"ARLOCK": { "actual": "s_axi_arlock"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARQOS": { "actual": "s_axi_arqos"},
"ARREADY": { "actual": "s_axi_arready"},
"ARUSER": { "actual": "s_axi_aruser"},
"ARVALID": { "actual": "s_axi_arvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RID": { "actual": "s_axi_rid"},
"RLAST": { "actual": "s_axi_rlast"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RUSER": { "actual": "s_axi_ruser"},
"RVALID": { "actual": "s_axi_rvalid"}
}
},
"/s00_entry_pipeline/m_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr"},
"ARCACHE": { "actual": "m_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARID": { "actual": "m_axi_arid"},
"ARLEN": { "actual": "m_axi_arlen"},
"ARLOCK": { "actual": "m_axi_arlock"},
"ARPROT": { "actual": "m_axi_arprot"},
"ARQOS": { "actual": "m_axi_arqos"},
"ARREADY": { "actual": "m_axi_arready"},
"ARUSER": { "actual": "m_axi_aruser"},
"ARVALID": { "actual": "m_axi_arvalid"},
"RDATA": { "actual": "m_axi_rdata"},
"RID": { "actual": "m_axi_rid"},
"RLAST": { "actual": "m_axi_rlast"},
"RREADY": { "actual": "m_axi_rready"},
"RRESP": { "actual": "m_axi_rresp"},
"RUSER": { "actual": "m_axi_ruser"},
"RVALID": { "actual": "m_axi_rvalid"}
}
},
"/s00_entry_pipeline/s00_mmu/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr"},
"ARBURST": { "actual": "m_axi_arburst"},
"ARCACHE": { "actual": "m_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARLEN": { "actual": "m_axi_arlen"},
"ARLOCK": { "actual": "m_axi_arlock"},
"ARPROT": { "actual": "m_axi_arprot"},
"ARQOS": { "actual": "m_axi_arqos"},
"ARREADY": { "actual": "m_axi_arready"},
"ARSIZE": { "actual": "m_axi_arsize"},
"ARUSER": { "actual": "m_axi_aruser"},
"ARVALID": { "actual": "m_axi_arvalid"},
"RDATA": { "actual": "m_axi_rdata"},
"RLAST": { "actual": "m_axi_rlast"},
"RREADY": { "actual": "m_axi_rready"},
"RRESP": { "actual": "m_axi_rresp"},
"RUSER": { "actual": "m_axi_ruser"},
"RVALID": { "actual": "m_axi_rvalid"}
}
},
"/s00_entry_pipeline/s00_mmu/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARBURST": { "actual": "s_axi_arburst"},
"ARCACHE": { "actual": "s_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARLEN": { "actual": "s_axi_arlen"},
"ARLOCK": { "actual": "s_axi_arlock"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARQOS": { "actual": "s_axi_arqos"},
"ARREADY": { "actual": "s_axi_arready"},
"ARSIZE": { "actual": "s_axi_arsize"},
"ARVALID": { "actual": "s_axi_arvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RLAST": { "actual": "s_axi_rlast"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"}
}
},
"/s00_entry_pipeline/s00_si_converter/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr"},
"ARCACHE": { "actual": "m_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARID": { "actual": "m_axi_arid"},
"ARLEN": { "actual": "m_axi_arlen"},
"ARLOCK": { "actual": "m_axi_arlock"},
"ARPROT": { "actual": "m_axi_arprot"},
"ARQOS": { "actual": "m_axi_arqos"},
"ARREADY": { "actual": "m_axi_arready"},
"ARUSER": { "actual": "m_axi_aruser"},
"ARVALID": { "actual": "m_axi_arvalid"},
"RDATA": { "actual": "m_axi_rdata"},
"RID": { "actual": "m_axi_rid"},
"RLAST": { "actual": "m_axi_rlast"},
"RREADY": { "actual": "m_axi_rready"},
"RRESP": { "actual": "m_axi_rresp"},
"RUSER": { "actual": "m_axi_ruser"},
"RVALID": { "actual": "m_axi_rvalid"}
}
},
"/s00_entry_pipeline/s00_si_converter/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARCACHE": { "actual": "s_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARID": { "actual": "s_axi_arid"},
"ARLEN": { "actual": "s_axi_arlen"},
"ARLOCK": { "actual": "s_axi_arlock"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARQOS": { "actual": "s_axi_arqos"},
"ARREADY": { "actual": "s_axi_arready"},
"ARSIZE": { "actual": "s_axi_arsize"},
"ARUSER": { "actual": "s_axi_aruser"},
"ARVALID": { "actual": "s_axi_arvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RID": { "actual": "s_axi_rid"},
"RLAST": { "actual": "s_axi_rlast"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RUSER": { "actual": "s_axi_ruser"},
"RVALID": { "actual": "s_axi_rvalid"}
}
},
"/s00_entry_pipeline/s00_transaction_regulator/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr"},
"ARBURST": { "actual": "m_axi_arburst"},
"ARCACHE": { "actual": "m_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARID": { "actual": "m_axi_arid"},
"ARLEN": { "actual": "m_axi_arlen"},
"ARLOCK": { "actual": "m_axi_arlock"},
"ARPROT": { "actual": "m_axi_arprot"},
"ARQOS": { "actual": "m_axi_arqos"},
"ARREADY": { "actual": "m_axi_arready"},
"ARSIZE": { "actual": "m_axi_arsize"},
"ARUSER": { "actual": "m_axi_aruser"},
"ARVALID": { "actual": "m_axi_arvalid"},
"RDATA": { "actual": "m_axi_rdata"},
"RID": { "actual": "m_axi_rid"},
"RLAST": { "actual": "m_axi_rlast"},
"RREADY": { "actual": "m_axi_rready"},
"RRESP": { "actual": "m_axi_rresp"},
"RUSER": { "actual": "m_axi_ruser"},
"RVALID": { "actual": "m_axi_rvalid"}
}
},
"/s00_entry_pipeline/s00_transaction_regulator/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARBURST": { "actual": "s_axi_arburst"},
"ARCACHE": { "actual": "s_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARLEN": { "actual": "s_axi_arlen"},
"ARLOCK": { "actual": "s_axi_arlock"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARQOS": { "actual": "s_axi_arqos"},
"ARREADY": { "actual": "s_axi_arready"},
"ARSIZE": { "actual": "s_axi_arsize"},
"ARUSER": { "actual": "s_axi_aruser"},
"ARVALID": { "actual": "s_axi_arvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RLAST": { "actual": "s_axi_rlast"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RUSER": { "actual": "s_axi_ruser"},
"RVALID": { "actual": "s_axi_rvalid"}
}
},
"/s00_entry_pipeline/s_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARBURST": { "actual": "s_axi_arburst"},
"ARCACHE": { "actual": "s_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARLEN": { "actual": "s_axi_arlen"},
"ARLOCK": { "actual": "s_axi_arlock"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARQOS": { "actual": "s_axi_arqos"},
"ARREADY": { "actual": "s_axi_arready"},
"ARSIZE": { "actual": "s_axi_arsize"},
"ARVALID": { "actual": "s_axi_arvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RLAST": { "actual": "s_axi_rlast"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"}
}
},
"/s01_axi2sc/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWCACHE": { "actual": "s_axi_awcache"},
"AWID": { "actual": "s_axi_awid"},
"AWLEN": { "actual": "s_axi_awlen"},
"AWLOCK": { "actual": "s_axi_awlock"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWQOS": { "actual": "s_axi_awqos"},
"AWREADY": { "actual": "s_axi_awready"},
"AWUSER": { "actual": "s_axi_awuser"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BID": { "actual": "s_axi_bid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BUSER": { "actual": "s_axi_buser"},
"BVALID": { "actual": "s_axi_bvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WLAST": { "actual": "s_axi_wlast"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WUSER": { "actual": "s_axi_wuser"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/s01_entry_pipeline/m_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARESETN": { "actual": "aresetn"},
"AWADDR": { "actual": "m_axi_awaddr"},
"AWCACHE": { "actual": "m_axi_awcache"},
"AWID": { "actual": "m_axi_awid"},
"AWLEN": { "actual": "m_axi_awlen"},
"AWLOCK": { "actual": "m_axi_awlock"},
"AWPROT": { "actual": "m_axi_awprot"},
"AWQOS": { "actual": "m_axi_awqos"},
"AWREADY": { "actual": "m_axi_awready"},
"AWUSER": { "actual": "m_axi_awuser"},
"AWVALID": { "actual": "m_axi_awvalid"},
"BID": { "actual": "m_axi_bid"},
"BREADY": { "actual": "m_axi_bready"},
"BRESP": { "actual": "m_axi_bresp"},
"BUSER": { "actual": "m_axi_buser"},
"BVALID": { "actual": "m_axi_bvalid"},
"WDATA": { "actual": "m_axi_wdata"},
"WLAST": { "actual": "m_axi_wlast"},
"WREADY": { "actual": "m_axi_wready"},
"WSTRB": { "actual": "m_axi_wstrb"},
"WUSER": { "actual": "m_axi_wuser"},
"WVALID": { "actual": "m_axi_wvalid"}
}
},
"/s01_entry_pipeline/s01_mmu/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARESETN": { "actual": "aresetn"},
"AWADDR": { "actual": "m_axi_awaddr"},
"AWBURST": { "actual": "m_axi_awburst"},
"AWCACHE": { "actual": "m_axi_awcache"},
"AWLEN": { "actual": "m_axi_awlen"},
"AWLOCK": { "actual": "m_axi_awlock"},
"AWPROT": { "actual": "m_axi_awprot"},
"AWQOS": { "actual": "m_axi_awqos"},
"AWREADY": { "actual": "m_axi_awready"},
"AWSIZE": { "actual": "m_axi_awsize"},
"AWUSER": { "actual": "m_axi_awuser"},
"AWVALID": { "actual": "m_axi_awvalid"},
"BREADY": { "actual": "m_axi_bready"},
"BRESP": { "actual": "m_axi_bresp"},
"BUSER": { "actual": "m_axi_buser"},
"BVALID": { "actual": "m_axi_bvalid"},
"WDATA": { "actual": "m_axi_wdata"},
"WLAST": { "actual": "m_axi_wlast"},
"WREADY": { "actual": "m_axi_wready"},
"WSTRB": { "actual": "m_axi_wstrb"},
"WUSER": { "actual": "m_axi_wuser"},
"WVALID": { "actual": "m_axi_wvalid"}
}
},
"/s01_entry_pipeline/s01_mmu/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARESETN": { "actual": "aresetn"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWBURST": { "actual": "s_axi_awburst"},
"AWCACHE": { "actual": "s_axi_awcache"},
"AWLEN": { "actual": "s_axi_awlen"},
"AWLOCK": { "actual": "s_axi_awlock"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWQOS": { "actual": "s_axi_awqos"},
"AWREADY": { "actual": "s_axi_awready"},
"AWSIZE": { "actual": "s_axi_awsize"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WLAST": { "actual": "s_axi_wlast"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/s01_entry_pipeline/s01_si_converter/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARESETN": { "actual": "aresetn"},
"AWADDR": { "actual": "m_axi_awaddr"},
"AWCACHE": { "actual": "m_axi_awcache"},
"AWID": { "actual": "m_axi_awid"},
"AWLEN": { "actual": "m_axi_awlen"},
"AWLOCK": { "actual": "m_axi_awlock"},
"AWPROT": { "actual": "m_axi_awprot"},
"AWQOS": { "actual": "m_axi_awqos"},
"AWREADY": { "actual": "m_axi_awready"},
"AWUSER": { "actual": "m_axi_awuser"},
"AWVALID": { "actual": "m_axi_awvalid"},
"BID": { "actual": "m_axi_bid"},
"BREADY": { "actual": "m_axi_bready"},
"BRESP": { "actual": "m_axi_bresp"},
"BUSER": { "actual": "m_axi_buser"},
"BVALID": { "actual": "m_axi_bvalid"},
"WDATA": { "actual": "m_axi_wdata"},
"WLAST": { "actual": "m_axi_wlast"},
"WREADY": { "actual": "m_axi_wready"},
"WSTRB": { "actual": "m_axi_wstrb"},
"WUSER": { "actual": "m_axi_wuser"},
"WVALID": { "actual": "m_axi_wvalid"}
}
},
"/s01_entry_pipeline/s01_si_converter/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARESETN": { "actual": "aresetn"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWCACHE": { "actual": "s_axi_awcache"},
"AWID": { "actual": "s_axi_awid"},
"AWLEN": { "actual": "s_axi_awlen"},
"AWLOCK": { "actual": "s_axi_awlock"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWQOS": { "actual": "s_axi_awqos"},
"AWREADY": { "actual": "s_axi_awready"},
"AWSIZE": { "actual": "s_axi_awsize"},
"AWUSER": { "actual": "s_axi_awuser"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BID": { "actual": "s_axi_bid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BUSER": { "actual": "s_axi_buser"},
"BVALID": { "actual": "s_axi_bvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WLAST": { "actual": "s_axi_wlast"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WUSER": { "actual": "s_axi_wuser"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/s01_entry_pipeline/s01_transaction_regulator/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARESETN": { "actual": "aresetn"},
"AWADDR": { "actual": "m_axi_awaddr"},
"AWBURST": { "actual": "m_axi_awburst"},
"AWCACHE": { "actual": "m_axi_awcache"},
"AWID": { "actual": "m_axi_awid"},
"AWLEN": { "actual": "m_axi_awlen"},
"AWLOCK": { "actual": "m_axi_awlock"},
"AWPROT": { "actual": "m_axi_awprot"},
"AWQOS": { "actual": "m_axi_awqos"},
"AWREADY": { "actual": "m_axi_awready"},
"AWSIZE": { "actual": "m_axi_awsize"},
"AWUSER": { "actual": "m_axi_awuser"},
"AWVALID": { "actual": "m_axi_awvalid"},
"BID": { "actual": "m_axi_bid"},
"BREADY": { "actual": "m_axi_bready"},
"BRESP": { "actual": "m_axi_bresp"},
"BUSER": { "actual": "m_axi_buser"},
"BVALID": { "actual": "m_axi_bvalid"},
"WDATA": { "actual": "m_axi_wdata"},
"WLAST": { "actual": "m_axi_wlast"},
"WREADY": { "actual": "m_axi_wready"},
"WSTRB": { "actual": "m_axi_wstrb"},
"WUSER": { "actual": "m_axi_wuser"},
"WVALID": { "actual": "m_axi_wvalid"}
}
},
"/s01_entry_pipeline/s01_transaction_regulator/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARESETN": { "actual": "aresetn"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWBURST": { "actual": "s_axi_awburst"},
"AWCACHE": { "actual": "s_axi_awcache"},
"AWLEN": { "actual": "s_axi_awlen"},
"AWLOCK": { "actual": "s_axi_awlock"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWQOS": { "actual": "s_axi_awqos"},
"AWREADY": { "actual": "s_axi_awready"},
"AWSIZE": { "actual": "s_axi_awsize"},
"AWUSER": { "actual": "s_axi_awuser"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BUSER": { "actual": "s_axi_buser"},
"BVALID": { "actual": "s_axi_bvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WLAST": { "actual": "s_axi_wlast"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WUSER": { "actual": "s_axi_wuser"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/s01_entry_pipeline/s_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARESETN": { "actual": "aresetn"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWBURST": { "actual": "s_axi_awburst"},
"AWCACHE": { "actual": "s_axi_awcache"},
"AWLEN": { "actual": "s_axi_awlen"},
"AWLOCK": { "actual": "s_axi_awlock"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWQOS": { "actual": "s_axi_awqos"},
"AWREADY": { "actual": "s_axi_awready"},
"AWSIZE": { "actual": "s_axi_awsize"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WLAST": { "actual": "s_axi_wlast"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
}
}
}
}
}
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xsim/protoinst_files/design_a9_1.protoinst
+836
View File
@@ -0,0 +1,836 @@
{
"version": "1.0",
"modules": {
"design_a9_1": {
"proto_instances": {
"/axi_bram_ctrl_0/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_bram_ctrl_1/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_bram_ctrl_2/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_bram_ctrl_3/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_bram_ctrl_4/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_dma_0/M_AXIS_MM2S": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "m_axi_mm2s_aclk"},
"ARESETN": { "actual": "mm2s_prmry_reset_out_n"},
"TDATA": { "actual": "m_axis_mm2s_tdata"},
"TKEEP": { "actual": "m_axis_mm2s_tkeep"},
"TLAST": { "actual": "m_axis_mm2s_tlast"},
"TREADY": { "actual": "m_axis_mm2s_tready"},
"TVALID": { "actual": "m_axis_mm2s_tvalid"}
}
},
"/axi_dma_0/M_AXI_MM2S": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "m_axi_mm2s_aclk"},
"ARADDR": { "actual": "m_axi_mm2s_araddr"},
"ARBURST": { "actual": "m_axi_mm2s_arburst"},
"ARCACHE": { "actual": "m_axi_mm2s_arcache"},
"ARESETN": { "actual": "mm2s_prmry_reset_out_n"},
"ARLEN": { "actual": "m_axi_mm2s_arlen"},
"ARPROT": { "actual": "m_axi_mm2s_arprot"},
"ARREADY": { "actual": "m_axi_mm2s_arready"},
"ARSIZE": { "actual": "m_axi_mm2s_arsize"},
"ARVALID": { "actual": "m_axi_mm2s_arvalid"},
"RDATA": { "actual": "m_axi_mm2s_rdata"},
"RLAST": { "actual": "m_axi_mm2s_rlast"},
"RREADY": { "actual": "m_axi_mm2s_rready"},
"RRESP": { "actual": "m_axi_mm2s_rresp"},
"RVALID": { "actual": "m_axi_mm2s_rvalid"}
}
},
"/axi_dma_0/S_AXI_LITE": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_lite_aclk"},
"ARADDR": { "actual": "s_axi_lite_araddr"},
"ARESETN": { "actual": "axi_resetn"},
"ARREADY": { "actual": "s_axi_lite_arready"},
"ARVALID": { "actual": "s_axi_lite_arvalid"},
"AWADDR": { "actual": "s_axi_lite_awaddr"},
"AWREADY": { "actual": "s_axi_lite_awready"},
"AWVALID": { "actual": "s_axi_lite_awvalid"},
"BREADY": { "actual": "s_axi_lite_bready"},
"BRESP": { "actual": "s_axi_lite_bresp"},
"BVALID": { "actual": "s_axi_lite_bvalid"},
"RDATA": { "actual": "s_axi_lite_rdata"},
"RREADY": { "actual": "s_axi_lite_rready"},
"RRESP": { "actual": "s_axi_lite_rresp"},
"RVALID": { "actual": "s_axi_lite_rvalid"},
"WDATA": { "actual": "s_axi_lite_wdata"},
"WREADY": { "actual": "s_axi_lite_wready"},
"WVALID": { "actual": "s_axi_lite_wvalid"}
}
},
"/axi_dma_1/M_AXI_S2MM": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "m_axi_s2mm_aclk"},
"ARESETN": { "actual": "s2mm_prmry_reset_out_n"},
"AWADDR": { "actual": "m_axi_s2mm_awaddr"},
"AWBURST": { "actual": "m_axi_s2mm_awburst"},
"AWCACHE": { "actual": "m_axi_s2mm_awcache"},
"AWLEN": { "actual": "m_axi_s2mm_awlen"},
"AWPROT": { "actual": "m_axi_s2mm_awprot"},
"AWREADY": { "actual": "m_axi_s2mm_awready"},
"AWSIZE": { "actual": "m_axi_s2mm_awsize"},
"AWVALID": { "actual": "m_axi_s2mm_awvalid"},
"BREADY": { "actual": "m_axi_s2mm_bready"},
"BRESP": { "actual": "m_axi_s2mm_bresp"},
"BVALID": { "actual": "m_axi_s2mm_bvalid"},
"WDATA": { "actual": "m_axi_s2mm_wdata"},
"WLAST": { "actual": "m_axi_s2mm_wlast"},
"WREADY": { "actual": "m_axi_s2mm_wready"},
"WSTRB": { "actual": "m_axi_s2mm_wstrb"},
"WVALID": { "actual": "m_axi_s2mm_wvalid"}
}
},
"/axi_dma_1/S_AXIS_S2MM": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "m_axi_s2mm_aclk"},
"ARESETN": { "actual": "s2mm_prmry_reset_out_n"},
"TDATA": { "actual": "s_axis_s2mm_tdata"},
"TKEEP": { "actual": "s_axis_s2mm_tkeep"},
"TLAST": { "actual": "s_axis_s2mm_tlast"},
"TREADY": { "actual": "s_axis_s2mm_tready"},
"TVALID": { "actual": "s_axis_s2mm_tvalid"}
}
},
"/axi_dma_1/S_AXI_LITE": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_lite_aclk"},
"ARADDR": { "actual": "s_axi_lite_araddr"},
"ARESETN": { "actual": "axi_resetn"},
"ARREADY": { "actual": "s_axi_lite_arready"},
"ARVALID": { "actual": "s_axi_lite_arvalid"},
"AWADDR": { "actual": "s_axi_lite_awaddr"},
"AWREADY": { "actual": "s_axi_lite_awready"},
"AWVALID": { "actual": "s_axi_lite_awvalid"},
"BREADY": { "actual": "s_axi_lite_bready"},
"BRESP": { "actual": "s_axi_lite_bresp"},
"BVALID": { "actual": "s_axi_lite_bvalid"},
"RDATA": { "actual": "s_axi_lite_rdata"},
"RREADY": { "actual": "s_axi_lite_rready"},
"RRESP": { "actual": "s_axi_lite_rresp"},
"RVALID": { "actual": "s_axi_lite_rvalid"},
"WDATA": { "actual": "s_axi_lite_wdata"},
"WREADY": { "actual": "s_axi_lite_wready"},
"WVALID": { "actual": "s_axi_lite_wvalid"}
}
},
"/axi_gpio_0/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_iic_0/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_iic_1/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_smc/M00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "M00_AXI_araddr"},
"ARPROT": { "actual": "M00_AXI_arprot"},
"ARREADY": { "actual": "M00_AXI_arready"},
"ARVALID": { "actual": "M00_AXI_arvalid"},
"AWADDR": { "actual": "M00_AXI_awaddr"},
"AWPROT": { "actual": "M00_AXI_awprot"},
"AWREADY": { "actual": "M00_AXI_awready"},
"AWVALID": { "actual": "M00_AXI_awvalid"},
"BREADY": { "actual": "M00_AXI_bready"},
"BRESP": { "actual": "M00_AXI_bresp"},
"BVALID": { "actual": "M00_AXI_bvalid"},
"RDATA": { "actual": "M00_AXI_rdata"},
"RREADY": { "actual": "M00_AXI_rready"},
"RRESP": { "actual": "M00_AXI_rresp"},
"RVALID": { "actual": "M00_AXI_rvalid"},
"WDATA": { "actual": "M00_AXI_wdata"},
"WREADY": { "actual": "M00_AXI_wready"},
"WSTRB": { "actual": "M00_AXI_wstrb"},
"WVALID": { "actual": "M00_AXI_wvalid"}
}
},
"/axi_smc/M01_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "M01_AXI_araddr"},
"ARPROT": { "actual": "M01_AXI_arprot"},
"ARREADY": { "actual": "M01_AXI_arready"},
"ARVALID": { "actual": "M01_AXI_arvalid"},
"AWADDR": { "actual": "M01_AXI_awaddr"},
"AWPROT": { "actual": "M01_AXI_awprot"},
"AWREADY": { "actual": "M01_AXI_awready"},
"AWVALID": { "actual": "M01_AXI_awvalid"},
"BREADY": { "actual": "M01_AXI_bready"},
"BRESP": { "actual": "M01_AXI_bresp"},
"BVALID": { "actual": "M01_AXI_bvalid"},
"RDATA": { "actual": "M01_AXI_rdata"},
"RREADY": { "actual": "M01_AXI_rready"},
"RRESP": { "actual": "M01_AXI_rresp"},
"RVALID": { "actual": "M01_AXI_rvalid"},
"WDATA": { "actual": "M01_AXI_wdata"},
"WREADY": { "actual": "M01_AXI_wready"},
"WSTRB": { "actual": "M01_AXI_wstrb"},
"WVALID": { "actual": "M01_AXI_wvalid"}
}
},
"/axi_smc/M02_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "M02_AXI_araddr"},
"ARPROT": { "actual": "M02_AXI_arprot"},
"ARREADY": { "actual": "M02_AXI_arready"},
"ARVALID": { "actual": "M02_AXI_arvalid"},
"AWADDR": { "actual": "M02_AXI_awaddr"},
"AWPROT": { "actual": "M02_AXI_awprot"},
"AWREADY": { "actual": "M02_AXI_awready"},
"AWVALID": { "actual": "M02_AXI_awvalid"},
"BREADY": { "actual": "M02_AXI_bready"},
"BRESP": { "actual": "M02_AXI_bresp"},
"BVALID": { "actual": "M02_AXI_bvalid"},
"RDATA": { "actual": "M02_AXI_rdata"},
"RREADY": { "actual": "M02_AXI_rready"},
"RRESP": { "actual": "M02_AXI_rresp"},
"RVALID": { "actual": "M02_AXI_rvalid"},
"WDATA": { "actual": "M02_AXI_wdata"},
"WREADY": { "actual": "M02_AXI_wready"},
"WSTRB": { "actual": "M02_AXI_wstrb"},
"WVALID": { "actual": "M02_AXI_wvalid"}
}
},
"/axi_smc/M03_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "M03_AXI_araddr"},
"ARPROT": { "actual": "M03_AXI_arprot"},
"ARREADY": { "actual": "M03_AXI_arready"},
"ARVALID": { "actual": "M03_AXI_arvalid"},
"AWADDR": { "actual": "M03_AXI_awaddr"},
"AWPROT": { "actual": "M03_AXI_awprot"},
"AWREADY": { "actual": "M03_AXI_awready"},
"AWVALID": { "actual": "M03_AXI_awvalid"},
"BREADY": { "actual": "M03_AXI_bready"},
"BRESP": { "actual": "M03_AXI_bresp"},
"BVALID": { "actual": "M03_AXI_bvalid"},
"RDATA": { "actual": "M03_AXI_rdata"},
"RREADY": { "actual": "M03_AXI_rready"},
"RRESP": { "actual": "M03_AXI_rresp"},
"RVALID": { "actual": "M03_AXI_rvalid"},
"WDATA": { "actual": "M03_AXI_wdata"},
"WREADY": { "actual": "M03_AXI_wready"},
"WSTRB": { "actual": "M03_AXI_wstrb"},
"WVALID": { "actual": "M03_AXI_wvalid"}
}
},
"/axi_smc/M04_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "M04_AXI_araddr"},
"ARPROT": { "actual": "M04_AXI_arprot"},
"ARREADY": { "actual": "M04_AXI_arready"},
"ARVALID": { "actual": "M04_AXI_arvalid"},
"AWADDR": { "actual": "M04_AXI_awaddr"},
"AWPROT": { "actual": "M04_AXI_awprot"},
"AWREADY": { "actual": "M04_AXI_awready"},
"AWVALID": { "actual": "M04_AXI_awvalid"},
"BREADY": { "actual": "M04_AXI_bready"},
"BRESP": { "actual": "M04_AXI_bresp"},
"BVALID": { "actual": "M04_AXI_bvalid"},
"RDATA": { "actual": "M04_AXI_rdata"},
"RREADY": { "actual": "M04_AXI_rready"},
"RRESP": { "actual": "M04_AXI_rresp"},
"RVALID": { "actual": "M04_AXI_rvalid"},
"WDATA": { "actual": "M04_AXI_wdata"},
"WREADY": { "actual": "M04_AXI_wready"},
"WSTRB": { "actual": "M04_AXI_wstrb"},
"WVALID": { "actual": "M04_AXI_wvalid"}
}
},
"/axi_smc/M05_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "M05_AXI_araddr"},
"ARPROT": { "actual": "M05_AXI_arprot"},
"ARREADY": { "actual": "M05_AXI_arready"},
"ARVALID": { "actual": "M05_AXI_arvalid"},
"AWADDR": { "actual": "M05_AXI_awaddr"},
"AWPROT": { "actual": "M05_AXI_awprot"},
"AWREADY": { "actual": "M05_AXI_awready"},
"AWVALID": { "actual": "M05_AXI_awvalid"},
"BREADY": { "actual": "M05_AXI_bready"},
"BRESP": { "actual": "M05_AXI_bresp"},
"BVALID": { "actual": "M05_AXI_bvalid"},
"RDATA": { "actual": "M05_AXI_rdata"},
"RREADY": { "actual": "M05_AXI_rready"},
"RRESP": { "actual": "M05_AXI_rresp"},
"RVALID": { "actual": "M05_AXI_rvalid"},
"WDATA": { "actual": "M05_AXI_wdata"},
"WREADY": { "actual": "M05_AXI_wready"},
"WSTRB": { "actual": "M05_AXI_wstrb"},
"WVALID": { "actual": "M05_AXI_wvalid"}
}
},
"/axi_smc/M06_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "M06_AXI_araddr"},
"ARPROT": { "actual": "M06_AXI_arprot"},
"ARREADY": { "actual": "M06_AXI_arready"},
"ARVALID": { "actual": "M06_AXI_arvalid"},
"AWADDR": { "actual": "M06_AXI_awaddr"},
"AWPROT": { "actual": "M06_AXI_awprot"},
"AWREADY": { "actual": "M06_AXI_awready"},
"AWVALID": { "actual": "M06_AXI_awvalid"},
"BREADY": { "actual": "M06_AXI_bready"},
"BRESP": { "actual": "M06_AXI_bresp"},
"BVALID": { "actual": "M06_AXI_bvalid"},
"RDATA": { "actual": "M06_AXI_rdata"},
"RREADY": { "actual": "M06_AXI_rready"},
"RRESP": { "actual": "M06_AXI_rresp"},
"RVALID": { "actual": "M06_AXI_rvalid"},
"WDATA": { "actual": "M06_AXI_wdata"},
"WREADY": { "actual": "M06_AXI_wready"},
"WSTRB": { "actual": "M06_AXI_wstrb"},
"WVALID": { "actual": "M06_AXI_wvalid"}
}
},
"/axi_smc/M07_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "M07_AXI_araddr"},
"ARPROT": { "actual": "M07_AXI_arprot"},
"ARREADY": { "actual": "M07_AXI_arready"},
"ARVALID": { "actual": "M07_AXI_arvalid"},
"AWADDR": { "actual": "M07_AXI_awaddr"},
"AWPROT": { "actual": "M07_AXI_awprot"},
"AWREADY": { "actual": "M07_AXI_awready"},
"AWVALID": { "actual": "M07_AXI_awvalid"},
"BREADY": { "actual": "M07_AXI_bready"},
"BRESP": { "actual": "M07_AXI_bresp"},
"BVALID": { "actual": "M07_AXI_bvalid"},
"RDATA": { "actual": "M07_AXI_rdata"},
"RREADY": { "actual": "M07_AXI_rready"},
"RRESP": { "actual": "M07_AXI_rresp"},
"RVALID": { "actual": "M07_AXI_rvalid"},
"WDATA": { "actual": "M07_AXI_wdata"},
"WREADY": { "actual": "M07_AXI_wready"},
"WSTRB": { "actual": "M07_AXI_wstrb"},
"WVALID": { "actual": "M07_AXI_wvalid"}
}
},
"/axi_smc/M08_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "M08_AXI_araddr"},
"ARPROT": { "actual": "M08_AXI_arprot"},
"ARREADY": { "actual": "M08_AXI_arready"},
"ARVALID": { "actual": "M08_AXI_arvalid"},
"AWADDR": { "actual": "M08_AXI_awaddr"},
"AWPROT": { "actual": "M08_AXI_awprot"},
"AWREADY": { "actual": "M08_AXI_awready"},
"AWVALID": { "actual": "M08_AXI_awvalid"},
"BREADY": { "actual": "M08_AXI_bready"},
"BRESP": { "actual": "M08_AXI_bresp"},
"BVALID": { "actual": "M08_AXI_bvalid"},
"RDATA": { "actual": "M08_AXI_rdata"},
"RREADY": { "actual": "M08_AXI_rready"},
"RRESP": { "actual": "M08_AXI_rresp"},
"RVALID": { "actual": "M08_AXI_rvalid"},
"WDATA": { "actual": "M08_AXI_wdata"},
"WREADY": { "actual": "M08_AXI_wready"},
"WSTRB": { "actual": "M08_AXI_wstrb"},
"WVALID": { "actual": "M08_AXI_wvalid"}
}
},
"/axi_smc/M09_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "M09_AXI_araddr"},
"ARPROT": { "actual": "M09_AXI_arprot"},
"ARREADY": { "actual": "M09_AXI_arready"},
"ARVALID": { "actual": "M09_AXI_arvalid"},
"AWADDR": { "actual": "M09_AXI_awaddr"},
"AWPROT": { "actual": "M09_AXI_awprot"},
"AWREADY": { "actual": "M09_AXI_awready"},
"AWVALID": { "actual": "M09_AXI_awvalid"},
"BREADY": { "actual": "M09_AXI_bready"},
"BRESP": { "actual": "M09_AXI_bresp"},
"BVALID": { "actual": "M09_AXI_bvalid"},
"RDATA": { "actual": "M09_AXI_rdata"},
"RREADY": { "actual": "M09_AXI_rready"},
"RRESP": { "actual": "M09_AXI_rresp"},
"RVALID": { "actual": "M09_AXI_rvalid"},
"WDATA": { "actual": "M09_AXI_wdata"},
"WREADY": { "actual": "M09_AXI_wready"},
"WSTRB": { "actual": "M09_AXI_wstrb"},
"WVALID": { "actual": "M09_AXI_wvalid"}
}
},
"/axi_smc/S00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "S00_AXI_araddr"},
"ARBURST": { "actual": "S00_AXI_arburst"},
"ARCACHE": { "actual": "S00_AXI_arcache"},
"ARID": { "actual": "S00_AXI_arid"},
"ARLEN": { "actual": "S00_AXI_arlen"},
"ARLOCK": { "actual": "S00_AXI_arlock"},
"ARPROT": { "actual": "S00_AXI_arprot"},
"ARQOS": { "actual": "S00_AXI_arqos"},
"ARREADY": { "actual": "S00_AXI_arready"},
"ARSIZE": { "actual": "S00_AXI_arsize"},
"ARVALID": { "actual": "S00_AXI_arvalid"},
"AWADDR": { "actual": "S00_AXI_awaddr"},
"AWBURST": { "actual": "S00_AXI_awburst"},
"AWCACHE": { "actual": "S00_AXI_awcache"},
"AWID": { "actual": "S00_AXI_awid"},
"AWLEN": { "actual": "S00_AXI_awlen"},
"AWLOCK": { "actual": "S00_AXI_awlock"},
"AWPROT": { "actual": "S00_AXI_awprot"},
"AWQOS": { "actual": "S00_AXI_awqos"},
"AWREADY": { "actual": "S00_AXI_awready"},
"AWSIZE": { "actual": "S00_AXI_awsize"},
"AWVALID": { "actual": "S00_AXI_awvalid"},
"BID": { "actual": "S00_AXI_bid"},
"BREADY": { "actual": "S00_AXI_bready"},
"BRESP": { "actual": "S00_AXI_bresp"},
"BVALID": { "actual": "S00_AXI_bvalid"},
"RDATA": { "actual": "S00_AXI_rdata"},
"RID": { "actual": "S00_AXI_rid"},
"RLAST": { "actual": "S00_AXI_rlast"},
"RREADY": { "actual": "S00_AXI_rready"},
"RRESP": { "actual": "S00_AXI_rresp"},
"RVALID": { "actual": "S00_AXI_rvalid"},
"WDATA": { "actual": "S00_AXI_wdata"},
"WID": { "actual": "S00_AXI_wid"},
"WLAST": { "actual": "S00_AXI_wlast"},
"WREADY": { "actual": "S00_AXI_wready"},
"WSTRB": { "actual": "S00_AXI_wstrb"},
"WVALID": { "actual": "S00_AXI_wvalid"}
}
},
"/axis_data_fifo_0/M_AXIS": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "s_axis_aclk"},
"ARESETN": { "actual": "s_axis_aresetn"},
"TDATA": { "actual": "m_axis_tdata"},
"TLAST": { "actual": "m_axis_tlast"},
"TREADY": { "actual": "m_axis_tready"},
"TVALID": { "actual": "m_axis_tvalid"}
}
},
"/axis_data_fifo_0/S_AXIS": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "s_axis_aclk"},
"ARESETN": { "actual": "s_axis_aresetn"},
"TDATA": { "actual": "s_axis_tdata"},
"TLAST": { "actual": "s_axis_tlast"},
"TREADY": { "actual": "s_axis_tready"},
"TVALID": { "actual": "s_axis_tvalid"}
}
},
"/axis_data_fifo_1/M_AXIS": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "s_axis_aclk"},
"ARESETN": { "actual": "s_axis_aresetn"},
"TDATA": { "actual": "m_axis_tdata"},
"TKEEP": { "actual": "m_axis_tkeep"},
"TLAST": { "actual": "m_axis_tlast"},
"TREADY": { "actual": "m_axis_tready"},
"TVALID": { "actual": "m_axis_tvalid"}
}
},
"/axis_data_fifo_1/S_AXIS": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "s_axis_aclk"},
"ARESETN": { "actual": "s_axis_aresetn"},
"TDATA": { "actual": "s_axis_tdata"},
"TKEEP": { "actual": "s_axis_tkeep"},
"TLAST": { "actual": "s_axis_tlast"},
"TREADY": { "actual": "s_axis_tready"},
"TVALID": { "actual": "s_axis_tvalid"}
}
},
"/processing_system7_0/M_AXI_GP0": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_AXI_GP0_ACLK"},
"ARADDR": { "actual": "M_AXI_GP0_ARADDR"},
"ARBURST": { "actual": "M_AXI_GP0_ARBURST"},
"ARCACHE": { "actual": "M_AXI_GP0_ARCACHE"},
"ARID": { "actual": "M_AXI_GP0_ARID"},
"ARLEN": { "actual": "M_AXI_GP0_ARLEN"},
"ARLOCK": { "actual": "M_AXI_GP0_ARLOCK"},
"ARPROT": { "actual": "M_AXI_GP0_ARPROT"},
"ARQOS": { "actual": "M_AXI_GP0_ARQOS"},
"ARREADY": { "actual": "M_AXI_GP0_ARREADY"},
"ARSIZE": { "actual": "M_AXI_GP0_ARSIZE"},
"ARVALID": { "actual": "M_AXI_GP0_ARVALID"},
"AWADDR": { "actual": "M_AXI_GP0_AWADDR"},
"AWBURST": { "actual": "M_AXI_GP0_AWBURST"},
"AWCACHE": { "actual": "M_AXI_GP0_AWCACHE"},
"AWID": { "actual": "M_AXI_GP0_AWID"},
"AWLEN": { "actual": "M_AXI_GP0_AWLEN"},
"AWLOCK": { "actual": "M_AXI_GP0_AWLOCK"},
"AWPROT": { "actual": "M_AXI_GP0_AWPROT"},
"AWQOS": { "actual": "M_AXI_GP0_AWQOS"},
"AWREADY": { "actual": "M_AXI_GP0_AWREADY"},
"AWSIZE": { "actual": "M_AXI_GP0_AWSIZE"},
"AWVALID": { "actual": "M_AXI_GP0_AWVALID"},
"BID": { "actual": "M_AXI_GP0_BID"},
"BREADY": { "actual": "M_AXI_GP0_BREADY"},
"BRESP": { "actual": "M_AXI_GP0_BRESP"},
"BVALID": { "actual": "M_AXI_GP0_BVALID"},
"RDATA": { "actual": "M_AXI_GP0_RDATA"},
"RID": { "actual": "M_AXI_GP0_RID"},
"RLAST": { "actual": "M_AXI_GP0_RLAST"},
"RREADY": { "actual": "M_AXI_GP0_RREADY"},
"RRESP": { "actual": "M_AXI_GP0_RRESP"},
"RVALID": { "actual": "M_AXI_GP0_RVALID"},
"WDATA": { "actual": "M_AXI_GP0_WDATA"},
"WID": { "actual": "M_AXI_GP0_WID"},
"WLAST": { "actual": "M_AXI_GP0_WLAST"},
"WREADY": { "actual": "M_AXI_GP0_WREADY"},
"WSTRB": { "actual": "M_AXI_GP0_WSTRB"},
"WVALID": { "actual": "M_AXI_GP0_WVALID"}
}
},
"/processing_system7_0/S_AXI_HP0": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_AXI_HP0_ACLK"},
"ARADDR": { "actual": "S_AXI_HP0_ARADDR"},
"ARBURST": { "actual": "S_AXI_HP0_ARBURST"},
"ARCACHE": { "actual": "S_AXI_HP0_ARCACHE"},
"ARID": { "actual": "S_AXI_HP0_ARID"},
"ARLEN": { "actual": "S_AXI_HP0_ARLEN"},
"ARLOCK": { "actual": "S_AXI_HP0_ARLOCK"},
"ARPROT": { "actual": "S_AXI_HP0_ARPROT"},
"ARQOS": { "actual": "S_AXI_HP0_ARQOS"},
"ARREADY": { "actual": "S_AXI_HP0_ARREADY"},
"ARSIZE": { "actual": "S_AXI_HP0_ARSIZE"},
"ARVALID": { "actual": "S_AXI_HP0_ARVALID"},
"AWADDR": { "actual": "S_AXI_HP0_AWADDR"},
"AWBURST": { "actual": "S_AXI_HP0_AWBURST"},
"AWCACHE": { "actual": "S_AXI_HP0_AWCACHE"},
"AWID": { "actual": "S_AXI_HP0_AWID"},
"AWLEN": { "actual": "S_AXI_HP0_AWLEN"},
"AWLOCK": { "actual": "S_AXI_HP0_AWLOCK"},
"AWPROT": { "actual": "S_AXI_HP0_AWPROT"},
"AWQOS": { "actual": "S_AXI_HP0_AWQOS"},
"AWREADY": { "actual": "S_AXI_HP0_AWREADY"},
"AWSIZE": { "actual": "S_AXI_HP0_AWSIZE"},
"AWVALID": { "actual": "S_AXI_HP0_AWVALID"},
"BID": { "actual": "S_AXI_HP0_BID"},
"BREADY": { "actual": "S_AXI_HP0_BREADY"},
"BRESP": { "actual": "S_AXI_HP0_BRESP"},
"BVALID": { "actual": "S_AXI_HP0_BVALID"},
"RDATA": { "actual": "S_AXI_HP0_RDATA"},
"RID": { "actual": "S_AXI_HP0_RID"},
"RLAST": { "actual": "S_AXI_HP0_RLAST"},
"RREADY": { "actual": "S_AXI_HP0_RREADY"},
"RRESP": { "actual": "S_AXI_HP0_RRESP"},
"RVALID": { "actual": "S_AXI_HP0_RVALID"},
"WDATA": { "actual": "S_AXI_HP0_WDATA"},
"WID": { "actual": "S_AXI_HP0_WID"},
"WLAST": { "actual": "S_AXI_HP0_WLAST"},
"WREADY": { "actual": "S_AXI_HP0_WREADY"},
"WSTRB": { "actual": "S_AXI_HP0_WSTRB"},
"WVALID": { "actual": "S_AXI_HP0_WVALID"}
}
},
"/smartconnect_0/M00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "M00_AXI_araddr"},
"ARBURST": { "actual": "M00_AXI_arburst"},
"ARCACHE": { "actual": "M00_AXI_arcache"},
"ARLEN": { "actual": "M00_AXI_arlen"},
"ARLOCK": { "actual": "M00_AXI_arlock"},
"ARPROT": { "actual": "M00_AXI_arprot"},
"ARQOS": { "actual": "M00_AXI_arqos"},
"ARREADY": { "actual": "M00_AXI_arready"},
"ARSIZE": { "actual": "M00_AXI_arsize"},
"ARVALID": { "actual": "M00_AXI_arvalid"},
"AWADDR": { "actual": "M00_AXI_awaddr"},
"AWBURST": { "actual": "M00_AXI_awburst"},
"AWCACHE": { "actual": "M00_AXI_awcache"},
"AWLEN": { "actual": "M00_AXI_awlen"},
"AWLOCK": { "actual": "M00_AXI_awlock"},
"AWPROT": { "actual": "M00_AXI_awprot"},
"AWQOS": { "actual": "M00_AXI_awqos"},
"AWREADY": { "actual": "M00_AXI_awready"},
"AWSIZE": { "actual": "M00_AXI_awsize"},
"AWVALID": { "actual": "M00_AXI_awvalid"},
"BREADY": { "actual": "M00_AXI_bready"},
"BRESP": { "actual": "M00_AXI_bresp"},
"BVALID": { "actual": "M00_AXI_bvalid"},
"RDATA": { "actual": "M00_AXI_rdata"},
"RLAST": { "actual": "M00_AXI_rlast"},
"RREADY": { "actual": "M00_AXI_rready"},
"RRESP": { "actual": "M00_AXI_rresp"},
"RVALID": { "actual": "M00_AXI_rvalid"},
"WDATA": { "actual": "M00_AXI_wdata"},
"WLAST": { "actual": "M00_AXI_wlast"},
"WREADY": { "actual": "M00_AXI_wready"},
"WSTRB": { "actual": "M00_AXI_wstrb"},
"WVALID": { "actual": "M00_AXI_wvalid"}
}
},
"/smartconnect_0/S00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "S00_AXI_araddr"},
"ARBURST": { "actual": "S00_AXI_arburst"},
"ARCACHE": { "actual": "S00_AXI_arcache"},
"ARLEN": { "actual": "S00_AXI_arlen"},
"ARLOCK": { "actual": "S00_AXI_arlock"},
"ARPROT": { "actual": "S00_AXI_arprot"},
"ARQOS": { "actual": "S00_AXI_arqos"},
"ARREADY": { "actual": "S00_AXI_arready"},
"ARSIZE": { "actual": "S00_AXI_arsize"},
"ARVALID": { "actual": "S00_AXI_arvalid"},
"RDATA": { "actual": "S00_AXI_rdata"},
"RLAST": { "actual": "S00_AXI_rlast"},
"RREADY": { "actual": "S00_AXI_rready"},
"RRESP": { "actual": "S00_AXI_rresp"},
"RVALID": { "actual": "S00_AXI_rvalid"}
}
},
"/smartconnect_0/S01_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"AWADDR": { "actual": "S01_AXI_awaddr"},
"AWBURST": { "actual": "S01_AXI_awburst"},
"AWCACHE": { "actual": "S01_AXI_awcache"},
"AWLEN": { "actual": "S01_AXI_awlen"},
"AWLOCK": { "actual": "S01_AXI_awlock"},
"AWPROT": { "actual": "S01_AXI_awprot"},
"AWQOS": { "actual": "S01_AXI_awqos"},
"AWREADY": { "actual": "S01_AXI_awready"},
"AWSIZE": { "actual": "S01_AXI_awsize"},
"AWVALID": { "actual": "S01_AXI_awvalid"},
"BREADY": { "actual": "S01_AXI_bready"},
"BRESP": { "actual": "S01_AXI_bresp"},
"BVALID": { "actual": "S01_AXI_bvalid"},
"WDATA": { "actual": "S01_AXI_wdata"},
"WLAST": { "actual": "S01_AXI_wlast"},
"WREADY": { "actual": "S01_AXI_wready"},
"WSTRB": { "actual": "S01_AXI_wstrb"},
"WVALID": { "actual": "S01_AXI_wvalid"}
}
}
}
}
}
}
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xsim/vhdl.prj
+3
View File
@@ -0,0 +1,3 @@
# Do not sort compile order
nosort
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xsim/vlog.prj
+7
View File
@@ -0,0 +1,7 @@
verilog xil_defaultlib --include "C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v" \
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort
c64_pro.ip_user_files/sim_scripts/fifo_generator_0/xsim/xsim.ini
+502
View File
@@ -0,0 +1,502 @@
std=$RDI_DATADIR/xsim/vhdl/std
ieee=$RDI_DATADIR/xsim/vhdl/ieee
ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
vl=$RDI_DATADIR/xsim/vhdl/vl
synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
uvm=$RDI_DATADIR/xsim/system_verilog/uvm
secureip=$RDI_DATADIR/xsim/verilog/secureip
unisim=$RDI_DATADIR/xsim/vhdl/unisim
unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
unifast=$RDI_DATADIR/xsim/vhdl/unifast
unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2
axi_mm2s_mapper_v1_1_27=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_27
xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6
versal_cips_ps_vip_v1_0_6=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_6
xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0
fec_5g_common_v1_1_2=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_2
av_pat_gen_v2_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_1
ldpc_5gnr_lite_v1_0_0=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_0
cpm4_v1_0_12=$RDI_DATADIR/xsim/ip/cpm4_v1_0_12
ieee802d3_rs_fec_v2_0_19=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_19
oddr_v1_0_2=$RDI_DATADIR/xsim/ip/oddr_v1_0_2
tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4
c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6
c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6
axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0
xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6
picxo=$RDI_DATADIR/xsim/ip/picxo
v_warp_init_v1_1_1=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_1
srio_gen2_v4_1_17=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_17
remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
axi_sideband_util_v1_0_12=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_12
fir_compiler_v7_2_19=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_19
mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11
v_smpte_uhdsdi_v1_0_9=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_9
gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
g709_rs_encoder_v2_2_9=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_9
xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6
stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4
v_uhdsdi_audio_v2_0_6=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_6
cmac_v2_6_11=$RDI_DATADIR/xsim/ip/cmac_v2_6_11
axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0
ten_gig_eth_mac_v15_1_10=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_10
xscl=$RDI_DATADIR/xsim/ip/xscl
aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
v_smpte_uhdsdi_tx_v1_0_2=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_2
axis_combiner_v1_1_26=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_26
xdma_v4_1_23=$RDI_DATADIR/xsim/ip/xdma_v4_1_23
util_vector_logic_v2_0_2=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_2
psx_vip_v1_0_1=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_1
tmr_voter_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_4
axis_vio_v1_0_8=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_8
pcie_qdma_mailbox_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_1
axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
axi_amm_bridge_v1_0_18=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_18
axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
qdma_v5_0_3=$RDI_DATADIR/xsim/ip/qdma_v5_0_3
noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
vitis_deadlock_detector_v1_0_1=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_1
noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0
axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0
rst_vip_v1_0_4=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_4
axi_uartlite_v2_0_32=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_32
an_lt_v1_0_9=$RDI_DATADIR/xsim/ip/an_lt_v1_0_9
xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6
rs_encoder_v9_0_18=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_18
axi_dwidth_converter_v2_1_28=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_28
axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0
axi_uart16550_v2_0_30=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_30
axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
v_demosaic_v1_1_7=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_7
ll_compress_v1_1_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_1_0
dfx_decoupler_v1_0_6=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_6
emb_mem_gen_v1_0_7=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_7
pc_cfr_v7_1_0=$RDI_DATADIR/xsim/ip/pc_cfr_v7_1_0
mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7
c_counter_binary_v12_0_16=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_16
ptp_1588_timer_syncer_v2_0_4=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_4
v_warp_init_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_init_v1_0_2
axis_switch_v1_1_28=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_28
icap_arb_v1_0_1=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_1
mdm_v3_2_24=$RDI_DATADIR/xsim/ip/mdm_v3_2_24
xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6
hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1
sem_ultra_v3_1_24=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_24
v_gamma_lut_v1_1_7=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_7
axi_data_fifo_v2_1_27=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_27
util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4
sd_fec_v1_1_11=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_11
spdif_v2_0_27=$RDI_DATADIR/xsim/ip/spdif_v2_0_27
noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0
sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
axi_remapper_tx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_0
ibert_lib_v1_0_8=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_8
ernic_v4_0_1=$RDI_DATADIR/xsim/ip/ernic_v4_0_1
common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
iomodule_v3_1_8=$RDI_DATADIR/xsim/ip/iomodule_v3_1_8
rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
v_scenechange_v1_1_4=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_4
v_mix_v5_2_5=$RDI_DATADIR/xsim/ip/v_mix_v5_2_5
ieee802d3_50g_rs_fec_v2_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_15
v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0
axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0
iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
system_cache_v5_0_9=$RDI_DATADIR/xsim/ip/system_cache_v5_0_9
xxv_ethernet_v4_1_4=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_4
v_deinterlacer_v5_1_0=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_0
lmb_v10_v3_0_12=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_12
sid_v8_0_18=$RDI_DATADIR/xsim/ip/sid_v8_0_18
hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0
v_frmbuf_wr_v2_4_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_4_0
xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6
common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0
xpm_cdc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_2
dfx_bitstream_monitor_v1_0_2=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_2
xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6
rama_v1_1_14_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_14_lib
convolution_v9_0_17=$RDI_DATADIR/xsim/ip/convolution_v9_0_17
xbip_multadd_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_17
high_speed_selectio_wiz_v3_6_5=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_5
axi_iic_v2_1_4=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_4
ats_switch_v1_0_7=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_7
fast_adapter_v1_0_5=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_5
gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
v_hdmi_tx1_v1_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_5
blk_mem_gen_v8_4_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_6
soft_ecc_proxy_v1_0_2=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_2
xlconstant_v1_1_7=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_7
pc_cfr_v7_2_1=$RDI_DATADIR/xsim/ip/pc_cfr_v7_2_1
xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
hdmi_gt_controller_v1_0_11=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_11
switch_core_top_v1_0_12=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_12
lte_fft_v2_0_23=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_23
v_tpg_v8_0_11=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_11
floating_point_v7_1_15=$RDI_DATADIR/xsim/ip/floating_point_v7_1_15
hdmi_acr_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_1
v_frmbuf_rd_v2_3_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_3_3
axi_firewall_v1_2_3=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_3
axi_mmu_v2_1_26=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_26
v_tc_v6_2_6=$RDI_DATADIR/xsim/ip/v_tc_v6_2_6
ll_compress_v1_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_0_0
displayport_v7_0_0=$RDI_DATADIR/xsim/ip/displayport_v7_0_0
fc32_rs_fec_v1_0_25=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_25
bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0
v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9
xtlm=$RDI_DATADIR/xsim/ip/xtlm
dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13
sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
tmr_manager_v1_0_10=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_10
dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16
xpm=$RDI_DATADIR/xsim/ip/xpm
ft_prach_v1_1_0=$RDI_DATADIR/xsim/ip/ft_prach_v1_1_0
axi_apb_bridge_v3_0_18=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_18
axi_firewall_v1_1_7=$RDI_DATADIR/xsim/ip/axi_firewall_v1_1_7
c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6
tsn_endpoint_ethernet_mac_block_v1_0_13=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_13
axis_data_fifo_v2_0_10=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_10
lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2
microblaze_v11_0_11=$RDI_DATADIR/xsim/ip/microblaze_v11_0_11
axi_clock_converter_v2_1_27=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_27
cpri_v8_11_16=$RDI_DATADIR/xsim/ip/cpri_v8_11_16
tmr_comparator_v1_0_5=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_5
floating_point_v7_0_20=$RDI_DATADIR/xsim/ip/floating_point_v7_0_20
uhdsdi_gt_v2_1_2=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_2
flexo_100g_rs_fec_v1_0_25=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_25
pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12
quadsgmii_v3_5_12=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_12
blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6
mpram_v1_0_0=$RDI_DATADIR/xsim/ip/mpram_v1_0_0
rs_decoder_v9_0_19=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_19
v_hdmi_tx_v3_0_2=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_2
pcie_axi4lite_tap_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_1
ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
pc_cfr_v6_4_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_4_2
axis_clock_converter_v1_1_29=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_29
dprx_fec_8b10b_v1_0_1=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_1
cpm5_v1_0_12=$RDI_DATADIR/xsim/ip/cpm5_v1_0_12
vid_phy_controller_v2_1_16=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_16
axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6
emb_fifo_gen_v1_0_3=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_3
versal_cips_v3_2_5=$RDI_DATADIR/xsim/ip/versal_cips_v3_2_5
ernic_v3_1_3=$RDI_DATADIR/xsim/ip/ernic_v3_1_3
ahblite_axi_bridge_v3_0_23=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_23
ieee802d3_400g_rs_fec_v3_0_0=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_0
interlaken_v2_4_15=$RDI_DATADIR/xsim/ip/interlaken_v2_4_15
v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0
ll_compress_v2_1_1=$RDI_DATADIR/xsim/ip/ll_compress_v2_1_1
xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2
axi_emc_v3_0_28=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_28
tcc_encoder_3gpp_v5_0_19=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_19
div_gen_v5_1_19=$RDI_DATADIR/xsim/ip/div_gen_v5_1_19
emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5
axi_ethernetlite_v3_0_27=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_27
noc_nmu_phydir_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_phydir_v1_0_0
pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11
xdfe_nlf_v1_0_3=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_0_3
xdfe_fft_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_4
sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
v_multi_scaler_v1_2_3=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_3
audio_clock_recovery_unit_v1_0_2=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_2
v_hcresampler_v1_1_7=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_7
c_accum_v12_0_15=$RDI_DATADIR/xsim/ip/c_accum_v12_0_15
mpegtsmux_v1_1_6=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_6
axi_crossbar_v2_1_29=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_29
multi_channel_25g_rs_fec_v1_0_22=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_22
sim_trig_v1_0_9=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_9
axi_mcdma_v1_1_9=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_9
zynq_ultra_ps_e_vip_v1_0_14=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_14
jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14
hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3
xdfe_equalizer_v1_0_6=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_6
axi4svideo_bridge_v1_0_16=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_16
clk_gen_sim_v1_0_3=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_3
generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0
lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
axis_protocol_checker_v2_0_12=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_12
v_vscaler_v1_1_7=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_7
axi_timer_v2_0_30=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_30
axi_remapper_rx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_0
axi_gpio_v2_0_30=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_30
v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9
cmpy_v6_0_21=$RDI_DATADIR/xsim/ip/cmpy_v6_0_21
axi_interconnect_v1_7_21=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_21
hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0
canfd_v3_0_7=$RDI_DATADIR/xsim/ip/canfd_v3_0_7
xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
dfx_controller_v1_0_4=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_4
gmii_to_rgmii_v4_1_8=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_8
axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2
func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
ptp_1588_timer_syncer_v1_0_2=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v1_0_2
axi_dma_v7_1_29=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_29
bscan_axi_v1_0_0=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_0
nvme_tc_v3_0_3=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_3
ieee802d3_clause74_fec_v1_0_16=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_16
hbm2e_pl_v1_0_0=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_0
mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0
noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6
v_tpg_v8_2_2=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_2
sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
roe_framer_v3_0_6=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_6
axi_sg_v4_1_16=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_16
util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2
qdriv_pl_v1_0_10=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_10
g975_efec_i4_v1_0_19=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_19
qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0
c_addsub_v12_0_15=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_15
gtwizard_ultrascale_v1_7_16=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_16
ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0
i2s_transmitter_v1_0_6=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_6
v_axi4s_remap_v1_0_21=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_21
axi_datamover_v5_1_30=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_30
lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2
clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2
noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
displayport_v9_0_6=$RDI_DATADIR/xsim/ip/displayport_v9_0_6
v_hscaler_v1_1_7=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_7
debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
pc_cfr_v7_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v7_3_0
i2s_receiver_v1_0_6=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_6
xdfe_cc_filter_v1_1_1=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_1
nvmeha_v1_0_9=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_9
smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
axi_pcie_v2_9_9=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_9
dds_compiler_v6_0_22=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_22
microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6
axis_dwidth_converter_v1_1_27=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_27
mult_gen_v12_0_18=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_18
axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0
xfft_v9_1_9=$RDI_DATADIR/xsim/ip/xfft_v9_1_9
displayport_v8_1_6=$RDI_DATADIR/xsim/ip/displayport_v8_1_6
util_ff_v1_0_2=$RDI_DATADIR/xsim/ip/util_ff_v1_0_2
g709_rs_decoder_v2_2_11=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_11
dprx_v1_0_1=$RDI_DATADIR/xsim/ip/dprx_v1_0_1
in_system_ibert_v1_0_19=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_19
axi_tft_v2_0_26=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_26
perf_axi_tg_v1_0_10=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_10
lib_bmg_v1_0_15=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_15
bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0
lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2
dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
oran_radio_if_v3_0_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_0_0
axi_vdma_v6_3_16=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_16
vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0
v_frmbuf_rd_v2_4_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_0
dft_v4_2_5=$RDI_DATADIR/xsim/ip/dft_v4_2_5
advanced_io_wizard_v1_0_9=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_9
axi_register_slice_v2_1_28=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_28
tmr_sem_v1_0_24=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_24
noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
axi_epu_v1_0_1=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_1
noc_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_v1_0_0
axis_data_fifo_v1_1_29=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_29
aurora_8b10b_versal_v1_0_1=$RDI_DATADIR/xsim/ip/aurora_8b10b_versal_v1_0_1
axi_vfifo_ctrl_v2_0_30=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_30
rs_toolbox_v9_0_10=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_10
gtwizard_ultrascale_v1_6_14=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_14
xdfe_cc_mixer_v2_0_1=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_1
ten_gig_eth_pcs_pma_v6_0_25=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_25
xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10
v_frmbuf_rd_v2_2_7=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_7
dptx_v1_0_1=$RDI_DATADIR/xsim/ip/dptx_v1_0_1
axis_ila_adv_trig_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_0
l_ethernet_v3_3_4=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_4
v_vcresampler_v1_1_7=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_7
xdfe_common_v1_0_0=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_0
ethernet_1_10_25g_v2_7_9=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_9
vid_phy_controller_v2_2_16=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_16
v_vid_gt_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_3
axi_bram_ctrl_v4_1_8=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_8
adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
axi_msg_v1_0_9=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_9
v_warp_filter_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_0_2
sim_clk_gen_v1_0_3=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_3
etrnic_v1_1_6=$RDI_DATADIR/xsim/ip/etrnic_v1_1_6
trace_s2mm_v2_0_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_0
vitis_net_p4_v1_3_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v1_3_0
uram_rd_back_v1_0_2=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_2
noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
lmb_bram_if_cntlr_v4_0_22=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_22
vfb_v1_0_22=$RDI_DATADIR/xsim/ip/vfb_v1_0_22
sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
mipi_dphy_v4_3_6=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_6
axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0
v_mix_v5_1_7=$RDI_DATADIR/xsim/ip/v_mix_v5_1_7
axis_register_slice_v1_1_28=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_28
lib_fifo_v1_0_17=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_17
axi_protocol_converter_v2_1_28=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_28
axis_broadcaster_v1_1_27=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_27
lte_fft_v2_1_7=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_7
axi_protocol_checker_v2_0_14=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_14
x5io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_0
vby1hs_v1_0_3=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_3
axi_fifo_mm_s_v4_3_0=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_0
tsn_temac_v1_0_7=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_7
viterbi_v9_1_14=$RDI_DATADIR/xsim/ip/viterbi_v9_1_14
jesd204c_v4_2_12=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_12
g975_efec_i7_v2_0_20=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_20
v_frmbuf_wr_v2_2_7=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_7
c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6
axi_hbicap_v1_0_5=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_5
v_axi4s_remap_v1_1_7=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_7
cam_v2_5_0=$RDI_DATADIR/xsim/ip/cam_v2_5_0
axi_epc_v2_0_31=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_31
v_hdmi_phy1_v1_0_9=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_9
v_vid_gt_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v1_0_9
axi_c2c_v1_0_7=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_7
axi_memory_init_v1_0_9=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_9
processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0
ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14
proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13
xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
fifo_generator_v13_2_8=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_8
msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
v_frmbuf_wr_v2_3_3=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_3_3
interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4
tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6
v_warp_filter_v1_1_1=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_1
axi_vip_v1_1_14=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_14
axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
axi_ahblite_bridge_v3_0_25=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_25
axi_lmb_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_1
can_v5_1_0=$RDI_DATADIR/xsim/ip/can_v5_1_0
mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1
picxo_fracxo_v2_0_0=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_0
axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0
tcc_decoder_3gppmm_v2_0_24=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_24
gig_ethernet_pcs_pma_v16_2_12=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_12
xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6
axis_interconnect_v1_1_21=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_21
g709_fec_v2_4_7=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_7
hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3
advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0
tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16
mrmac_v2_1_0=$RDI_DATADIR/xsim/ip/mrmac_v2_1_0
pr_decoupler_v1_0_10=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_10
hsdp_trace_v2_0_0=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_0
xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6
axi4stream_vip_v1_1_14=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_14
ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
axi_timebase_wdt_v3_0_20=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_20
msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
axi_usb2_device_v5_0_29=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_29
ieee802d3_50g_rs_fec_v1_0_22=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_22
ieee802d3_200g_rs_fec_v2_0_9=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_9
cordic_v6_0_19=$RDI_DATADIR/xsim/ip/cordic_v6_0_19
v_smpte_sdi_v3_0_9=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_9
anlt_subcore_ip_v1_0_0=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_0
shell_utils_addr_remap_v1_0_7=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_7
axi_hwicap_v3_0_32=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_32
axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0
noc_sc_v2_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v2_0_0
compact_gt_v1_0_15=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_15
axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1
ddr4_pl_v1_0_11=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_11
videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5
axi_quad_spi_v3_2_27=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_27
ilknf_v1_3_0=$RDI_DATADIR/xsim/ip/ilknf_v1_3_0
sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
hsdp_trace_v1_0_0=$RDI_DATADIR/xsim/ip/hsdp_trace_v1_0_0
mailbox_v2_1_15=$RDI_DATADIR/xsim/ip/mailbox_v2_1_15
trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
bs_switch_v1_0_2=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_2
dfx_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_0
emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
tri_mode_ethernet_mac_v9_0_26=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_26
v_tpg_v8_1_7=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_7
axi_perf_mon_v5_0_30=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_30
axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
v_hdmi_rx_v3_0_2=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_2
processing_system7_vip_v1_0_16=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_16
v_smpte_uhdsdi_rx_v1_0_1=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_1
axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0
can_v5_0_31=$RDI_DATADIR/xsim/ip/can_v5_0_31
sem_v4_1_13=$RDI_DATADIR/xsim/ip/sem_v4_1_13
c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6
microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4
ll_compress_v2_0_1=$RDI_DATADIR/xsim/ip/ll_compress_v2_0_1
usxgmii_v1_2_11=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_11
polar_v1_0_11=$RDI_DATADIR/xsim/ip/polar_v1_0_11
xdfe_nr_prach_v2_0_0=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_0
axi_traffic_gen_v3_0_14=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_14
ieee802d3_25g_rs_fec_v1_0_27=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_27
v_letterbox_v1_1_7=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_7
ldpc_v2_0_12=$RDI_DATADIR/xsim/ip/ldpc_v2_0_12
xlconcat_v2_1_4=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_4
v_axi4s_vid_out_v4_0_16=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_16
fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6
v_dp_axi4s_vid_out_v1_0_6=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_6
mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8
lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0
axi_cdma_v4_1_28=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_28
amm_axi_bridge_v1_0_14=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_14
axi_chip2chip_v5_0_19=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_19
xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4
axi_intc_v4_1_17=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_17
mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0
cic_compiler_v4_0_16=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_16
rld3_pl_v1_0_12=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_12
jesd204_v7_2_18=$RDI_DATADIR/xsim/ip/jesd204_v7_2_18
v_hdmi_rx1_v1_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_5
ta_dma_v1_0_12=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_12
dsp_macro_v1_0_3=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_3
uhdsdi_gt_v2_0_11=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_11
v_csc_v1_1_7=$RDI_DATADIR/xsim/ip/v_csc_v1_1_7
mem_tg_v1_0_10=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_10
v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13
stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0
axis_subset_converter_v1_1_28=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_28
pc_cfr_v7_0_1=$RDI_DATADIR/xsim/ip/pc_cfr_v7_0_1
timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4
axi_pcie3_v3_0_26=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_26
aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
axi_stream_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_0
xdfe_resampler_v1_0_6=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_6
mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4
shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0
ecc_v2_0_14=$RDI_DATADIR/xsim/ip/ecc_v2_0_14
axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16
axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0
audio_formatter_v1_0_10=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_10
x5io_wizard_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_1
lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
cmac_usplus_v3_1_13=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_13
sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
video_frame_crc_v1_0_4=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_4
fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10
axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7
rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0
xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0
xfft_v7_2_14=$RDI_DATADIR/xsim/ip/xfft_v7_2_14
av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1
polar_v1_1_1=$RDI_DATADIR/xsim/ip/polar_v1_1_1
zynq_ultra_ps_e_v3_3_9=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_9
axi_ethernet_buffer_v2_0_24=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_24
v_vid_in_axi4s_v5_0_2=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_2
dcmac_v2_2_0=$RDI_DATADIR/xsim/ip/dcmac_v2_2_0
fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6