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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of AMD and is protected under U.S. and international copyright
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// and other intellectual property laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// AMD, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) AMD shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or AMD had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// AMD products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of AMD products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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// IP VLNV: xilinx.com:ip:fifo_generator:13.2
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// IP Revision: 8
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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fifo_generator_0 your_instance_name (
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.rst(rst), // input wire rst
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.wr_clk(wr_clk), // input wire wr_clk
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.rd_clk(rd_clk), // input wire rd_clk
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.din(din), // input wire [8 : 0] din
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.wr_en(wr_en), // input wire wr_en
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.rd_en(rd_en), // input wire rd_en
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.dout(dout), // output wire [8 : 0] dout
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.full(full), // output wire full
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.empty(empty), // output wire empty
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.wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy
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.rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file fifo_generator_0.v when simulating
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// the core, fifo_generator_0. When compiling the wrapper file, be sure to
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// reference the Verilog simulation library.
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@@ -0,0 +1,96 @@
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of AMD and is protected under U.S. and international copyright
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-- and other intellectual property laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- AMD, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) AMD shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
|
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or AMD had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- AMD products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of AMD products in Critical
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-- Applications, subject only to applicable laws and
|
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-- DO NOT MODIFY THIS FILE.
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-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
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-- IP Revision: 8
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-- The following code must appear in the VHDL architecture header.
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------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
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COMPONENT fifo_generator_0
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PORT (
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rst : IN STD_LOGIC;
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wr_clk : IN STD_LOGIC;
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rd_clk : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC;
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wr_rst_busy : OUT STD_LOGIC;
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rd_rst_busy : OUT STD_LOGIC
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);
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END COMPONENT;
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-- COMP_TAG_END ------ End COMPONENT Declaration ------------
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-- The following code must appear in the VHDL architecture
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-- body. Substitute your own instance name and net names.
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------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
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your_instance_name : fifo_generator_0
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PORT MAP (
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rst => rst,
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wr_clk => wr_clk,
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rd_clk => rd_clk,
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din => din,
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wr_en => wr_en,
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rd_en => rd_en,
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dout => dout,
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full => full,
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empty => empty,
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wr_rst_busy => wr_rst_busy,
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rd_rst_busy => rd_rst_busy
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);
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-- INST_TAG_END ------ End INSTANTIATION Template ---------
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-- You must compile the wrapper file fifo_generator_0.vhd when simulating
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-- the core, fifo_generator_0. When compiling the wrapper file, be sure to
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-- reference the VHDL simulation library.
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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// Date : Tue Oct 28 21:01:28 2025
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// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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// Command : write_verilog -force -mode synth_stub
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// d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_stub.v
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// Design : fifo_generator_0
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z020clg400-2
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "fifo_generator_v13_2_8,Vivado 2023.1" *)
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module fifo_generator_0(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
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empty, wr_rst_busy, rd_rst_busy)
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/* synthesis syn_black_box black_box_pad_pin="rst,din[8:0],wr_en,rd_en,dout[8:0],full,empty,wr_rst_busy,rd_rst_busy" */
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/* synthesis syn_force_seq_prim="wr_clk" */
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/* synthesis syn_force_seq_prim="rd_clk" */;
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input rst;
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input wr_clk /* synthesis syn_isclock = 1 */;
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input rd_clk /* synthesis syn_isclock = 1 */;
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input [8:0]din;
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input wr_en;
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input rd_en;
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output [8:0]dout;
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output full;
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output empty;
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output wr_rst_busy;
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output rd_rst_busy;
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endmodule
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@@ -0,0 +1,41 @@
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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-- Date : Tue Oct 28 21:01:28 2025
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-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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-- Command : write_vhdl -force -mode synth_stub
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-- d:/Project/A64/pl/a64_v0/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_stub.vhdl
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-- Design : fifo_generator_0
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7z020clg400-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity fifo_generator_0 is
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Port (
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rst : in STD_LOGIC;
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wr_clk : in STD_LOGIC;
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rd_clk : in STD_LOGIC;
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din : in STD_LOGIC_VECTOR ( 8 downto 0 );
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wr_en : in STD_LOGIC;
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rd_en : in STD_LOGIC;
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dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
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full : out STD_LOGIC;
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empty : out STD_LOGIC;
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wr_rst_busy : out STD_LOGIC;
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rd_rst_busy : out STD_LOGIC
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);
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end fifo_generator_0;
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architecture stub of fifo_generator_0 is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[8:0],wr_en,rd_en,dout[8:0],full,empty,wr_rst_busy,rd_rst_busy";
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attribute x_core_info : string;
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attribute x_core_info of stub : architecture is "fifo_generator_v13_2_8,Vivado 2023.1";
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begin
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end;
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