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chunk-sync
2026-09-11 16:18:23 +08:00
parent e4ba5f5837
commit c315cef09e
1297 changed files with 1380453 additions and 221838 deletions
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c64_pro.gen/sources_1/ip/dds_stim_16ch/synth/dds_stim_16ch.vhd
+5 -6
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@@ -1,5 +1,5 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
@@ -160,14 +160,13 @@ ARCHITECTURE dds_stim_16ch_arch OF dds_stim_16ch IS
);
END COMPONENT dds_compiler_v6_0_22;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dds_stim_16ch_arch: ARCHITECTURE IS "dds_compiler_v6_0_22,Vivado 2023.1.1";
ATTRIBUTE X_CORE_INFO OF dds_stim_16ch_arch: ARCHITECTURE IS "dds_compiler_v6_0_22,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dds_stim_16ch_arch : ARCHITECTURE IS "dds_stim_16ch,dds_compiler_v6_0_22,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dds_stim_16ch_arch: ARCHITECTURE IS "dds_stim_16ch,dds_compiler_v6_0_22,{x_ipProduct=Vivado 2023.1.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=32,C_CHANNELS=16,C_HAS_PHASE_OUT=1,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=4,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=0,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=9,C_PHASE_ANGLE_WIDTH=9" &
",C_PHASE_INCREMENT=1,C_PHASE_INCREMENT_VALUE=000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000,C_RESYNC=0,C_PHASE_OFFSET=1,C_PHASE_OFFSET_VALUE=0_0_0_" &
"0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=1,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=0,C_S_PHASE_TDATA_WIDTH=1,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=1,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=64,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=16,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=1,C_M_PHASE_TDATA_WIDTH=32,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=" &
"4}";
ATTRIBUTE CORE_GENERATION_INFO OF dds_stim_16ch_arch: ARCHITECTURE IS "dds_stim_16ch,dds_compiler_v6_0_22,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=32,C_CHANNELS=16,C_HAS_PHASE_OUT=1,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=4,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=0,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=9,C_PHASE_ANGLE_WIDTH=9,C" &
"_PHASE_INCREMENT=1,C_PHASE_INCREMENT_VALUE=000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000_000111110111010100010000,C_RESYNC=0,C_PHASE_OFFSET=1,C_PHASE_OFFSET_VALUE=0_0_0_0_" &
"0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=1,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=0,C_S_PHASE_TDATA_WIDTH=1,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=1,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=64,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=16,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=1,C_M_PHASE_TDATA_WIDTH=32,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=4}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";