sync chunk 10/12
This commit is contained in:
chunk-sync
+19
-19
@@ -2,14 +2,14 @@
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Apr 29 21:32:06 2024
|
||||
-- Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
-- Date : Thu Aug 20 13:42:44 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_sim_netlist.vhdl
|
||||
-- d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_sim_netlist.vhdl
|
||||
-- Design : design_a9_1_processing_system7_0_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z010clg400-2
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
@@ -600,7 +600,7 @@ entity design_a9_1_processing_system7_0_0_processing_system7_v5_5_processing_sys
|
||||
IRQ_P2F_SPI1 : out STD_LOGIC;
|
||||
IRQ_P2F_UART1 : out STD_LOGIC;
|
||||
IRQ_P2F_CAN1 : out STD_LOGIC;
|
||||
IRQ_F2P : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
IRQ_F2P : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
Core0_nFIQ : in STD_LOGIC;
|
||||
Core0_nIRQ : in STD_LOGIC;
|
||||
Core1_nFIQ : in STD_LOGIC;
|
||||
@@ -752,7 +752,7 @@ entity design_a9_1_processing_system7_0_0_processing_system7_v5_5_processing_sys
|
||||
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
|
||||
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of design_a9_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
|
||||
attribute C_NUM_F2P_INTR_INPUTS : integer;
|
||||
attribute C_NUM_F2P_INTR_INPUTS of design_a9_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 9;
|
||||
attribute C_NUM_F2P_INTR_INPUTS of design_a9_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 10;
|
||||
attribute C_PACKAGE_NAME : string;
|
||||
attribute C_PACKAGE_NAME of design_a9_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg400";
|
||||
attribute C_PS7_SI_REV : string;
|
||||
@@ -818,7 +818,7 @@ entity design_a9_1_processing_system7_0_0_processing_system7_v5_5_processing_sys
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of design_a9_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
|
||||
attribute POWER : string;
|
||||
attribute POWER of design_a9_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={500} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={16} clockFreq={500} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={13} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1000.000} /><PLL domain={Memory} vco={1000.000} /><PLL domain={IO} vco={1800.000} /><AXI interface={S_AXI_HP0} dataWidth={32} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
|
||||
attribute POWER of design_a9_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={700} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={16} clockFreq={500} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={5} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1400.000} /><PLL domain={Memory} vco={1000.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={32} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
|
||||
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
|
||||
attribute USE_TRACE_DATA_EDGE_DETECTOR of design_a9_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
|
||||
end design_a9_1_processing_system7_0_0_processing_system7_v5_5_processing_system7;
|
||||
@@ -3510,8 +3510,8 @@ PS7_i: unisim.vcomponents.PS7
|
||||
FTMTP2FTRIG(1) => PS7_i_n_719,
|
||||
FTMTP2FTRIG(0) => PS7_i_n_720,
|
||||
FTMTP2FTRIGACK(3 downto 0) => B"0000",
|
||||
IRQF2P(19 downto 9) => B"00000000000",
|
||||
IRQF2P(8 downto 0) => IRQ_F2P(8 downto 0),
|
||||
IRQF2P(19 downto 10) => B"0000000000",
|
||||
IRQF2P(9 downto 0) => IRQ_F2P(9 downto 0),
|
||||
IRQP2F(28) => PS7_i_n_292,
|
||||
IRQP2F(27) => PS7_i_n_293,
|
||||
IRQP2F(26) => PS7_i_n_294,
|
||||
@@ -5425,7 +5425,7 @@ entity design_a9_1_processing_system7_0_0 is
|
||||
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
IRQ_F2P : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
IRQ_F2P : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
FCLK_CLK0 : out STD_LOGIC;
|
||||
FCLK_RESET0_N : out STD_LOGIC;
|
||||
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
|
||||
@@ -5796,7 +5796,7 @@ architecture STRUCTURE of design_a9_1_processing_system7_0_0 is
|
||||
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
|
||||
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
|
||||
attribute C_NUM_F2P_INTR_INPUTS : integer;
|
||||
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 9;
|
||||
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 10;
|
||||
attribute C_PACKAGE_NAME : string;
|
||||
attribute C_PACKAGE_NAME of inst : label is "clg400";
|
||||
attribute C_PS7_SI_REV : string;
|
||||
@@ -5860,7 +5860,7 @@ architecture STRUCTURE of design_a9_1_processing_system7_0_0 is
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of inst : label is "design_a9_1_processing_system7_0_0.hwdef";
|
||||
attribute POWER : string;
|
||||
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={500} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={16} clockFreq={500} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={13} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1000.000} /><PLL domain={Memory} vco={1000.000} /><PLL domain={IO} vco={1800.000} /><AXI interface={S_AXI_HP0} dataWidth={32} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
|
||||
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={700} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={16} clockFreq={500} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={5} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1400.000} /><PLL domain={Memory} vco={1000.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={32} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
|
||||
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
|
||||
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
@@ -5877,11 +5877,11 @@ architecture STRUCTURE of design_a9_1_processing_system7_0_0 is
|
||||
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
|
||||
attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
|
||||
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
|
||||
attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
|
||||
attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
|
||||
@@ -5899,7 +5899,7 @@ architecture STRUCTURE of design_a9_1_processing_system7_0_0 is
|
||||
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
|
||||
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
|
||||
attribute X_INTERFACE_INFO of S_AXI_HP0_ACLK : signal is "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER of S_AXI_HP0_ACLK : signal is "XIL_INTERFACENAME S_AXI_HP0_ACLK, ASSOCIATED_BUSIF S_AXI_HP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_PARAMETER of S_AXI_HP0_ACLK : signal is "XIL_INTERFACENAME S_AXI_HP0_ACLK, ASSOCIATED_BUSIF S_AXI_HP0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of S_AXI_HP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY";
|
||||
attribute X_INTERFACE_INFO of S_AXI_HP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID";
|
||||
attribute X_INTERFACE_INFO of S_AXI_HP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY";
|
||||
@@ -5924,7 +5924,7 @@ architecture STRUCTURE of design_a9_1_processing_system7_0_0 is
|
||||
attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
|
||||
attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
|
||||
attribute X_INTERFACE_INFO of IRQ_F2P : signal is "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT";
|
||||
attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH, PortWidth 9";
|
||||
attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH, PortWidth 10";
|
||||
attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
|
||||
attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
|
||||
attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
|
||||
@@ -5947,7 +5947,7 @@ architecture STRUCTURE of design_a9_1_processing_system7_0_0 is
|
||||
attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
|
||||
attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
|
||||
attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
|
||||
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
|
||||
attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
|
||||
attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
|
||||
@@ -5983,7 +5983,7 @@ architecture STRUCTURE of design_a9_1_processing_system7_0_0 is
|
||||
attribute X_INTERFACE_INFO of S_AXI_HP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA";
|
||||
attribute X_INTERFACE_INFO of S_AXI_HP0_WID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID";
|
||||
attribute X_INTERFACE_INFO of S_AXI_HP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB";
|
||||
attribute X_INTERFACE_PARAMETER of S_AXI_HP0_WSTRB : signal is "XIL_INTERFACENAME S_AXI_HP0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_PARAMETER of S_AXI_HP0_WSTRB : signal is "XIL_INTERFACENAME S_AXI_HP0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL";
|
||||
begin
|
||||
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
|
||||
@@ -6172,7 +6172,7 @@ inst: entity work.design_a9_1_processing_system7_0_0_processing_system7_v5_5_pro
|
||||
I2C1_SDA_I => '0',
|
||||
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
|
||||
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
|
||||
IRQ_F2P(8 downto 0) => IRQ_F2P(8 downto 0),
|
||||
IRQ_F2P(9 downto 0) => IRQ_F2P(9 downto 0),
|
||||
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
|
||||
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
|
||||
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
|
||||
|
||||
+6
-6
@@ -2,13 +2,13 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Apr 29 21:32:06 2024
|
||||
// Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
// Date : Thu Aug 20 13:42:44 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_stub.v
|
||||
// d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_stub.v
|
||||
// Design : design_a9_1_processing_system7_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010clg400-2
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
@@ -37,7 +37,7 @@ module design_a9_1_processing_system7_0_0(USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
|
||||
S_AXI_HP0_WSTRB, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk,
|
||||
DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM,
|
||||
DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
|
||||
/* synthesis syn_black_box black_box_pad_pin="USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[31:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[31:0],S_AXI_HP0_WSTRB[3:0],IRQ_F2P[8:0],FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */
|
||||
/* synthesis syn_black_box black_box_pad_pin="USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[31:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[31:0],S_AXI_HP0_WSTRB[3:0],IRQ_F2P[9:0],FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */
|
||||
/* synthesis syn_force_seq_prim="M_AXI_GP0_ACLK" */
|
||||
/* synthesis syn_force_seq_prim="S_AXI_HP0_ACLK" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK0" */;
|
||||
@@ -128,7 +128,7 @@ module design_a9_1_processing_system7_0_0(USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
|
||||
input [5:0]S_AXI_HP0_WID;
|
||||
input [31:0]S_AXI_HP0_WDATA;
|
||||
input [3:0]S_AXI_HP0_WSTRB;
|
||||
input [8:0]IRQ_F2P;
|
||||
input [9:0]IRQ_F2P;
|
||||
output FCLK_CLK0 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_RESET0_N;
|
||||
inout [53:0]MIO;
|
||||
|
||||
+6
-6
@@ -2,13 +2,13 @@
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Apr 29 21:32:06 2024
|
||||
-- Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
-- Date : Thu Aug 20 13:42:44 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_stub.vhdl
|
||||
-- d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_stub.vhdl
|
||||
-- Design : design_a9_1_processing_system7_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010clg400-2
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
@@ -102,7 +102,7 @@ entity design_a9_1_processing_system7_0_0 is
|
||||
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
IRQ_F2P : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
IRQ_F2P : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
FCLK_CLK0 : out STD_LOGIC;
|
||||
FCLK_RESET0_N : out STD_LOGIC;
|
||||
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
|
||||
@@ -134,7 +134,7 @@ architecture stub of design_a9_1_processing_system7_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[31:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[31:0],S_AXI_HP0_WSTRB[3:0],IRQ_F2P[8:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
|
||||
attribute black_box_pad_pin of stub : architecture is "USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[31:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[31:0],S_AXI_HP0_WSTRB[3:0],IRQ_F2P[9:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2023.1";
|
||||
begin
|
||||
|
||||
BIN
Binary file not shown.
+5
-5
@@ -149,13 +149,13 @@
|
||||
// CR #682573
|
||||
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
|
||||
//------------------------------------------------------------------------------
|
||||
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={500} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={16} clockFreq={500} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={13} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1000.000} /><PLL domain={Memory} vco={1000.000} /><PLL domain={IO} vco={1800.000} /><AXI interface={S_AXI_HP0} dataWidth={32} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
|
||||
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={700} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={16} clockFreq={500} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={5} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1400.000} /><PLL domain={Memory} vco={1000.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={32} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
|
||||
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=500, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.0, PCW_UIPARAM_DDR_BOARD_DELAY0=0.25, PCW_UIPARAM_DDR_BOARD_DELAY1=0.25, PCW_UIPARAM_DDR_BOARD_DELAY2=0.25, PCW_UIPARAM_DDR_BOARD_DELAY3=0.25, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\
|
||||
, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50, PCW_APU_PERIPHERAL_FREQMHZ=500, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=100, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=1, PCW_ARMPLL_CTRL_FBDIV=20, PCW_IOPLL_CTRL_FBDIV=36, PCW_DDRPLL_CTRL_FBDIV=20, PCW_CPU_CPU_PLL_FREQMHZ=1000.000, PCW_IO_IO_PLL_FREQMHZ=1800.000, PCW_DDR_DDR_PLL_FREQMHZ=1000.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100\
|
||||
, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50, PCW_APU_PERIPHERAL_FREQMHZ=700, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=100, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=28, PCW_IOPLL_CTRL_FBDIV=20, PCW_DDRPLL_CTRL_FBDIV=20, PCW_CPU_CPU_PLL_FREQMHZ=1400.000, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1000.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100\
|
||||
, PCW_M_AXI_GP1_FREQMHZ=100, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=100, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=32, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3 (Low Voltage), PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=16 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K256M16 RE-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0\
|
||||
, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_SINGLE_QSPI_DATA_MODE=x4, PCW_ENET0_PERIPHERAL_ENABLE=0, PCW_ENET0_GRP_MDIO_ENABLE=0, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 16 .. 21, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=1, PCW_SD1_SD1_IO=MIO 22 .. 27, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=1, PCW_UART0_UART0_IO=MIO 10 .. 11, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 12 .. 13, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0\
|
||||
, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 40, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low\
|
||||
, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
|
||||
, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_SINGLE_QSPI_DATA_MODE=x4, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=1, PCW_ENET0_RESET_IO=MIO 0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=1, PCW_SD1_SD1_IO=MIO 46 .. 51, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=1, PCW_UART0_UART0_IO=MIO 10 .. 11, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 8 .. 9, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0\
|
||||
, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 40, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL\
|
||||
, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
|
||||
(* HW_HANDOFF = "design_a9_1_processing_system7_0_0.hwdef" *)
|
||||
|
||||
module processing_system7_v5_5_processing_system7
|
||||
|
||||
+930
-672
File diff suppressed because it is too large
Load Diff
+4
-4
@@ -70,20 +70,20 @@ extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 500000000
|
||||
#define APU_FREQ 700000000
|
||||
#define DDR_FREQ 500000000
|
||||
#define DCI_FREQ 10204082
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 100000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 83333336
|
||||
#define WDT_FREQ 83333333
|
||||
#define I2C_FREQ 116666664
|
||||
#define WDT_FREQ 116666664
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
|
||||
+3726
-990
File diff suppressed because it is too large
Load Diff
+133
-112
@@ -1,7 +1,7 @@
|
||||
proc ps7_pll_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x001F42C0
|
||||
mask_write 0XF8000100 0x0007F000 0x00014000
|
||||
mask_write 0XF8000110 0x003FFFF0 0x0015E2C0
|
||||
mask_write 0XF8000100 0x0007F000 0x0001C000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
@@ -16,8 +16,8 @@ proc ps7_pll_init_data_3_0 {} {
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x00113220
|
||||
mask_write 0XF8000108 0x0007F000 0x00024000
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001F42C0
|
||||
mask_write 0XF8000108 0x0007F000 0x00014000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
@@ -28,13 +28,15 @@ proc ps7_pll_init_data_3_0 {} {
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00203101
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000150 0x00003F33 0x00001203
|
||||
mask_write 0XF8000154 0x00003F33 0x00001203
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00300600
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC0C0D
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC084D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
@@ -146,26 +148,26 @@ proc ps7_mio_init_data_3_0 {} {
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000724 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000720 0x00003FFF 0x000006E0
|
||||
mask_write 0XF8000724 0x00003FFF 0x000016E1
|
||||
mask_write 0XF8000728 0x00003FFF 0x000016E1
|
||||
mask_write 0XF800072C 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000730 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000734 0x00003FFF 0x000016E1
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001600
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001280
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001280
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001280
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000600
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000770 0x00003FFF 0x00001204
|
||||
mask_write 0XF8000774 0x00003FFF 0x00001205
|
||||
mask_write 0XF8000778 0x00003FFF 0x00001204
|
||||
@@ -184,15 +186,14 @@ proc ps7_mio_init_data_3_0 {} {
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C4 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000830 0x003F003F 0x00380037
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007C0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007C4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000834 0x003F003F 0x003A0039
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
@@ -219,6 +220,12 @@ proc ps7_peripherals_init_data_3_0 {} {
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xFEFF0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xFEFF0100
|
||||
mask_write 0XE000A204 0xFFFFFFFF 0x00000001
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFE0001
|
||||
mask_write 0XE000A208 0xFFFFFFFF 0x00000001
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFE0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFE0001
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
@@ -235,8 +242,8 @@ proc ps7_debug_3_0 {} {
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x001F42C0
|
||||
mask_write 0XF8000100 0x0007F000 0x00014000
|
||||
mask_write 0XF8000110 0x003FFFF0 0x0015E2C0
|
||||
mask_write 0XF8000100 0x0007F000 0x0001C000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
@@ -251,8 +258,8 @@ proc ps7_pll_init_data_2_0 {} {
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x00113220
|
||||
mask_write 0XF8000108 0x0007F000 0x00024000
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001F42C0
|
||||
mask_write 0XF8000108 0x0007F000 0x00014000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
@@ -263,13 +270,15 @@ proc ps7_pll_init_data_2_0 {} {
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00203101
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000150 0x00003F33 0x00001203
|
||||
mask_write 0XF8000154 0x00003F33 0x00001203
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00300600
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC0C0D
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC084D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
@@ -382,26 +391,26 @@ proc ps7_mio_init_data_2_0 {} {
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000724 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000720 0x00003FFF 0x000006E0
|
||||
mask_write 0XF8000724 0x00003FFF 0x000016E1
|
||||
mask_write 0XF8000728 0x00003FFF 0x000016E1
|
||||
mask_write 0XF800072C 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000730 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000734 0x00003FFF 0x000016E1
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001600
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001280
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001280
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001280
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000600
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000770 0x00003FFF 0x00001204
|
||||
mask_write 0XF8000774 0x00003FFF 0x00001205
|
||||
mask_write 0XF8000778 0x00003FFF 0x00001204
|
||||
@@ -420,15 +429,14 @@ proc ps7_mio_init_data_2_0 {} {
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C4 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000830 0x003F003F 0x00380037
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007C0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007C4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000834 0x003F003F 0x003A0039
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
@@ -455,6 +463,12 @@ proc ps7_peripherals_init_data_2_0 {} {
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xFEFF0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xFEFF0100
|
||||
mask_write 0XE000A204 0xFFFFFFFF 0x00000001
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFE0001
|
||||
mask_write 0XE000A208 0xFFFFFFFF 0x00000001
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFE0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFE0001
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
@@ -471,8 +485,8 @@ proc ps7_debug_2_0 {} {
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x001F42C0
|
||||
mask_write 0XF8000100 0x0007F000 0x00014000
|
||||
mask_write 0XF8000110 0x003FFFF0 0x0015E2C0
|
||||
mask_write 0XF8000100 0x0007F000 0x0001C000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
@@ -487,8 +501,8 @@ proc ps7_pll_init_data_1_0 {} {
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x00113220
|
||||
mask_write 0XF8000108 0x0007F000 0x00024000
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001F42C0
|
||||
mask_write 0XF8000108 0x0007F000 0x00014000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
@@ -499,13 +513,15 @@ proc ps7_pll_init_data_1_0 {} {
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00203101
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000150 0x00003F33 0x00001203
|
||||
mask_write 0XF8000154 0x00003F33 0x00001203
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00300600
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC0C0D
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC084D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
@@ -616,26 +632,26 @@ proc ps7_mio_init_data_1_0 {} {
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000724 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000720 0x00003FFF 0x000006E0
|
||||
mask_write 0XF8000724 0x00003FFF 0x000016E1
|
||||
mask_write 0XF8000728 0x00003FFF 0x000016E1
|
||||
mask_write 0XF800072C 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000730 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000734 0x00003FFF 0x000016E1
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001600
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001280
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001280
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001280
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000600
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000770 0x00003FFF 0x00001204
|
||||
mask_write 0XF8000774 0x00003FFF 0x00001205
|
||||
mask_write 0XF8000778 0x00003FFF 0x00001204
|
||||
@@ -654,15 +670,14 @@ proc ps7_mio_init_data_1_0 {} {
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C4 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000830 0x003F003F 0x00380037
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007C0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007C4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000834 0x003F003F 0x003A0039
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
@@ -689,6 +704,12 @@ proc ps7_peripherals_init_data_1_0 {} {
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xFEFF0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xFEFF0100
|
||||
mask_write 0XE000A204 0xFFFFFFFF 0x00000001
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFE0001
|
||||
mask_write 0XE000A208 0xFFFFFFFF 0x00000001
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFE0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFE0001
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
@@ -706,7 +727,7 @@ proc ps7_debug_1_0 {} {
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 500000000
|
||||
set APU_FREQ 700000000
|
||||
|
||||
|
||||
|
||||
|
||||
+930
-672
File diff suppressed because it is too large
Load Diff
+4
-4
@@ -84,20 +84,20 @@ extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 500000000
|
||||
#define APU_FREQ 700000000
|
||||
#define DDR_FREQ 500000000
|
||||
#define DCI_FREQ 10204082
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 100000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 83333336
|
||||
#define WDT_FREQ 83333333
|
||||
#define I2C_FREQ 116666664
|
||||
#define WDT_FREQ 116666664
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
|
||||
+47
-47
@@ -4,8 +4,8 @@
|
||||
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
|
||||
<PARAMETERS >
|
||||
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
|
||||
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="500" />
|
||||
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="20" />
|
||||
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="700" />
|
||||
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="28" />
|
||||
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
|
||||
@@ -22,7 +22,7 @@
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1000.000" />
|
||||
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1400.000" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
@@ -52,16 +52,16 @@
|
||||
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="MIO 52 .. 53" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="MIO 0" />
|
||||
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
|
||||
@@ -72,17 +72,17 @@
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
@@ -128,10 +128,10 @@
|
||||
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="36" />
|
||||
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1800.000" />
|
||||
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="20" />
|
||||
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000" />
|
||||
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
|
||||
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow" />
|
||||
@@ -143,35 +143,35 @@
|
||||
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="slow" />
|
||||
@@ -179,35 +179,35 @@
|
||||
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow" />
|
||||
@@ -319,7 +319,7 @@
|
||||
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
|
||||
@@ -343,7 +343,7 @@
|
||||
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow" />
|
||||
@@ -400,9 +400,9 @@
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="9" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
|
||||
@@ -419,18 +419,18 @@
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="9" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="MIO 16 .. 21" />
|
||||
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="0" />
|
||||
@@ -438,9 +438,9 @@
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="MIO 22 .. 27" />
|
||||
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="MIO 46 .. 51" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="18" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="x4" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
@@ -517,9 +517,9 @@
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 12 .. 13" />
|
||||
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 8 .. 9" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="18" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
|
||||
|
||||
+306
-31
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -128,10 +128,37 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
// 'M_AXI_GP0' transactor parameters
|
||||
xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
|
||||
M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
M_AXI_GP0_transactor_param_props.addLong("FREQ_HZ", "100000000");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ID_WIDTH", "12");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
|
||||
M_AXI_GP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_QOS", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_READ_THREADS", "4");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
|
||||
M_AXI_GP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
M_AXI_GP0_transactor_param_props.addString("PROTOCOL", "AXI3");
|
||||
M_AXI_GP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
M_AXI_GP0_transactor_param_props.addString("CLK_DOMAIN", "design_a9_1_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
|
||||
|
||||
@@ -192,8 +219,8 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
|
||||
// M_AXI_GP0' transactor sockets
|
||||
|
||||
mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
|
||||
mp_impl->M_AXI_GP0_rd_socket->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
|
||||
mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -207,10 +234,38 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
|
||||
// 'S_AXI_HP0' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_HP0_transactor_param_props;
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_HP0_transactor_param_props.addLong("FREQ_HZ", "100000000");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ID_WIDTH", "6");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
|
||||
S_AXI_HP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_QOS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
S_AXI_HP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
S_AXI_HP0_transactor_param_props.addString("PROTOCOL", "AXI3");
|
||||
S_AXI_HP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_HP0_transactor_param_props.addString("CLK_DOMAIN", "design_a9_1_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_HP0_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>("S_AXI_HP0_transactor", S_AXI_HP0_transactor_param_props);
|
||||
|
||||
@@ -271,8 +326,8 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
|
||||
// S_AXI_HP0' transactor sockets
|
||||
|
||||
mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
|
||||
mp_impl->S_AXI_HP0_rd_socket->bind(*(mp_S_AXI_HP0_transactor->rd_socket));
|
||||
mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -353,10 +408,37 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
// 'M_AXI_GP0' transactor parameters
|
||||
xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
|
||||
M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
M_AXI_GP0_transactor_param_props.addLong("FREQ_HZ", "100000000");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ID_WIDTH", "12");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
|
||||
M_AXI_GP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_QOS", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_READ_THREADS", "4");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
|
||||
M_AXI_GP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
M_AXI_GP0_transactor_param_props.addString("PROTOCOL", "AXI3");
|
||||
M_AXI_GP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
M_AXI_GP0_transactor_param_props.addString("CLK_DOMAIN", "design_a9_1_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
|
||||
|
||||
@@ -417,8 +499,8 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
|
||||
// M_AXI_GP0' transactor sockets
|
||||
|
||||
mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
|
||||
mp_impl->M_AXI_GP0_rd_socket->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
|
||||
mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -432,10 +514,38 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
|
||||
// 'S_AXI_HP0' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_HP0_transactor_param_props;
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_HP0_transactor_param_props.addLong("FREQ_HZ", "100000000");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ID_WIDTH", "6");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
|
||||
S_AXI_HP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_QOS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
S_AXI_HP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
S_AXI_HP0_transactor_param_props.addString("PROTOCOL", "AXI3");
|
||||
S_AXI_HP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_HP0_transactor_param_props.addString("CLK_DOMAIN", "design_a9_1_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_HP0_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>("S_AXI_HP0_transactor", S_AXI_HP0_transactor_param_props);
|
||||
|
||||
@@ -496,8 +606,8 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
|
||||
// S_AXI_HP0' transactor sockets
|
||||
|
||||
mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
|
||||
mp_impl->S_AXI_HP0_rd_socket->bind(*(mp_S_AXI_HP0_transactor->rd_socket));
|
||||
mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -578,10 +688,37 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
// 'M_AXI_GP0' transactor parameters
|
||||
xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
|
||||
M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
M_AXI_GP0_transactor_param_props.addLong("FREQ_HZ", "100000000");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ID_WIDTH", "12");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
|
||||
M_AXI_GP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_QOS", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_READ_THREADS", "4");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
|
||||
M_AXI_GP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
M_AXI_GP0_transactor_param_props.addString("PROTOCOL", "AXI3");
|
||||
M_AXI_GP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
M_AXI_GP0_transactor_param_props.addString("CLK_DOMAIN", "design_a9_1_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
|
||||
|
||||
@@ -642,8 +779,8 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
|
||||
// M_AXI_GP0' transactor sockets
|
||||
|
||||
mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
|
||||
mp_impl->M_AXI_GP0_rd_socket->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
|
||||
mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -657,10 +794,38 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
|
||||
// 'S_AXI_HP0' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_HP0_transactor_param_props;
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_HP0_transactor_param_props.addLong("FREQ_HZ", "100000000");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ID_WIDTH", "6");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
|
||||
S_AXI_HP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_QOS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
S_AXI_HP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
S_AXI_HP0_transactor_param_props.addString("PROTOCOL", "AXI3");
|
||||
S_AXI_HP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_HP0_transactor_param_props.addString("CLK_DOMAIN", "design_a9_1_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_HP0_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>("S_AXI_HP0_transactor", S_AXI_HP0_transactor_param_props);
|
||||
|
||||
@@ -721,8 +886,8 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
|
||||
// S_AXI_HP0' transactor sockets
|
||||
|
||||
mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
|
||||
mp_impl->S_AXI_HP0_rd_socket->bind(*(mp_S_AXI_HP0_transactor->rd_socket));
|
||||
mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -792,10 +957,37 @@ design_a9_1_processing_system7_0_0::design_a9_1_processing_system7_0_0(const sc_
|
||||
// configure M_AXI_GP0_transactor
|
||||
xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
|
||||
M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
M_AXI_GP0_transactor_param_props.addLong("FREQ_HZ", "100000000");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ID_WIDTH", "12");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
|
||||
M_AXI_GP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_QOS", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_READ_THREADS", "4");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
|
||||
M_AXI_GP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
M_AXI_GP0_transactor_param_props.addString("PROTOCOL", "AXI3");
|
||||
M_AXI_GP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
M_AXI_GP0_transactor_param_props.addString("CLK_DOMAIN", "design_a9_1_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
|
||||
mp_M_AXI_GP0_transactor->ARVALID(M_AXI_GP0_ARVALID);
|
||||
@@ -852,10 +1044,38 @@ design_a9_1_processing_system7_0_0::design_a9_1_processing_system7_0_0(const sc_
|
||||
mp_M_AXI_GP0_transactor->RST(m_M_AXI_GP0_transactor_rst_signal);
|
||||
// configure S_AXI_HP0_transactor
|
||||
xsc::common_cpp::properties S_AXI_HP0_transactor_param_props;
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_HP0_transactor_param_props.addLong("FREQ_HZ", "100000000");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ID_WIDTH", "6");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
|
||||
S_AXI_HP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_QOS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
S_AXI_HP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
S_AXI_HP0_transactor_param_props.addString("PROTOCOL", "AXI3");
|
||||
S_AXI_HP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_HP0_transactor_param_props.addString("CLK_DOMAIN", "design_a9_1_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_HP0_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>("S_AXI_HP0_transactor", S_AXI_HP0_transactor_param_props);
|
||||
mp_S_AXI_HP0_transactor->ARREADY(S_AXI_HP0_ARREADY);
|
||||
@@ -924,8 +1144,8 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
// configure 'M_AXI_GP0' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_a9_1_processing_system7_0_0", "M_AXI_GP0_TLM_MODE") != 1)
|
||||
{
|
||||
mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
|
||||
mp_impl->M_AXI_GP0_rd_socket->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
|
||||
mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
|
||||
|
||||
}
|
||||
else
|
||||
@@ -940,8 +1160,8 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
// configure 'S_AXI_HP0' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_a9_1_processing_system7_0_0", "S_AXI_HP0_TLM_MODE") != 1)
|
||||
{
|
||||
mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
|
||||
mp_impl->S_AXI_HP0_rd_socket->bind(*(mp_S_AXI_HP0_transactor->rd_socket));
|
||||
mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
|
||||
|
||||
}
|
||||
else
|
||||
@@ -1017,10 +1237,37 @@ design_a9_1_processing_system7_0_0::design_a9_1_processing_system7_0_0(const sc_
|
||||
// configure M_AXI_GP0_transactor
|
||||
xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
|
||||
M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
M_AXI_GP0_transactor_param_props.addLong("FREQ_HZ", "100000000");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ID_WIDTH", "12");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
|
||||
M_AXI_GP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_QOS", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_READ_THREADS", "4");
|
||||
M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
|
||||
M_AXI_GP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
M_AXI_GP0_transactor_param_props.addString("PROTOCOL", "AXI3");
|
||||
M_AXI_GP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
M_AXI_GP0_transactor_param_props.addString("CLK_DOMAIN", "design_a9_1_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
|
||||
mp_M_AXI_GP0_transactor->ARVALID(M_AXI_GP0_ARVALID);
|
||||
@@ -1077,10 +1324,38 @@ design_a9_1_processing_system7_0_0::design_a9_1_processing_system7_0_0(const sc_
|
||||
mp_M_AXI_GP0_transactor->RST(m_M_AXI_GP0_transactor_rst_signal);
|
||||
// configure S_AXI_HP0_transactor
|
||||
xsc::common_cpp::properties S_AXI_HP0_transactor_param_props;
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_HP0_transactor_param_props.addLong("FREQ_HZ", "100000000");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ID_WIDTH", "6");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
|
||||
S_AXI_HP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_QOS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_HP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
S_AXI_HP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_HP0_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
S_AXI_HP0_transactor_param_props.addString("PROTOCOL", "AXI3");
|
||||
S_AXI_HP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_HP0_transactor_param_props.addString("CLK_DOMAIN", "design_a9_1_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_HP0_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>("S_AXI_HP0_transactor", S_AXI_HP0_transactor_param_props);
|
||||
mp_S_AXI_HP0_transactor->ARREADY(S_AXI_HP0_ARREADY);
|
||||
@@ -1149,8 +1424,8 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
// configure 'M_AXI_GP0' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_a9_1_processing_system7_0_0", "M_AXI_GP0_TLM_MODE") != 1)
|
||||
{
|
||||
mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
|
||||
mp_impl->M_AXI_GP0_rd_socket->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
|
||||
mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
|
||||
|
||||
}
|
||||
else
|
||||
@@ -1165,8 +1440,8 @@ void design_a9_1_processing_system7_0_0::before_end_of_elaboration()
|
||||
// configure 'S_AXI_HP0' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_a9_1_processing_system7_0_0", "S_AXI_HP0_TLM_MODE") != 1)
|
||||
{
|
||||
mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
|
||||
mp_impl->S_AXI_HP0_rd_socket->bind(*(mp_S_AXI_HP0_transactor->rd_socket));
|
||||
mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
|
||||
|
||||
}
|
||||
else
|
||||
|
||||
+6
-6
@@ -2,7 +2,7 @@
|
||||
#define IP_DESIGN_A9_1_PROCESSING_SYSTEM7_0_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -167,7 +167,7 @@ public:
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<9> > IRQ_F2P;
|
||||
sc_core::sc_in< sc_dt::sc_bv<10> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
@@ -325,7 +325,7 @@ public:
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<9> > IRQ_F2P;
|
||||
sc_core::sc_in< sc_dt::sc_bv<10> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<54> > MIO;
|
||||
@@ -483,7 +483,7 @@ public:
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<9> > IRQ_F2P;
|
||||
sc_core::sc_in< sc_dt::sc_bv<10> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
@@ -645,7 +645,7 @@ public:
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<9> > IRQ_F2P;
|
||||
sc_core::sc_in< sc_dt::sc_bv<10> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
@@ -815,7 +815,7 @@ public:
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<9> > IRQ_F2P;
|
||||
sc_core::sc_in< sc_dt::sc_bv<10> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
|
||||
+11
-3
@@ -576,7 +576,7 @@
|
||||
bit IRQ_P2F_SPI1;
|
||||
bit IRQ_P2F_UART1;
|
||||
bit IRQ_P2F_CAN1;
|
||||
bit [8 : 0] IRQ_F2P;
|
||||
bit [9 : 0] IRQ_F2P;
|
||||
bit Core0_nFIQ;
|
||||
bit Core0_nIRQ;
|
||||
bit Core1_nFIQ;
|
||||
@@ -823,7 +823,7 @@
|
||||
parameter C_S_AXI_HP3_DATA_WIDTH = 64;
|
||||
parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12;
|
||||
parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12;
|
||||
parameter C_NUM_F2P_INTR_INPUTS = 9;
|
||||
parameter C_NUM_F2P_INTR_INPUTS = 10;
|
||||
parameter C_IRQ_F2P_MODE = "DIRECT";
|
||||
parameter C_DQ_WIDTH = 32;
|
||||
parameter C_DQS_WIDTH = 4;
|
||||
@@ -938,7 +938,7 @@
|
||||
input [5 : 0] S_AXI_HP0_WID;
|
||||
input [31 : 0] S_AXI_HP0_WDATA;
|
||||
input [3 : 0] S_AXI_HP0_WSTRB;
|
||||
input [8 : 0] IRQ_F2P;
|
||||
input [9 : 0] IRQ_F2P;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_RESET0_N;
|
||||
inout [53 : 0] MIO;
|
||||
@@ -1295,6 +1295,14 @@ always@(negedge IRQ_F2P[8])
|
||||
begin
|
||||
ps7_set_input_IRQ_F2P(8,0);
|
||||
end
|
||||
always@(posedge IRQ_F2P[9])
|
||||
begin
|
||||
ps7_set_input_IRQ_F2P(9,1);
|
||||
end
|
||||
always@(negedge IRQ_F2P[9])
|
||||
begin
|
||||
ps7_set_input_IRQ_F2P(9,0);
|
||||
end
|
||||
|
||||
always@(posedge M_AXI_GP0_ACLK)
|
||||
begin
|
||||
|
||||
+1
-1
@@ -255,7 +255,7 @@ input [5 : 0] S_AXI_HP0_AWID;
|
||||
input [5 : 0] S_AXI_HP0_WID;
|
||||
input [31 : 0] S_AXI_HP0_WDATA;
|
||||
input [3 : 0] S_AXI_HP0_WSTRB;
|
||||
input [8 : 0] IRQ_F2P;
|
||||
input [9 : 0] IRQ_F2P;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_RESET0_N;
|
||||
input [53 : 0] MIO;
|
||||
|
||||
+4
-4
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -92,7 +92,7 @@ design_a9_1_processing_system7_0_0_sc::design_a9_1_processing_system7_0_0_sc(con
|
||||
model_param_props.addLong("C_S_AXI_HP3_DATA_WIDTH", "64");
|
||||
model_param_props.addLong("C_M_AXI_GP0_THREAD_ID_WIDTH", "12");
|
||||
model_param_props.addLong("C_M_AXI_GP1_THREAD_ID_WIDTH", "12");
|
||||
model_param_props.addLong("C_NUM_F2P_INTR_INPUTS", "9");
|
||||
model_param_props.addLong("C_NUM_F2P_INTR_INPUTS", "10");
|
||||
model_param_props.addLong("C_DQ_WIDTH", "32");
|
||||
model_param_props.addLong("C_DQS_WIDTH", "4");
|
||||
model_param_props.addLong("C_DM_WIDTH", "4");
|
||||
@@ -122,10 +122,10 @@ design_a9_1_processing_system7_0_0_sc::design_a9_1_processing_system7_0_0_sc(con
|
||||
mp_impl = new processing_system7_v5_5_tlm("inst", model_param_props);
|
||||
|
||||
// initialize AXI sockets
|
||||
M_AXI_GP0_wr_socket = mp_impl->M_AXI_GP0_wr_socket;
|
||||
M_AXI_GP0_rd_socket = mp_impl->M_AXI_GP0_rd_socket;
|
||||
S_AXI_HP0_wr_socket = mp_impl->S_AXI_HP0_wr_socket;
|
||||
M_AXI_GP0_wr_socket = mp_impl->M_AXI_GP0_wr_socket;
|
||||
S_AXI_HP0_rd_socket = mp_impl->S_AXI_HP0_rd_socket;
|
||||
S_AXI_HP0_wr_socket = mp_impl->S_AXI_HP0_wr_socket;
|
||||
}
|
||||
|
||||
design_a9_1_processing_system7_0_0_sc::~design_a9_1_processing_system7_0_0_sc()
|
||||
|
||||
+3
-3
@@ -2,7 +2,7 @@
|
||||
#define IP_DESIGN_A9_1_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -76,10 +76,10 @@ public:
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
+3
-3
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -153,7 +153,7 @@ module design_a9_1_processing_system7_0_0 (
|
||||
input bit [5 : 0] S_AXI_HP0_WID,
|
||||
input bit [31 : 0] S_AXI_HP0_WDATA,
|
||||
input bit [3 : 0] S_AXI_HP0_WSTRB,
|
||||
input bit [8 : 0] IRQ_F2P,
|
||||
input bit [9 : 0] IRQ_F2P,
|
||||
output bit_as_bool FCLK_CLK0,
|
||||
output bit_as_bool FCLK_RESET0_N,
|
||||
output bit [53 : 0] MIO,
|
||||
@@ -273,7 +273,7 @@ module design_a9_1_processing_system7_0_0 (USB0_PORT_INDCTL,USB0_VBUS_PWRSELECT,
|
||||
input bit [5 : 0] S_AXI_HP0_WID;
|
||||
input bit [31 : 0] S_AXI_HP0_WDATA;
|
||||
input bit [3 : 0] S_AXI_HP0_WSTRB;
|
||||
input bit [8 : 0] IRQ_F2P;
|
||||
input bit [9 : 0] IRQ_F2P;
|
||||
output wire FCLK_CLK0;
|
||||
output wire FCLK_RESET0_N;
|
||||
inout wire [53 : 0] MIO;
|
||||
|
||||
+1
-1
@@ -145,7 +145,7 @@ class processing_system7_v5_5_tlm : public sc_core::sc_module {
|
||||
sc_core::sc_in<bool> S_AXI_HP0_ACLK;
|
||||
sc_core::sc_in<bool> S_AXI_HP0_RDISSUECAP1_EN;
|
||||
sc_core::sc_in<bool> S_AXI_HP0_WRISSUECAP1_EN;
|
||||
sc_core::sc_in<sc_dt::sc_bv<9> > IRQ_F2P;
|
||||
sc_core::sc_in<sc_dt::sc_bv<10> > IRQ_F2P;
|
||||
sc_core::sc_out<bool> FCLK_CLK0;
|
||||
sc_core::sc_out<bool> FCLK_RESET0_N;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
|
||||
|
||||
+13
-13
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -54,8 +54,8 @@
|
||||
(* CHECK_LICENSE_TYPE = "design_a9_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
|
||||
(* CORE_GENERATION_INFO = "design_a9_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS\
|
||||
_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=32,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=1\
|
||||
2,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=9,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=1,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIABLE\
|
||||
_TXN=1,C_GP1_EN_MODIFIABLE_TXN=1}" *)
|
||||
2,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=10,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=1,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIABL\
|
||||
E_TXN=1,C_GP1_EN_MODIFIABLE_TXN=1}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_a9_1_processing_system7_0_0 (
|
||||
USB0_PORT_INDCTL,
|
||||
@@ -231,7 +231,7 @@ output wire [3 : 0] M_AXI_GP0_AWLEN;
|
||||
output wire [3 : 0] M_AXI_GP0_AWQOS;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
|
||||
output wire [3 : 0] M_AXI_GP0_WSTRB;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
|
||||
input wire M_AXI_GP0_ACLK;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
|
||||
@@ -254,8 +254,8 @@ input wire [11 : 0] M_AXI_GP0_RID;
|
||||
input wire [1 : 0] M_AXI_GP0_BRESP;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
|
||||
input wire [1 : 0] M_AXI_GP0_RRESP;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_T\
|
||||
HREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR\
|
||||
EADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
|
||||
input wire [31 : 0] M_AXI_GP0_RDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY" *)
|
||||
@@ -288,7 +288,7 @@ output wire [7 : 0] S_AXI_HP0_WCOUNT;
|
||||
output wire [2 : 0] S_AXI_HP0_RACOUNT;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WACOUNT" *)
|
||||
output wire [5 : 0] S_AXI_HP0_WACOUNT;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_HP0_ACLK, ASSOCIATED_BUSIF S_AXI_HP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_HP0_ACLK, ASSOCIATED_BUSIF S_AXI_HP0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK" *)
|
||||
input wire S_AXI_HP0_ACLK;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID" *)
|
||||
@@ -347,14 +347,14 @@ input wire [5 : 0] S_AXI_HP0_AWID;
|
||||
input wire [5 : 0] S_AXI_HP0_WID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *)
|
||||
input wire [31 : 0] S_AXI_HP0_WDATA;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_HP0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_TH\
|
||||
READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_HP0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THRE\
|
||||
ADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *)
|
||||
input wire [3 : 0] S_AXI_HP0_WSTRB;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH, PortWidth 9" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH, PortWidth 10" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
|
||||
input wire [8 : 0] IRQ_F2P;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
input wire [9 : 0] IRQ_F2P;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
|
||||
output wire FCLK_CLK0;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -437,7 +437,7 @@ inout wire PS_PORB;
|
||||
.C_S_AXI_HP3_DATA_WIDTH(64),
|
||||
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
|
||||
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
|
||||
.C_NUM_F2P_INTR_INPUTS(9),
|
||||
.C_NUM_F2P_INTR_INPUTS(10),
|
||||
.C_IRQ_F2P_MODE("DIRECT"),
|
||||
.C_DQ_WIDTH(32),
|
||||
.C_DQS_WIDTH(4),
|
||||
|
||||
BIN
Binary file not shown.
+17
-17
@@ -43,7 +43,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -398,11 +398,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:56:04 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Jul 02 09:34:13 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3ad677f8</spirit:value>
|
||||
<spirit:value>9:2202a3a3</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -416,11 +416,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Jul 02 09:34:02 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3ad677f8</spirit:value>
|
||||
<spirit:value>9:2202a3a3</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -434,11 +434,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Jul 02 09:34:02 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3ad677f8</spirit:value>
|
||||
<spirit:value>9:2202a3a3</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -457,11 +457,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:cf9683b7</spirit:value>
|
||||
<spirit:value>9:692eded8</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -477,11 +477,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Jul 02 09:34:02 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:cf9683b7</spirit:value>
|
||||
<spirit:value>9:692eded8</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -500,11 +500,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Jul 02 09:34:02 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3ad677f8</spirit:value>
|
||||
<spirit:value>9:2202a3a3</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -520,11 +520,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Jul 02 09:34:02 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3ad677f8</spirit:value>
|
||||
<spirit:value>9:2202a3a3</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -950,7 +950,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
@@ -967,7 +967,7 @@
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1.1</xilinx:xilinxVersion>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
# (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
|
||||
+4
-4
@@ -2,14 +2,14 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Sep 7 19:18:22 2023
|
||||
// Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
// Date : Tue Oct 28 21:00:58 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top design_a9_1_rst_ps7_0_50M_0 -prefix
|
||||
// design_a9_1_rst_ps7_0_50M_0_ design_a9_1_rst_ps7_0_50M_0_sim_netlist.v
|
||||
// Design : design_a9_1_rst_ps7_0_50M_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z010clg400-2
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
@@ -221,7 +221,7 @@ module design_a9_1_rst_ps7_0_50M_0
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
|
||||
|
||||
+4
-4
@@ -2,14 +2,14 @@
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Thu Sep 7 19:18:22 2023
|
||||
-- Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
-- Date : Tue Oct 28 21:00:58 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top design_a9_1_rst_ps7_0_50M_0 -prefix
|
||||
-- design_a9_1_rst_ps7_0_50M_0_ design_a9_1_rst_ps7_0_50M_0_sim_netlist.vhdl
|
||||
-- Design : design_a9_1_rst_ps7_0_50M_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z010clg400-2
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
@@ -1099,7 +1099,7 @@ architecture STRUCTURE of design_a9_1_rst_ps7_0_50M_0 is
|
||||
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
|
||||
+3
-3
@@ -2,13 +2,13 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Sep 7 19:18:22 2023
|
||||
// Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
// Date : Tue Oct 28 21:00:58 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top design_a9_1_rst_ps7_0_50M_0 -prefix
|
||||
// design_a9_1_rst_ps7_0_50M_0_ design_a9_1_rst_ps7_0_50M_0_stub.v
|
||||
// Design : design_a9_1_rst_ps7_0_50M_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010clg400-2
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
|
||||
+3
-3
@@ -2,13 +2,13 @@
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Thu Sep 7 19:18:22 2023
|
||||
-- Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
-- Date : Tue Oct 28 21:00:58 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top design_a9_1_rst_ps7_0_50M_0 -prefix
|
||||
-- design_a9_1_rst_ps7_0_50M_0_ design_a9_1_rst_ps7_0_50M_0_stub.vhdl
|
||||
-- Design : design_a9_1_rst_ps7_0_50M_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010clg400-2
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
+2
-2
@@ -1,5 +1,5 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
@@ -117,7 +117,7 @@ ARCHITECTURE design_a9_1_rst_ps7_0_50M_0_arch OF design_a9_1_rst_ps7_0_50M_0 IS
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
|
||||
+2
-2
@@ -1,5 +1,5 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
@@ -123,7 +123,7 @@ ARCHITECTURE design_a9_1_rst_ps7_0_50M_0_arch OF design_a9_1_rst_ps7_0_50M_0 IS
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
|
||||
+2662
-78
File diff suppressed because it is too large
Load Diff
+4
-4
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_962a" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1714397434"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1714397434"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1714397434"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1714397434"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1787204487"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1787204487"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1787204487"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1787204487"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\bd_962a.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
|
||||
+144
@@ -74,6 +74,42 @@ module bd_962a_wrapper
|
||||
S01_AXI_wready,
|
||||
S01_AXI_wstrb,
|
||||
S01_AXI_wvalid,
|
||||
S02_AXI_awaddr,
|
||||
S02_AXI_awburst,
|
||||
S02_AXI_awcache,
|
||||
S02_AXI_awlen,
|
||||
S02_AXI_awlock,
|
||||
S02_AXI_awprot,
|
||||
S02_AXI_awqos,
|
||||
S02_AXI_awready,
|
||||
S02_AXI_awsize,
|
||||
S02_AXI_awvalid,
|
||||
S02_AXI_bready,
|
||||
S02_AXI_bresp,
|
||||
S02_AXI_bvalid,
|
||||
S02_AXI_wdata,
|
||||
S02_AXI_wlast,
|
||||
S02_AXI_wready,
|
||||
S02_AXI_wstrb,
|
||||
S02_AXI_wvalid,
|
||||
S03_AXI_awaddr,
|
||||
S03_AXI_awburst,
|
||||
S03_AXI_awcache,
|
||||
S03_AXI_awlen,
|
||||
S03_AXI_awlock,
|
||||
S03_AXI_awprot,
|
||||
S03_AXI_awqos,
|
||||
S03_AXI_awready,
|
||||
S03_AXI_awsize,
|
||||
S03_AXI_awvalid,
|
||||
S03_AXI_bready,
|
||||
S03_AXI_bresp,
|
||||
S03_AXI_bvalid,
|
||||
S03_AXI_wdata,
|
||||
S03_AXI_wlast,
|
||||
S03_AXI_wready,
|
||||
S03_AXI_wstrb,
|
||||
S03_AXI_wvalid,
|
||||
aclk,
|
||||
aresetn);
|
||||
output [31:0]M00_AXI_araddr;
|
||||
@@ -142,6 +178,42 @@ module bd_962a_wrapper
|
||||
output S01_AXI_wready;
|
||||
input [3:0]S01_AXI_wstrb;
|
||||
input S01_AXI_wvalid;
|
||||
input [31:0]S02_AXI_awaddr;
|
||||
input [1:0]S02_AXI_awburst;
|
||||
input [3:0]S02_AXI_awcache;
|
||||
input [7:0]S02_AXI_awlen;
|
||||
input [0:0]S02_AXI_awlock;
|
||||
input [2:0]S02_AXI_awprot;
|
||||
input [3:0]S02_AXI_awqos;
|
||||
output S02_AXI_awready;
|
||||
input [2:0]S02_AXI_awsize;
|
||||
input S02_AXI_awvalid;
|
||||
input S02_AXI_bready;
|
||||
output [1:0]S02_AXI_bresp;
|
||||
output S02_AXI_bvalid;
|
||||
input [31:0]S02_AXI_wdata;
|
||||
input S02_AXI_wlast;
|
||||
output S02_AXI_wready;
|
||||
input [3:0]S02_AXI_wstrb;
|
||||
input S02_AXI_wvalid;
|
||||
input [31:0]S03_AXI_awaddr;
|
||||
input [1:0]S03_AXI_awburst;
|
||||
input [3:0]S03_AXI_awcache;
|
||||
input [7:0]S03_AXI_awlen;
|
||||
input [0:0]S03_AXI_awlock;
|
||||
input [2:0]S03_AXI_awprot;
|
||||
input [3:0]S03_AXI_awqos;
|
||||
output S03_AXI_awready;
|
||||
input [2:0]S03_AXI_awsize;
|
||||
input S03_AXI_awvalid;
|
||||
input S03_AXI_bready;
|
||||
output [1:0]S03_AXI_bresp;
|
||||
output S03_AXI_bvalid;
|
||||
input [31:0]S03_AXI_wdata;
|
||||
input S03_AXI_wlast;
|
||||
output S03_AXI_wready;
|
||||
input [3:0]S03_AXI_wstrb;
|
||||
input S03_AXI_wvalid;
|
||||
input aclk;
|
||||
input aresetn;
|
||||
|
||||
@@ -211,6 +283,42 @@ module bd_962a_wrapper
|
||||
wire S01_AXI_wready;
|
||||
wire [3:0]S01_AXI_wstrb;
|
||||
wire S01_AXI_wvalid;
|
||||
wire [31:0]S02_AXI_awaddr;
|
||||
wire [1:0]S02_AXI_awburst;
|
||||
wire [3:0]S02_AXI_awcache;
|
||||
wire [7:0]S02_AXI_awlen;
|
||||
wire [0:0]S02_AXI_awlock;
|
||||
wire [2:0]S02_AXI_awprot;
|
||||
wire [3:0]S02_AXI_awqos;
|
||||
wire S02_AXI_awready;
|
||||
wire [2:0]S02_AXI_awsize;
|
||||
wire S02_AXI_awvalid;
|
||||
wire S02_AXI_bready;
|
||||
wire [1:0]S02_AXI_bresp;
|
||||
wire S02_AXI_bvalid;
|
||||
wire [31:0]S02_AXI_wdata;
|
||||
wire S02_AXI_wlast;
|
||||
wire S02_AXI_wready;
|
||||
wire [3:0]S02_AXI_wstrb;
|
||||
wire S02_AXI_wvalid;
|
||||
wire [31:0]S03_AXI_awaddr;
|
||||
wire [1:0]S03_AXI_awburst;
|
||||
wire [3:0]S03_AXI_awcache;
|
||||
wire [7:0]S03_AXI_awlen;
|
||||
wire [0:0]S03_AXI_awlock;
|
||||
wire [2:0]S03_AXI_awprot;
|
||||
wire [3:0]S03_AXI_awqos;
|
||||
wire S03_AXI_awready;
|
||||
wire [2:0]S03_AXI_awsize;
|
||||
wire S03_AXI_awvalid;
|
||||
wire S03_AXI_bready;
|
||||
wire [1:0]S03_AXI_bresp;
|
||||
wire S03_AXI_bvalid;
|
||||
wire [31:0]S03_AXI_wdata;
|
||||
wire S03_AXI_wlast;
|
||||
wire S03_AXI_wready;
|
||||
wire [3:0]S03_AXI_wstrb;
|
||||
wire S03_AXI_wvalid;
|
||||
wire aclk;
|
||||
wire aresetn;
|
||||
|
||||
@@ -281,6 +389,42 @@ module bd_962a_wrapper
|
||||
.S01_AXI_wready(S01_AXI_wready),
|
||||
.S01_AXI_wstrb(S01_AXI_wstrb),
|
||||
.S01_AXI_wvalid(S01_AXI_wvalid),
|
||||
.S02_AXI_awaddr(S02_AXI_awaddr),
|
||||
.S02_AXI_awburst(S02_AXI_awburst),
|
||||
.S02_AXI_awcache(S02_AXI_awcache),
|
||||
.S02_AXI_awlen(S02_AXI_awlen),
|
||||
.S02_AXI_awlock(S02_AXI_awlock),
|
||||
.S02_AXI_awprot(S02_AXI_awprot),
|
||||
.S02_AXI_awqos(S02_AXI_awqos),
|
||||
.S02_AXI_awready(S02_AXI_awready),
|
||||
.S02_AXI_awsize(S02_AXI_awsize),
|
||||
.S02_AXI_awvalid(S02_AXI_awvalid),
|
||||
.S02_AXI_bready(S02_AXI_bready),
|
||||
.S02_AXI_bresp(S02_AXI_bresp),
|
||||
.S02_AXI_bvalid(S02_AXI_bvalid),
|
||||
.S02_AXI_wdata(S02_AXI_wdata),
|
||||
.S02_AXI_wlast(S02_AXI_wlast),
|
||||
.S02_AXI_wready(S02_AXI_wready),
|
||||
.S02_AXI_wstrb(S02_AXI_wstrb),
|
||||
.S02_AXI_wvalid(S02_AXI_wvalid),
|
||||
.S03_AXI_awaddr(S03_AXI_awaddr),
|
||||
.S03_AXI_awburst(S03_AXI_awburst),
|
||||
.S03_AXI_awcache(S03_AXI_awcache),
|
||||
.S03_AXI_awlen(S03_AXI_awlen),
|
||||
.S03_AXI_awlock(S03_AXI_awlock),
|
||||
.S03_AXI_awprot(S03_AXI_awprot),
|
||||
.S03_AXI_awqos(S03_AXI_awqos),
|
||||
.S03_AXI_awready(S03_AXI_awready),
|
||||
.S03_AXI_awsize(S03_AXI_awsize),
|
||||
.S03_AXI_awvalid(S03_AXI_awvalid),
|
||||
.S03_AXI_bready(S03_AXI_bready),
|
||||
.S03_AXI_bresp(S03_AXI_bresp),
|
||||
.S03_AXI_bvalid(S03_AXI_bvalid),
|
||||
.S03_AXI_wdata(S03_AXI_wdata),
|
||||
.S03_AXI_wlast(S03_AXI_wlast),
|
||||
.S03_AXI_wready(S03_AXI_wready),
|
||||
.S03_AXI_wstrb(S03_AXI_wstrb),
|
||||
.S03_AXI_wvalid(S03_AXI_wvalid),
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn));
|
||||
endmodule
|
||||
|
||||
+11707
-297
File diff suppressed because it is too large
Load Diff
+1
-1
@@ -20,7 +20,7 @@
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
|
||||
+13
-13
@@ -13,7 +13,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:c9e4e5ad</spirit:value>
|
||||
<spirit:value>9:d13031f6</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -29,11 +29,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:32 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:22 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a1e0d0d4</spirit:value>
|
||||
<spirit:value>9:07588dbb</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
@@ -53,11 +53,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:32 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:22 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a1e0d0d4</spirit:value>
|
||||
<spirit:value>9:07588dbb</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
@@ -77,11 +77,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a1e0d0d4</spirit:value>
|
||||
<spirit:value>9:07588dbb</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -97,11 +97,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:32 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:22 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a1e0d0d4</spirit:value>
|
||||
<spirit:value>9:07588dbb</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -117,11 +117,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:c9e4e5ad</spirit:value>
|
||||
<spirit:value>9:d13031f6</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -137,11 +137,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:32 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:22 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:c9e4e5ad</spirit:value>
|
||||
<spirit:value>9:d13031f6</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
|
||||
+2
-2
@@ -35,7 +35,7 @@
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
@@ -77,7 +77,7 @@
|
||||
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+13
-13
@@ -43,7 +43,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -398,11 +398,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:32 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:22 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:843f2b46</spirit:value>
|
||||
<spirit:value>9:789e77ee</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -413,7 +413,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:843f2b46</spirit:value>
|
||||
<spirit:value>9:789e77ee</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -432,11 +432,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e4a9e18f</spirit:value>
|
||||
<spirit:value>9:3902251b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -452,11 +452,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:32 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:22 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e4a9e18f</spirit:value>
|
||||
<spirit:value>9:3902251b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -475,11 +475,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:32 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:22 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:843f2b46</spirit:value>
|
||||
<spirit:value>9:789e77ee</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -495,11 +495,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:32 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:22 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:843f2b46</spirit:value>
|
||||
<spirit:value>9:789e77ee</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -879,7 +879,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
|
||||
+2
-2
@@ -1,5 +1,5 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
@@ -117,7 +117,7 @@ ARCHITECTURE bd_962a_psr_aclk_0_arch OF bd_962a_psr_aclk_0 IS
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
|
||||
+2
-2
@@ -1,5 +1,5 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
@@ -123,7 +123,7 @@ ARCHITECTURE bd_962a_psr_aclk_0_arch OF bd_962a_psr_aclk_0 IS
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
|
||||
+18
-18
@@ -10,11 +10,11 @@
|
||||
"component_parameters": {
|
||||
"READ_WRITE_MODE": [ { "value": "READ_ONLY", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_ID_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_RDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_WDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ID_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_RDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_WDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ARUSER_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -23,16 +23,16 @@
|
||||
"SC_WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MSC_ROUTE_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SSC_ROUTE_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SSC_ROUTE_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "bd_962a_s00a2s_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -41,18 +41,18 @@
|
||||
"C_SC_AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MSC_ROUTE_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SSC_ROUTE_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AWPAYLD_WIDTH": [ { "value": "140", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_ARPAYLD_WIDTH": [ { "value": "140", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_SSC_ROUTE_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AWPAYLD_WIDTH": [ { "value": "142", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_ARPAYLD_WIDTH": [ { "value": "142", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_WPAYLD_WIDTH": [ { "value": "52", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_RPAYLD_WIDTH": [ { "value": "53", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_BPAYLD_WIDTH": [ { "value": "7", "resolve_type": "dependent", "format": "long", "usage": "all" } ]
|
||||
"C_RPAYLD_WIDTH": [ { "value": "56", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_BPAYLD_WIDTH": [ { "value": "10", "resolve_type": "dependent", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
@@ -79,13 +79,13 @@
|
||||
"s_sc_r_info": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_r_send": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_sc_r_recv": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_sc_r_payld": [ { "direction": "in", "size_left": "52", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_r_payld": [ { "direction": "in", "size_left": "55", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_sc_ar_req": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"m_sc_ar_info": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_sc_ar_send": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"m_sc_ar_recv": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_sc_ar_payld": [ { "direction": "out", "size_left": "139", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_sc_ar_payld": [ { "direction": "out", "size_left": "141", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arid": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||
@@ -95,7 +95,7 @@
|
||||
"s_axi_aruser": [ { "direction": "in", "size_left": "1023", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rid": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rlast": [ { "direction": "out" } ],
|
||||
@@ -136,7 +136,7 @@
|
||||
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -157,7 +157,7 @@
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -193,7 +193,7 @@
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+32
-32
@@ -627,7 +627,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">3</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -816,7 +816,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -920,7 +920,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -975,7 +975,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:ed3fcaa6</spirit:value>
|
||||
<spirit:value>9:440b88eb</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -994,11 +994,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:17f56b96</spirit:value>
|
||||
<spirit:value>9:3ce7346c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1014,11 +1014,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:23 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:17f56b96</spirit:value>
|
||||
<spirit:value>9:3ce7346c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1037,11 +1037,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:ed3fcaa6</spirit:value>
|
||||
<spirit:value>9:440b88eb</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1057,11 +1057,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:23 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:ed3fcaa6</spirit:value>
|
||||
<spirit:value>9:440b88eb</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1153,7 +1153,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_RPAYLD_WIDTH')) - 1)">52</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_RPAYLD_WIDTH')) - 1)">55</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1269,7 +1269,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_BPAYLD_WIDTH')) - 1)">6</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_BPAYLD_WIDTH')) - 1)">9</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1364,7 +1364,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ARPAYLD_WIDTH')) - 1)">139</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ARPAYLD_WIDTH')) - 1)">141</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1480,7 +1480,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AWPAYLD_WIDTH')) - 1)">139</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AWPAYLD_WIDTH')) - 1)">141</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1630,7 +1630,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2036,7 +2036,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2151,7 +2151,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2410,7 +2410,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2574,7 +2574,7 @@
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_AXI_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>AXI_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_AXI_RDATA_WIDTH</spirit:name>
|
||||
@@ -2594,7 +2594,7 @@
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_SC_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>SC_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SC_ID_WIDTH" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SC_ID_WIDTH" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_SC_RDATA_WIDTH</spirit:name>
|
||||
@@ -2639,15 +2639,15 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_SSC_ROUTE_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_SSC_ROUTE_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_AWPAYLD_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_AWPAYLD_WIDTH" spirit:dependency="(((((102 + spirit:decode(id('MODELPARAM_VALUE.C_SC_ADDR_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_MSC_ROUTE_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_AWUSER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_AWUSER_WIDTH'))))">140</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_AWPAYLD_WIDTH" spirit:dependency="(((((102 + spirit:decode(id('MODELPARAM_VALUE.C_SC_ADDR_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_MSC_ROUTE_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_AWUSER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_AWUSER_WIDTH'))))">142</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_ARPAYLD_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_ARPAYLD_WIDTH" spirit:dependency="(((((102 + spirit:decode(id('MODELPARAM_VALUE.C_SC_ADDR_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_MSC_ROUTE_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ARUSER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ARUSER_WIDTH'))))">140</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_ARPAYLD_WIDTH" spirit:dependency="(((((102 + spirit:decode(id('MODELPARAM_VALUE.C_SC_ADDR_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_MSC_ROUTE_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ARUSER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ARUSER_WIDTH'))))">142</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_WPAYLD_WIDTH</spirit:name>
|
||||
@@ -2655,11 +2655,11 @@
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_RPAYLD_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_RPAYLD_WIDTH" spirit:dependency="((((17 + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH'))) + spirit:decode(id('MODELPARAM_VALUE.C_SC_RDATA_WIDTH'))) + (spirit:decode(id('MODELPARAM_VALUE.C_SC_RUSER_BITS_PER_BYTE')) * (spirit:decode(id('MODELPARAM_VALUE.C_SC_RDATA_WIDTH')) / 8)))">53</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_RPAYLD_WIDTH" spirit:dependency="((((17 + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH'))) + spirit:decode(id('MODELPARAM_VALUE.C_SC_RDATA_WIDTH'))) + (spirit:decode(id('MODELPARAM_VALUE.C_SC_RUSER_BITS_PER_BYTE')) * (spirit:decode(id('MODELPARAM_VALUE.C_SC_RDATA_WIDTH')) / 8)))">56</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_BPAYLD_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_BPAYLD_WIDTH" spirit:dependency="(((2 + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_BUSER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_BUSER_WIDTH'))))">7</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_BPAYLD_WIDTH" spirit:dependency="(((2 + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_BUSER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_BUSER_WIDTH'))))">10</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
@@ -2807,7 +2807,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>AXI_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>AXI_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_WIDTH" spirit:order="4" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_WIDTH" spirit:order="4" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>AXI_RDATA_WIDTH</spirit:name>
|
||||
@@ -2827,7 +2827,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>SC_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>SC_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SC_ID_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SC_ID_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SC_RDATA_WIDTH</spirit:name>
|
||||
@@ -2872,7 +2872,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>SSC_ROUTE_WIDTH</spirit:name>
|
||||
<spirit:displayName>SSC_ROUTE_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SSC_ROUTE_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SSC_ROUTE_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
@@ -2894,7 +2894,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
@@ -2917,7 +2917,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
|
||||
+17
-17
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -84,7 +84,7 @@ module bd_962a_s00a2s_0 (
|
||||
s_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R REQ" *)
|
||||
@@ -96,7 +96,7 @@ input wire s_sc_r_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R RECV" *)
|
||||
output wire s_sc_r_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R PAYLD" *)
|
||||
input wire [52 : 0] s_sc_r_payld;
|
||||
input wire [55 : 0] s_sc_r_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR REQ" *)
|
||||
output wire m_sc_ar_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR INFO" *)
|
||||
@@ -106,9 +106,9 @@ output wire m_sc_ar_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR RECV" *)
|
||||
input wire m_sc_ar_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR PAYLD" *)
|
||||
output wire [139 : 0] m_sc_ar_payld;
|
||||
output wire [141 : 0] m_sc_ar_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [1 : 0] s_axi_arid;
|
||||
input wire [2 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
@@ -128,7 +128,7 @@ input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [1 : 0] s_axi_rid;
|
||||
output wire [2 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
@@ -139,18 +139,18 @@ output wire s_axi_rlast;
|
||||
output wire [1023 : 0] s_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 1024, WUSER_WIDTH 0, RUSER_WIDTH 1024, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_\
|
||||
THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 1024, WUSER_WIDTH 0, RUSER_WIDTH 1024, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_TH\
|
||||
READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
|
||||
sc_axi2sc_v1_0_8_top #(
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ID_WIDTH(2),
|
||||
.C_AXI_ID_WIDTH(3),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_SC_ADDR_WIDTH(32),
|
||||
.C_SC_ID_WIDTH(2),
|
||||
.C_SC_ID_WIDTH(3),
|
||||
.C_SC_RDATA_WIDTH(32),
|
||||
.C_SC_WDATA_WIDTH(32),
|
||||
.C_SC_RUSER_BITS_PER_BYTE(0),
|
||||
@@ -159,12 +159,12 @@ input wire s_axi_rready;
|
||||
.C_SC_AWUSER_WIDTH(0),
|
||||
.C_SC_BUSER_WIDTH(0),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_SSC_ROUTE_WIDTH(2),
|
||||
.C_AWPAYLD_WIDTH(140),
|
||||
.C_ARPAYLD_WIDTH(140),
|
||||
.C_SSC_ROUTE_WIDTH(4),
|
||||
.C_AWPAYLD_WIDTH(142),
|
||||
.C_ARPAYLD_WIDTH(142),
|
||||
.C_WPAYLD_WIDTH(52),
|
||||
.C_RPAYLD_WIDTH(53),
|
||||
.C_BPAYLD_WIDTH(7)
|
||||
.C_RPAYLD_WIDTH(56),
|
||||
.C_BPAYLD_WIDTH(10)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.s_sc_r_req(s_sc_r_req),
|
||||
@@ -176,7 +176,7 @@ input wire s_axi_rready;
|
||||
.s_sc_b_info(1'D0),
|
||||
.s_sc_b_send(1'D0),
|
||||
.s_sc_b_recv(),
|
||||
.s_sc_b_payld(7'D0),
|
||||
.s_sc_b_payld(10'D0),
|
||||
.m_sc_ar_req(m_sc_ar_req),
|
||||
.m_sc_ar_info(m_sc_ar_info),
|
||||
.m_sc_ar_send(m_sc_ar_send),
|
||||
@@ -192,7 +192,7 @@ input wire s_axi_rready;
|
||||
.m_sc_w_send(),
|
||||
.m_sc_w_recv(1'D0),
|
||||
.m_sc_w_payld(),
|
||||
.s_axi_awid(2'H0),
|
||||
.s_axi_awid(3'H0),
|
||||
.s_axi_awaddr(32'H00000000),
|
||||
.s_axi_awlen(8'H0),
|
||||
.s_axi_awlock(1'H0),
|
||||
|
||||
+19
-19
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -52,8 +52,8 @@
|
||||
|
||||
(* X_CORE_INFO = "sc_axi2sc_v1_0_8_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_s00a2s_0,sc_axi2sc_v1_0_8_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_s00a2s_0,sc_axi2sc_v1_0_8_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_axi2sc,x_ipVersion=1.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_AXI_ADDR_WIDTH=32,C_AXI_ID_WIDTH=2,C_AXI_RDATA_WIDTH=32,C_AXI_WDATA_WIDTH=32,C_SC_ADDR_WIDTH=32,C_SC_ID_WIDTH=2,C_SC_RDATA_WIDTH=32,C_SC_WDATA_WIDTH=32,C_SC_RUSER_BITS_PER_BYTE=0,C_SC_WUSER_BITS_PER_BYTE=0,C_SC_ARUSER_WIDTH=0,C_SC_AWUSER_WIDTH=0,C_SC_BUSER_WIDTH=0,C_MSC_ROUTE_WIDTH=1,C_SSC_ROUTE_WI\
|
||||
DTH=2,C_AWPAYLD_WIDTH=140,C_ARPAYLD_WIDTH=140,C_WPAYLD_WIDTH=52,C_RPAYLD_WIDTH=53,C_BPAYLD_WIDTH=7}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_s00a2s_0,sc_axi2sc_v1_0_8_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_axi2sc,x_ipVersion=1.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_AXI_ADDR_WIDTH=32,C_AXI_ID_WIDTH=3,C_AXI_RDATA_WIDTH=32,C_AXI_WDATA_WIDTH=32,C_SC_ADDR_WIDTH=32,C_SC_ID_WIDTH=3,C_SC_RDATA_WIDTH=32,C_SC_WDATA_WIDTH=32,C_SC_RUSER_BITS_PER_BYTE=0,C_SC_WUSER_BITS_PER_BYTE=0,C_SC_ARUSER_WIDTH=0,C_SC_AWUSER_WIDTH=0,C_SC_BUSER_WIDTH=0,C_MSC_ROUTE_WIDTH=1,C_SSC_ROUTE_WI\
|
||||
DTH=4,C_AWPAYLD_WIDTH=142,C_ARPAYLD_WIDTH=142,C_WPAYLD_WIDTH=52,C_RPAYLD_WIDTH=56,C_BPAYLD_WIDTH=10}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_s00a2s_0 (
|
||||
aclk,
|
||||
@@ -86,7 +86,7 @@ module bd_962a_s00a2s_0 (
|
||||
s_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R REQ" *)
|
||||
@@ -98,7 +98,7 @@ input wire s_sc_r_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R RECV" *)
|
||||
output wire s_sc_r_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R PAYLD" *)
|
||||
input wire [52 : 0] s_sc_r_payld;
|
||||
input wire [55 : 0] s_sc_r_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR REQ" *)
|
||||
output wire m_sc_ar_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR INFO" *)
|
||||
@@ -108,9 +108,9 @@ output wire m_sc_ar_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR RECV" *)
|
||||
input wire m_sc_ar_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR PAYLD" *)
|
||||
output wire [139 : 0] m_sc_ar_payld;
|
||||
output wire [141 : 0] m_sc_ar_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [1 : 0] s_axi_arid;
|
||||
input wire [2 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
@@ -130,7 +130,7 @@ input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [1 : 0] s_axi_rid;
|
||||
output wire [2 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
@@ -141,18 +141,18 @@ output wire s_axi_rlast;
|
||||
output wire [1023 : 0] s_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 1024, WUSER_WIDTH 0, RUSER_WIDTH 1024, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_\
|
||||
THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 1024, WUSER_WIDTH 0, RUSER_WIDTH 1024, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_TH\
|
||||
READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
|
||||
sc_axi2sc_v1_0_8_top #(
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ID_WIDTH(2),
|
||||
.C_AXI_ID_WIDTH(3),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_SC_ADDR_WIDTH(32),
|
||||
.C_SC_ID_WIDTH(2),
|
||||
.C_SC_ID_WIDTH(3),
|
||||
.C_SC_RDATA_WIDTH(32),
|
||||
.C_SC_WDATA_WIDTH(32),
|
||||
.C_SC_RUSER_BITS_PER_BYTE(0),
|
||||
@@ -161,12 +161,12 @@ input wire s_axi_rready;
|
||||
.C_SC_AWUSER_WIDTH(0),
|
||||
.C_SC_BUSER_WIDTH(0),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_SSC_ROUTE_WIDTH(2),
|
||||
.C_AWPAYLD_WIDTH(140),
|
||||
.C_ARPAYLD_WIDTH(140),
|
||||
.C_SSC_ROUTE_WIDTH(4),
|
||||
.C_AWPAYLD_WIDTH(142),
|
||||
.C_ARPAYLD_WIDTH(142),
|
||||
.C_WPAYLD_WIDTH(52),
|
||||
.C_RPAYLD_WIDTH(53),
|
||||
.C_BPAYLD_WIDTH(7)
|
||||
.C_RPAYLD_WIDTH(56),
|
||||
.C_BPAYLD_WIDTH(10)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.s_sc_r_req(s_sc_r_req),
|
||||
@@ -178,7 +178,7 @@ input wire s_axi_rready;
|
||||
.s_sc_b_info(1'D0),
|
||||
.s_sc_b_send(1'D0),
|
||||
.s_sc_b_recv(),
|
||||
.s_sc_b_payld(7'D0),
|
||||
.s_sc_b_payld(10'D0),
|
||||
.m_sc_ar_req(m_sc_ar_req),
|
||||
.m_sc_ar_info(m_sc_ar_info),
|
||||
.m_sc_ar_send(m_sc_ar_send),
|
||||
@@ -194,7 +194,7 @@ input wire s_axi_rready;
|
||||
.m_sc_w_send(),
|
||||
.m_sc_w_recv(1'D0),
|
||||
.m_sc_w_payld(),
|
||||
.s_axi_awid(2'H0),
|
||||
.s_axi_awid(3'H0),
|
||||
.s_axi_awaddr(32'H00000000),
|
||||
.s_axi_awlen(8'H0),
|
||||
.s_axi_awlock(1'H0),
|
||||
|
||||
+9
-9
@@ -22,8 +22,8 @@
|
||||
"MAX_PAYLD_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ARBITER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ROUTE_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "140", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "142", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USER_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_PIPELINE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -95,14 +95,14 @@
|
||||
"C_NUM_SI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CHANNEL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PAYLD_WIDTH": [ { "value": "140", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PAYLD_WIDTH": [ { "value": "142", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_NUM_BYTES_ARRAY": [ { "value": "0x00000004", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_M_NUM_BYTES_ARRAY": [ { "value": "0x00000004", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_PRIORITY_ARB_ARRAY": [ { "value": "0b0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ARBITER_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ROUTE_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MAX_PAYLD_BYTES": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -118,7 +118,7 @@
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
@@ -146,14 +146,14 @@
|
||||
"s_sc_info": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_send": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"s_sc_recv": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"s_sc_payld": [ { "direction": "in", "size_left": "139", "size_right": "0" } ],
|
||||
"s_sc_payld": [ { "direction": "in", "size_left": "141", "size_right": "0" } ],
|
||||
"m_sc_aclk": [ { "direction": "in" } ],
|
||||
"m_sc_aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_sc_recv": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_send": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_req": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_info": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_payld": [ { "direction": "out", "size_left": "139", "size_right": "0" } ]
|
||||
"m_sc_payld": [ { "direction": "out", "size_left": "141", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_SC": {
|
||||
@@ -190,7 +190,7 @@
|
||||
"ASSOCIATED_CLKEN": [ { "value": "s_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
@@ -221,7 +221,7 @@
|
||||
"ASSOCIATED_CLKEN": [ { "value": "m_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
|
||||
+19
-19
@@ -470,7 +470,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -622,7 +622,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -735,7 +735,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:275cd552</spirit:value>
|
||||
<spirit:value>9:a871bfaf</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -754,11 +754,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:bf065d2a</spirit:value>
|
||||
<spirit:value>9:142bf686</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -774,11 +774,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:23 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:bf065d2a</spirit:value>
|
||||
<spirit:value>9:142bf686</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -797,11 +797,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:275cd552</spirit:value>
|
||||
<spirit:value>9:a871bfaf</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -817,11 +817,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:23 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:275cd552</spirit:value>
|
||||
<spirit:value>9:a871bfaf</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -958,7 +958,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">139</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">141</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1095,7 +1095,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">139</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">141</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1301,7 +1301,7 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_PAYLD_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_PAYLD_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PAYLD_WIDTH" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">140</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PAYLD_WIDTH" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">142</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="bitstring">
|
||||
<spirit:name>C_S_NUM_BYTES_ARRAY</spirit:name>
|
||||
@@ -1336,7 +1336,7 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ID_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ID_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_ADDR_WIDTH</spirit:name>
|
||||
@@ -1603,12 +1603,12 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="16" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="16" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PAYLD_WIDTH</spirit:name>
|
||||
<spirit:displayName>PAYLD_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PAYLD_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">140</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PAYLD_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">142</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ADDR_WIDTH</spirit:name>
|
||||
@@ -1916,7 +1916,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ARESETN.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.ASSOCIATED_CLKEN" xilinx:valuePermission="bd"/>
|
||||
@@ -1925,7 +1925,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ARESETN.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLKEN_CONVERSION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RELATIONSHIP" xilinx:valueSource="user"/>
|
||||
|
||||
+7
-7
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -70,7 +70,7 @@ module bd_962a_sarn_0 (
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -85,8 +85,8 @@ input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [139 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
input wire [141 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -101,7 +101,7 @@ output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
output wire [141 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
@@ -115,14 +115,14 @@ output wire [139 : 0] m_sc_payld;
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(2),
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.C_PAYLD_WIDTH(142),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
|
||||
+9
-9
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -52,8 +52,8 @@
|
||||
|
||||
(* X_CORE_INFO = "sc_node_v1_0_14_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_sarn_0,sc_node_v1_0_14_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_sarn_0,sc_node_v1_0_14_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=2,C_PAYLD_WIDTH=140,C_S_NUM_BYTES_ARRAY=0x00000004,C_M_NUM_BYTES_ARRAY=0x00000004,C_PRIORITY_ARB_ARRAY=0b0,C_USER_BITS_PER_BYTE=0,C_\
|
||||
ARBITER_MODE=1,C_SC_ROUTE_WIDTH=1,C_ID_WIDTH=2,C_ADDR_WIDTH=32,C_USER_WIDTH=0,C_MAX_PAYLD_BYTES=4,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=1,C_S_LATENCY=0,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_sarn_0,sc_node_v1_0_14_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=2,C_PAYLD_WIDTH=142,C_S_NUM_BYTES_ARRAY=0x00000004,C_M_NUM_BYTES_ARRAY=0x00000004,C_PRIORITY_ARB_ARRAY=0b0,C_USER_BITS_PER_BYTE=0,C_\
|
||||
ARBITER_MODE=1,C_SC_ROUTE_WIDTH=1,C_ID_WIDTH=3,C_ADDR_WIDTH=32,C_USER_WIDTH=0,C_MAX_PAYLD_BYTES=4,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=1,C_S_LATENCY=0,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_sarn_0 (
|
||||
s_sc_aclk,
|
||||
@@ -72,7 +72,7 @@ module bd_962a_sarn_0 (
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -87,8 +87,8 @@ input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [139 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
input wire [141 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -103,7 +103,7 @@ output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
output wire [141 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
@@ -117,14 +117,14 @@ output wire [139 : 0] m_sc_payld;
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(2),
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.C_PAYLD_WIDTH(142),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
|
||||
+11
-11
@@ -21,9 +21,9 @@
|
||||
"USER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MAX_PAYLD_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ARBITER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ROUTE_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "53", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ROUTE_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "56", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USER_WIDTH": [ { "value": "512", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_PIPELINE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -95,14 +95,14 @@
|
||||
"C_NUM_SI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PAYLD_WIDTH": [ { "value": "53", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PAYLD_WIDTH": [ { "value": "56", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_NUM_BYTES_ARRAY": [ { "value": "0x00000004", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_M_NUM_BYTES_ARRAY": [ { "value": "0x00000004", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_PRIORITY_ARB_ARRAY": [ { "value": "0b0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ARBITER_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ROUTE_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ROUTE_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MAX_PAYLD_BYTES": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -118,7 +118,7 @@
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
@@ -146,14 +146,14 @@
|
||||
"s_sc_info": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_send": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"s_sc_recv": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"s_sc_payld": [ { "direction": "in", "size_left": "52", "size_right": "0" } ],
|
||||
"s_sc_payld": [ { "direction": "in", "size_left": "55", "size_right": "0" } ],
|
||||
"m_sc_aclk": [ { "direction": "in" } ],
|
||||
"m_sc_aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_sc_recv": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_send": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_req": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_info": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_payld": [ { "direction": "out", "size_left": "52", "size_right": "0" } ]
|
||||
"m_sc_payld": [ { "direction": "out", "size_left": "55", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_SC": {
|
||||
@@ -190,7 +190,7 @@
|
||||
"ASSOCIATED_CLKEN": [ { "value": "s_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
@@ -221,7 +221,7 @@
|
||||
"ASSOCIATED_CLKEN": [ { "value": "m_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
|
||||
+21
-21
@@ -470,7 +470,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -622,7 +622,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -735,7 +735,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e584a805</spirit:value>
|
||||
<spirit:value>9:cbef8ac2</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -754,11 +754,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:c74fef9c</spirit:value>
|
||||
<spirit:value>9:bc47dfcf</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -774,11 +774,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:23 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:c74fef9c</spirit:value>
|
||||
<spirit:value>9:bc47dfcf</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -797,11 +797,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e584a805</spirit:value>
|
||||
<spirit:value>9:cbef8ac2</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -817,11 +817,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:23 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e584a805</spirit:value>
|
||||
<spirit:value>9:cbef8ac2</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -958,7 +958,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">52</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">55</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1095,7 +1095,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">52</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">55</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1301,7 +1301,7 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_PAYLD_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_PAYLD_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PAYLD_WIDTH" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">53</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PAYLD_WIDTH" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">56</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="bitstring">
|
||||
<spirit:name>C_S_NUM_BYTES_ARRAY</spirit:name>
|
||||
@@ -1331,12 +1331,12 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_SC_ROUTE_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_SC_ROUTE_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SC_ROUTE_WIDTH" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SC_ROUTE_WIDTH" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ID_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ID_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_ADDR_WIDTH</spirit:name>
|
||||
@@ -1598,17 +1598,17 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>SC_ROUTE_WIDTH</spirit:name>
|
||||
<spirit:displayName>SC_ROUTE_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SC_ROUTE_WIDTH" spirit:order="15" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SC_ROUTE_WIDTH" spirit:order="15" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="16" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="16" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PAYLD_WIDTH</spirit:name>
|
||||
<spirit:displayName>PAYLD_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PAYLD_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">53</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PAYLD_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">56</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ADDR_WIDTH</spirit:name>
|
||||
@@ -1916,7 +1916,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ARESETN.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.ASSOCIATED_CLKEN" xilinx:valuePermission="bd"/>
|
||||
@@ -1925,7 +1925,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ARESETN.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLKEN_CONVERSION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RELATIONSHIP" xilinx:valueSource="user"/>
|
||||
|
||||
+8
-8
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -70,7 +70,7 @@ module bd_962a_srn_0 (
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -85,8 +85,8 @@ input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [52 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
input wire [55 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -101,7 +101,7 @@ output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [52 : 0] m_sc_payld;
|
||||
output wire [55 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
@@ -115,14 +115,14 @@ output wire [52 : 0] m_sc_payld;
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(0),
|
||||
.C_PAYLD_WIDTH(53),
|
||||
.C_PAYLD_WIDTH(56),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(2),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_SC_ROUTE_WIDTH(4),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(512),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
|
||||
+10
-10
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -52,8 +52,8 @@
|
||||
|
||||
(* X_CORE_INFO = "sc_node_v1_0_14_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_srn_0,sc_node_v1_0_14_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_srn_0,sc_node_v1_0_14_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=0,C_PAYLD_WIDTH=53,C_S_NUM_BYTES_ARRAY=0x00000004,C_M_NUM_BYTES_ARRAY=0x00000004,C_PRIORITY_ARB_ARRAY=0b0,C_USER_BITS_PER_BYTE=0,C_AR\
|
||||
BITER_MODE=1,C_SC_ROUTE_WIDTH=2,C_ID_WIDTH=2,C_ADDR_WIDTH=32,C_USER_WIDTH=512,C_MAX_PAYLD_BYTES=4,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=0,C_S_LATENCY=1,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_srn_0,sc_node_v1_0_14_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=0,C_PAYLD_WIDTH=56,C_S_NUM_BYTES_ARRAY=0x00000004,C_M_NUM_BYTES_ARRAY=0x00000004,C_PRIORITY_ARB_ARRAY=0b0,C_USER_BITS_PER_BYTE=0,C_AR\
|
||||
BITER_MODE=1,C_SC_ROUTE_WIDTH=4,C_ID_WIDTH=3,C_ADDR_WIDTH=32,C_USER_WIDTH=512,C_MAX_PAYLD_BYTES=4,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=0,C_S_LATENCY=1,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_srn_0 (
|
||||
s_sc_aclk,
|
||||
@@ -72,7 +72,7 @@ module bd_962a_srn_0 (
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -87,8 +87,8 @@ input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [52 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
input wire [55 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -103,7 +103,7 @@ output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [52 : 0] m_sc_payld;
|
||||
output wire [55 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
@@ -117,14 +117,14 @@ output wire [52 : 0] m_sc_payld;
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(0),
|
||||
.C_PAYLD_WIDTH(53),
|
||||
.C_PAYLD_WIDTH(56),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(2),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_SC_ROUTE_WIDTH(4),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(512),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
|
||||
+4
-4
@@ -2123,7 +2123,7 @@
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
@@ -2225,7 +2225,7 @@
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "128", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -2283,7 +2283,7 @@
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -2322,7 +2322,7 @@
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+15
-15
@@ -604,7 +604,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1230,7 +1230,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1327,7 +1327,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1437,7 +1437,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:5d8c23c5</spirit:value>
|
||||
<spirit:value>9:a12d7f6d</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1456,11 +1456,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:311549ff</spirit:value>
|
||||
<spirit:value>9:ecbe8d6b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1476,11 +1476,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:311549ff</spirit:value>
|
||||
<spirit:value>9:ecbe8d6b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1499,11 +1499,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:5d8c23c5</spirit:value>
|
||||
<spirit:value>9:a12d7f6d</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1519,11 +1519,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:5d8c23c5</spirit:value>
|
||||
<spirit:value>9:a12d7f6d</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -14347,7 +14347,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
@@ -14370,7 +14370,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
@@ -14402,7 +14402,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
|
||||
+6
-6
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -97,7 +97,7 @@ module bd_962a_s01mmu_0 (
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
@@ -137,8 +137,8 @@ output wire s_axi_wready;
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THRE\
|
||||
ADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 128, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
|
||||
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
@@ -181,8 +181,8 @@ input wire [1 : 0] m_axi_bresp;
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_R\
|
||||
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
|
||||
+6
-6
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -99,7 +99,7 @@ module bd_962a_s01mmu_0 (
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
@@ -139,8 +139,8 @@ output wire s_axi_wready;
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THRE\
|
||||
ADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 128, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
|
||||
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
@@ -183,8 +183,8 @@ input wire [1 : 0] m_axi_bresp;
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_R\
|
||||
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
|
||||
+11
-11
@@ -14,10 +14,10 @@
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_PIPELINING": [ { "value": "0x1", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"MEP_IDENTIFIER": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MEP_IDENTIFIER_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MEP_IDENTIFIER_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_ID_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_ID_WIDTH": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_ID_WIDTH": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"WDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SEP_ROUTE_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -37,13 +37,13 @@
|
||||
"C_ENABLE_PIPELINING": [ { "value": "0x1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEP_IDENTIFIER_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEP_IDENTIFIER_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEP_IDENTIFIER": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SEP_ROUTE_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_ID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SUPPORTS_READ_DEADLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SUPPORTS_WRITE_DEADLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -57,7 +57,7 @@
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
@@ -102,7 +102,7 @@
|
||||
"s_axi_buser": [ { "direction": "out", "size_left": "1023", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_awid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_awid": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
@@ -120,7 +120,7 @@
|
||||
"m_axi_wuser": [ { "direction": "out", "size_left": "1023", "size_right": "0" } ],
|
||||
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_bid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_bid": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_buser": [ { "direction": "in", "size_left": "1023", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
@@ -157,7 +157,7 @@
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -197,7 +197,7 @@
|
||||
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -218,7 +218,7 @@
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -259,7 +259,7 @@
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+26
-26
@@ -572,7 +572,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1009,7 +1009,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">3</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1198,7 +1198,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1295,7 +1295,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1405,7 +1405,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a453248c</spirit:value>
|
||||
<spirit:value>9:6e9cdf1a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1424,11 +1424,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:edcb11fb</spirit:value>
|
||||
<spirit:value>9:c4459059</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1444,11 +1444,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:edcb11fb</spirit:value>
|
||||
<spirit:value>9:c4459059</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1467,11 +1467,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a453248c</spirit:value>
|
||||
<spirit:value>9:6e9cdf1a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1487,11 +1487,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a453248c</spirit:value>
|
||||
<spirit:value>9:6e9cdf1a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1502,7 +1502,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_MEP_IDENTIFIER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_MEP_IDENTIFIER_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_MEP_IDENTIFIER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_MEP_IDENTIFIER_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2628,7 +2628,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -3046,7 +3046,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -3170,7 +3170,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -3453,7 +3453,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_M_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -3651,7 +3651,7 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_MEP_IDENTIFIER_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_MEP_IDENTIFER_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEP_IDENTIFIER_WIDTH" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEP_IDENTIFIER_WIDTH" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_MEP_IDENTIFIER</spirit:name>
|
||||
@@ -3681,7 +3681,7 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_M_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_M_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_ID_WIDTH" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_ID_WIDTH" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_ADDR_WIDTH</spirit:name>
|
||||
@@ -3877,12 +3877,12 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>MEP_IDENTIFIER</spirit:name>
|
||||
<spirit:displayName>MEP_IDENIFIER</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEP_IDENTIFIER" spirit:order="7" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">3</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEP_IDENTIFIER" spirit:order="7" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>MEP_IDENTIFIER_WIDTH</spirit:name>
|
||||
<spirit:displayName>MEP_IDENTIFIER_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEP_IDENTIFIER_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEP_IDENTIFIER_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ADDR_WIDTH</spirit:name>
|
||||
@@ -3897,7 +3897,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>M_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>M_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.M_ID_WIDTH" spirit:order="11" spirit:minimum="2" spirit:maximum="2" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.M_ID_WIDTH" spirit:order="11" spirit:minimum="3" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>WDATA_WIDTH</spirit:name>
|
||||
@@ -3974,7 +3974,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
@@ -3997,7 +3997,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
@@ -4030,7 +4030,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
|
||||
+12
-12
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -102,7 +102,7 @@ module bd_962a_s01tr_0 (
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
@@ -148,12 +148,12 @@ output wire [1 : 0] s_axi_bresp;
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_F\
|
||||
CLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCL\
|
||||
K_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [1 : 0] m_axi_awid;
|
||||
output wire [2 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
@@ -189,15 +189,15 @@ output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [1 : 0] m_axi_bid;
|
||||
input wire [2 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_R\
|
||||
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
@@ -207,13 +207,13 @@ output wire m_axi_bready;
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(2),
|
||||
.C_MEP_IDENTIFIER_WIDTH(3),
|
||||
.C_MEP_IDENTIFIER(3),
|
||||
.C_SEP_ROUTE_WIDTH(1),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_ID_WIDTH(0),
|
||||
.C_M_ID_WIDTH(2),
|
||||
.C_M_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_SUPPORTS_READ_DEADLOCK(0),
|
||||
.C_SUPPORTS_WRITE_DEADLOCK(0),
|
||||
@@ -223,7 +223,7 @@ output wire m_axi_bready;
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_SINGLE_ISSUING(0)
|
||||
) inst (
|
||||
.mep_identifier(2'H3),
|
||||
.mep_identifier(3'H3),
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
@@ -304,7 +304,7 @@ output wire m_axi_bready;
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(2'H0),
|
||||
.m_axi_rid(3'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
|
||||
+13
-13
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -52,7 +52,7 @@
|
||||
|
||||
(* X_CORE_INFO = "sc_transaction_regulator_v1_0_9_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_s01tr_0,sc_transaction_regulator_v1_0_9_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_s01tr_0,sc_transaction_regulator_v1_0_9_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_transaction_regulator,x_ipVersion=1.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_IS_CASCADED=0,C_ENABLE_PIPELINING=0x1,C_NUM_READ_THREADS=1,C_NUM_WRITE_THREADS=1,C_MEP_IDENTIFIER_WIDTH=2,C_MEP_IDENTIFIER=3,C_SEP_ROUTE_WIDTH=1,C_RDATA_WIDTH=32,C_WDATA_WIDTH=32,C_S_ID_WIDTH=0,C_M_ID_WIDTH=2,C_ADDR_WIDTH=32,C_SUPPORTS_READ_DEADLOCK=0,C_SU\
|
||||
(* CORE_GENERATION_INFO = "bd_962a_s01tr_0,sc_transaction_regulator_v1_0_9_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_transaction_regulator,x_ipVersion=1.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_IS_CASCADED=0,C_ENABLE_PIPELINING=0x1,C_NUM_READ_THREADS=1,C_NUM_WRITE_THREADS=1,C_MEP_IDENTIFIER_WIDTH=3,C_MEP_IDENTIFIER=3,C_SEP_ROUTE_WIDTH=1,C_RDATA_WIDTH=32,C_WDATA_WIDTH=32,C_S_ID_WIDTH=0,C_M_ID_WIDTH=3,C_ADDR_WIDTH=32,C_SUPPORTS_READ_DEADLOCK=0,C_SU\
|
||||
PPORTS_WRITE_DEADLOCK=0,C_READ_ACCEPTANCE=32,C_WRITE_ACCEPTANCE=32,C_NUM_READ_OUTSTANDING=2,C_NUM_WRITE_OUTSTANDING=16,C_SINGLE_ISSUING=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_s01tr_0 (
|
||||
@@ -104,7 +104,7 @@ module bd_962a_s01tr_0 (
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
@@ -150,12 +150,12 @@ output wire [1 : 0] s_axi_bresp;
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_F\
|
||||
CLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCL\
|
||||
K_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [1 : 0] m_axi_awid;
|
||||
output wire [2 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
@@ -191,15 +191,15 @@ output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [1 : 0] m_axi_bid;
|
||||
input wire [2 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_R\
|
||||
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
@@ -209,13 +209,13 @@ output wire m_axi_bready;
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(2),
|
||||
.C_MEP_IDENTIFIER_WIDTH(3),
|
||||
.C_MEP_IDENTIFIER(3),
|
||||
.C_SEP_ROUTE_WIDTH(1),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_ID_WIDTH(0),
|
||||
.C_M_ID_WIDTH(2),
|
||||
.C_M_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_SUPPORTS_READ_DEADLOCK(0),
|
||||
.C_SUPPORTS_WRITE_DEADLOCK(0),
|
||||
@@ -225,7 +225,7 @@ output wire m_axi_bready;
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_SINGLE_ISSUING(0)
|
||||
) inst (
|
||||
.mep_identifier(2'H3),
|
||||
.mep_identifier(3'H3),
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
@@ -306,7 +306,7 @@ output wire m_axi_bready;
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(2'H0),
|
||||
.m_axi_rid(3'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
|
||||
+14
-14
@@ -17,12 +17,12 @@
|
||||
"IS_CASCADED": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MEP_IDENTIFIER_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MEP_IDENTIFIER_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SEG": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"WDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_MSC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -1329,7 +1329,7 @@
|
||||
"C_IS_CASCADED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEP_IDENTIFIER_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEP_IDENTIFIER_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SUPPORTS_NARROW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_SEG": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -1340,7 +1340,7 @@
|
||||
"C_MSC_WDATA_WIDTH_ARRAY": [ { "value": "0x00000020", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_MSC_RDATA_WIDTH_ARRAY": [ { "value": "0x00000020", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -1357,7 +1357,7 @@
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
@@ -1381,7 +1381,7 @@
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_awid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awid": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
@@ -1398,12 +1398,12 @@
|
||||
"s_axi_wuser": [ { "direction": "in", "size_left": "1023", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bid": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_buser": [ { "direction": "out", "size_left": "1023", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_awid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_awid": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
@@ -1419,7 +1419,7 @@
|
||||
"m_axi_wuser": [ { "direction": "out", "size_left": "1023", "size_right": "0" } ],
|
||||
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_bid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_bid": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_buser": [ { "direction": "in", "size_left": "1023", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
@@ -1435,7 +1435,7 @@
|
||||
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -1456,7 +1456,7 @@
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -1497,7 +1497,7 @@
|
||||
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -1518,7 +1518,7 @@
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -1557,7 +1557,7 @@
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+29
-29
@@ -383,7 +383,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">3</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -572,7 +572,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1012,7 +1012,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">3</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1201,7 +1201,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1298,7 +1298,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1408,7 +1408,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:be17d85b</spirit:value>
|
||||
<spirit:value>9:b5610072</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1427,11 +1427,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:6615ce6c</spirit:value>
|
||||
<spirit:value>9:1727af23</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1447,11 +1447,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:6615ce6c</spirit:value>
|
||||
<spirit:value>9:1727af23</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1470,11 +1470,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:be17d85b</spirit:value>
|
||||
<spirit:value>9:b5610072</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1490,11 +1490,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:be17d85b</spirit:value>
|
||||
<spirit:value>9:b5610072</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1557,7 +1557,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2017,7 +2017,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2132,7 +2132,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2445,7 +2445,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2604,7 +2604,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2974,7 +2974,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -3098,7 +3098,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -3333,7 +3333,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -3552,7 +3552,7 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_MEP_IDENTIFIER_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_MEP_IDENTIFER_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEP_IDENTIFIER_WIDTH" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEP_IDENTIFIER_WIDTH" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_SUPPORTS_NARROW</spirit:name>
|
||||
@@ -3607,7 +3607,7 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ID_WIDTH" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ID_WIDTH" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_WDATA_WIDTH</spirit:name>
|
||||
@@ -3844,7 +3844,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>MEP_IDENTIFIER_WIDTH</spirit:name>
|
||||
<spirit:displayName>MEP_IDENTIFIER_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEP_IDENTIFIER_WIDTH" spirit:order="11" spirit:minimum="0" spirit:maximum="2" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEP_IDENTIFIER_WIDTH" spirit:order="11" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SUPPORTS_NARROW</spirit:name>
|
||||
@@ -3869,7 +3869,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="16" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="16" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RDATA_WIDTH</spirit:name>
|
||||
@@ -10361,7 +10361,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
@@ -10384,7 +10384,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
@@ -10417,7 +10417,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
|
||||
+14
-14
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -101,14 +101,14 @@ module bd_962a_s01sic_0 (
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [1 : 0] s_axi_awid;
|
||||
input wire [2 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
@@ -142,19 +142,19 @@ input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [1 : 0] s_axi_bid;
|
||||
output wire [2 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_F\
|
||||
CLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCL\
|
||||
K_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [1 : 0] m_axi_awid;
|
||||
output wire [2 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
@@ -186,15 +186,15 @@ output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [1 : 0] m_axi_bid;
|
||||
input wire [2 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_R\
|
||||
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
@@ -208,7 +208,7 @@ output wire m_axi_bready;
|
||||
.C_IS_CASCADED(0),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(2),
|
||||
.C_MEP_IDENTIFIER_WIDTH(3),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_HAS_BURST(0),
|
||||
.C_NUM_SEG(1),
|
||||
@@ -219,7 +219,7 @@ output wire m_axi_bready;
|
||||
.C_MSC_WDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_MSC_RDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_S_WUSER_BITS_PER_BYTE(0),
|
||||
@@ -258,7 +258,7 @@ output wire m_axi_bready;
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(2'H0),
|
||||
.s_axi_arid(3'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arsize(3'H0),
|
||||
@@ -308,7 +308,7 @@ output wire m_axi_bready;
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(2'H0),
|
||||
.m_axi_rid(3'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
|
||||
+16
-16
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -52,8 +52,8 @@
|
||||
|
||||
(* X_CORE_INFO = "sc_si_converter_v1_0_11_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_s01sic_0,sc_si_converter_v1_0_11_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_s01sic_0,sc_si_converter_v1_0_11_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_si_converter,x_ipVersion=1.0,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_AXILITE_CONV=0,C_LIMIT_WRITE_LENGTH=0,C_LIMIT_READ_LENGTH=0,C_WRITE_WATERMARK=0,C_READ_WATERMARK=0,C_ENABLE_PIPELINING=0x1,C_IS_CASCADED=0,C_NUM_WRITE_THREADS=1,C_NUM_READ_THREADS=1,C_MEP_IDENTIFIER_WIDTH=2,C_SUPPORTS_NARROW=0,C_HAS_BURST=0,C_NUM_SEG=1,C_SEP_WDATA_WIDTH_ARRAY=0x000000\
|
||||
20,C_SEP_RDATA_WIDTH_ARRAY=0x00000020,C_SEP_PROTOCOL_ARRAY=0x00000001,C_NUM_MSC=1,C_MSC_WDATA_WIDTH_ARRAY=0x00000020,C_MSC_RDATA_WIDTH_ARRAY=0x00000020,C_ADDR_WIDTH=32,C_ID_WIDTH=2,C_WDATA_WIDTH=32,C_RDATA_WIDTH=32,C_S_WUSER_BITS_PER_BYTE=0,C_S_RUSER_BITS_PER_BYTE=0,C_MAX_WUSER_BITS_PER_BYTE=0,C_MAX_RUSER_BITS_PER_BYTE=0,C_SINGLE_ISSUING=0,C_NUM_READ_OUTSTANDING=2,C_NUM_WRITE_OUTSTANDING=16,C_READ_ACCEPTANCE=32,C_WRITE_ACCEPTANCE=32}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_s01sic_0,sc_si_converter_v1_0_11_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_si_converter,x_ipVersion=1.0,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_AXILITE_CONV=0,C_LIMIT_WRITE_LENGTH=0,C_LIMIT_READ_LENGTH=0,C_WRITE_WATERMARK=0,C_READ_WATERMARK=0,C_ENABLE_PIPELINING=0x1,C_IS_CASCADED=0,C_NUM_WRITE_THREADS=1,C_NUM_READ_THREADS=1,C_MEP_IDENTIFIER_WIDTH=3,C_SUPPORTS_NARROW=0,C_HAS_BURST=0,C_NUM_SEG=1,C_SEP_WDATA_WIDTH_ARRAY=0x000000\
|
||||
20,C_SEP_RDATA_WIDTH_ARRAY=0x00000020,C_SEP_PROTOCOL_ARRAY=0x00000001,C_NUM_MSC=1,C_MSC_WDATA_WIDTH_ARRAY=0x00000020,C_MSC_RDATA_WIDTH_ARRAY=0x00000020,C_ADDR_WIDTH=32,C_ID_WIDTH=3,C_WDATA_WIDTH=32,C_RDATA_WIDTH=32,C_S_WUSER_BITS_PER_BYTE=0,C_S_RUSER_BITS_PER_BYTE=0,C_MAX_WUSER_BITS_PER_BYTE=0,C_MAX_RUSER_BITS_PER_BYTE=0,C_SINGLE_ISSUING=0,C_NUM_READ_OUTSTANDING=2,C_NUM_WRITE_OUTSTANDING=16,C_READ_ACCEPTANCE=32,C_WRITE_ACCEPTANCE=32}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_s01sic_0 (
|
||||
aclk,
|
||||
@@ -103,14 +103,14 @@ module bd_962a_s01sic_0 (
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [1 : 0] s_axi_awid;
|
||||
input wire [2 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
@@ -144,19 +144,19 @@ input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [1 : 0] s_axi_bid;
|
||||
output wire [2 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_F\
|
||||
CLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCL\
|
||||
K_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [1 : 0] m_axi_awid;
|
||||
output wire [2 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
@@ -188,15 +188,15 @@ output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [1 : 0] m_axi_bid;
|
||||
input wire [2 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_R\
|
||||
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
@@ -210,7 +210,7 @@ output wire m_axi_bready;
|
||||
.C_IS_CASCADED(0),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(2),
|
||||
.C_MEP_IDENTIFIER_WIDTH(3),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_HAS_BURST(0),
|
||||
.C_NUM_SEG(1),
|
||||
@@ -221,7 +221,7 @@ output wire m_axi_bready;
|
||||
.C_MSC_WDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_MSC_RDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_S_WUSER_BITS_PER_BYTE(0),
|
||||
@@ -260,7 +260,7 @@ output wire m_axi_bready;
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(2'H0),
|
||||
.s_axi_arid(3'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arsize(3'H0),
|
||||
@@ -310,7 +310,7 @@ output wire m_axi_bready;
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(2'H0),
|
||||
.m_axi_rid(3'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
|
||||
+18
-18
@@ -10,11 +10,11 @@
|
||||
"component_parameters": {
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_ID_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_RDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_WDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ID_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_RDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_WDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ARUSER_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -23,16 +23,16 @@
|
||||
"SC_WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MSC_ROUTE_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SSC_ROUTE_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SSC_ROUTE_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "bd_962a_s01a2s_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -41,18 +41,18 @@
|
||||
"C_SC_AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MSC_ROUTE_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SSC_ROUTE_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AWPAYLD_WIDTH": [ { "value": "140", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_ARPAYLD_WIDTH": [ { "value": "140", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_SSC_ROUTE_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AWPAYLD_WIDTH": [ { "value": "142", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_ARPAYLD_WIDTH": [ { "value": "142", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_WPAYLD_WIDTH": [ { "value": "52", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_RPAYLD_WIDTH": [ { "value": "53", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_BPAYLD_WIDTH": [ { "value": "7", "resolve_type": "dependent", "format": "long", "usage": "all" } ]
|
||||
"C_RPAYLD_WIDTH": [ { "value": "56", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_BPAYLD_WIDTH": [ { "value": "10", "resolve_type": "dependent", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
@@ -79,18 +79,18 @@
|
||||
"s_sc_b_info": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_b_send": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_sc_b_recv": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_sc_b_payld": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_b_payld": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_sc_aw_req": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"m_sc_aw_info": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_sc_aw_send": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"m_sc_aw_recv": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_sc_aw_payld": [ { "direction": "out", "size_left": "139", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_sc_aw_payld": [ { "direction": "out", "size_left": "141", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_sc_w_req": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"m_sc_w_info": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_sc_w_send": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"m_sc_w_recv": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_sc_w_payld": [ { "direction": "out", "size_left": "51", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awid": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||
@@ -106,7 +106,7 @@
|
||||
"s_axi_wuser": [ { "direction": "in", "size_left": "1023", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bid": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_buser": [ { "direction": "out", "size_left": "1023", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
@@ -157,7 +157,7 @@
|
||||
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -178,7 +178,7 @@
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -218,7 +218,7 @@
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+32
-32
@@ -627,7 +627,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">3</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -816,7 +816,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -920,7 +920,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -975,7 +975,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e2432c31</spirit:value>
|
||||
<spirit:value>9:668033ae</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -994,11 +994,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:2bb85da4</spirit:value>
|
||||
<spirit:value>9:e3e88212</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1014,11 +1014,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:2bb85da4</spirit:value>
|
||||
<spirit:value>9:e3e88212</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1037,11 +1037,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e2432c31</spirit:value>
|
||||
<spirit:value>9:668033ae</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1057,11 +1057,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:33 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e2432c31</spirit:value>
|
||||
<spirit:value>9:668033ae</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1181,7 +1181,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_RPAYLD_WIDTH')) - 1)">52</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_RPAYLD_WIDTH')) - 1)">55</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1276,7 +1276,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_BPAYLD_WIDTH')) - 1)">6</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_BPAYLD_WIDTH')) - 1)">9</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1392,7 +1392,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ARPAYLD_WIDTH')) - 1)">139</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ARPAYLD_WIDTH')) - 1)">141</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1487,7 +1487,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AWPAYLD_WIDTH')) - 1)">139</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AWPAYLD_WIDTH')) - 1)">141</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1595,7 +1595,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2001,7 +2001,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2116,7 +2116,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2375,7 +2375,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">1</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_AXI_ID_WIDTH'))) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2539,7 +2539,7 @@
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_AXI_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>AXI_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_AXI_RDATA_WIDTH</spirit:name>
|
||||
@@ -2559,7 +2559,7 @@
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_SC_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>SC_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SC_ID_WIDTH" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SC_ID_WIDTH" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_SC_RDATA_WIDTH</spirit:name>
|
||||
@@ -2604,15 +2604,15 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_SSC_ROUTE_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_SSC_ROUTE_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_AWPAYLD_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_AWPAYLD_WIDTH" spirit:dependency="(((((102 + spirit:decode(id('MODELPARAM_VALUE.C_SC_ADDR_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_MSC_ROUTE_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_AWUSER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_AWUSER_WIDTH'))))">140</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_AWPAYLD_WIDTH" spirit:dependency="(((((102 + spirit:decode(id('MODELPARAM_VALUE.C_SC_ADDR_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_MSC_ROUTE_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_AWUSER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_AWUSER_WIDTH'))))">142</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_ARPAYLD_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_ARPAYLD_WIDTH" spirit:dependency="(((((102 + spirit:decode(id('MODELPARAM_VALUE.C_SC_ADDR_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_MSC_ROUTE_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ARUSER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ARUSER_WIDTH'))))">140</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_ARPAYLD_WIDTH" spirit:dependency="(((((102 + spirit:decode(id('MODELPARAM_VALUE.C_SC_ADDR_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_MSC_ROUTE_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ARUSER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ARUSER_WIDTH'))))">142</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_WPAYLD_WIDTH</spirit:name>
|
||||
@@ -2620,11 +2620,11 @@
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_RPAYLD_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_RPAYLD_WIDTH" spirit:dependency="((((17 + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH'))) + spirit:decode(id('MODELPARAM_VALUE.C_SC_RDATA_WIDTH'))) + (spirit:decode(id('MODELPARAM_VALUE.C_SC_RUSER_BITS_PER_BYTE')) * (spirit:decode(id('MODELPARAM_VALUE.C_SC_RDATA_WIDTH')) / 8)))">53</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_RPAYLD_WIDTH" spirit:dependency="((((17 + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH'))) + spirit:decode(id('MODELPARAM_VALUE.C_SC_RDATA_WIDTH'))) + (spirit:decode(id('MODELPARAM_VALUE.C_SC_RUSER_BITS_PER_BYTE')) * (spirit:decode(id('MODELPARAM_VALUE.C_SC_RDATA_WIDTH')) / 8)))">56</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_BPAYLD_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_BPAYLD_WIDTH" spirit:dependency="(((2 + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_BUSER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_BUSER_WIDTH'))))">7</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_BPAYLD_WIDTH" spirit:dependency="(((2 + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_ID_WIDTH')))) + spirit:decode(id('MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH'))) + ((spirit:decode(id('MODELPARAM_VALUE.C_SC_BUSER_WIDTH')) = 0) ? 1 : spirit:decode(id('MODELPARAM_VALUE.C_SC_BUSER_WIDTH'))))">10</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
@@ -2772,7 +2772,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>AXI_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>AXI_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_WIDTH" spirit:order="4" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_WIDTH" spirit:order="4" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>AXI_RDATA_WIDTH</spirit:name>
|
||||
@@ -2792,7 +2792,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>SC_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>SC_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SC_ID_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SC_ID_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SC_RDATA_WIDTH</spirit:name>
|
||||
@@ -2837,7 +2837,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>SSC_ROUTE_WIDTH</spirit:name>
|
||||
<spirit:displayName>SSC_ROUTE_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SSC_ROUTE_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SSC_ROUTE_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
@@ -2859,7 +2859,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
@@ -2882,7 +2882,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
|
||||
+17
-17
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -93,7 +93,7 @@ module bd_962a_s01a2s_0 (
|
||||
s_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B REQ" *)
|
||||
@@ -105,7 +105,7 @@ input wire s_sc_b_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B RECV" *)
|
||||
output wire s_sc_b_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B PAYLD" *)
|
||||
input wire [6 : 0] s_sc_b_payld;
|
||||
input wire [9 : 0] s_sc_b_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW REQ" *)
|
||||
output wire m_sc_aw_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW INFO" *)
|
||||
@@ -115,7 +115,7 @@ output wire m_sc_aw_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW RECV" *)
|
||||
input wire m_sc_aw_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW PAYLD" *)
|
||||
output wire [139 : 0] m_sc_aw_payld;
|
||||
output wire [141 : 0] m_sc_aw_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W REQ" *)
|
||||
output wire m_sc_w_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W INFO" *)
|
||||
@@ -127,7 +127,7 @@ input wire m_sc_w_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W PAYLD" *)
|
||||
output wire [51 : 0] m_sc_w_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [1 : 0] s_axi_awid;
|
||||
input wire [2 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
@@ -159,25 +159,25 @@ input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [1 : 0] s_axi_bid;
|
||||
output wire [2 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_R\
|
||||
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
|
||||
sc_axi2sc_v1_0_8_top #(
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ID_WIDTH(2),
|
||||
.C_AXI_ID_WIDTH(3),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_SC_ADDR_WIDTH(32),
|
||||
.C_SC_ID_WIDTH(2),
|
||||
.C_SC_ID_WIDTH(3),
|
||||
.C_SC_RDATA_WIDTH(32),
|
||||
.C_SC_WDATA_WIDTH(32),
|
||||
.C_SC_RUSER_BITS_PER_BYTE(0),
|
||||
@@ -186,19 +186,19 @@ input wire s_axi_bready;
|
||||
.C_SC_AWUSER_WIDTH(0),
|
||||
.C_SC_BUSER_WIDTH(0),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_SSC_ROUTE_WIDTH(2),
|
||||
.C_AWPAYLD_WIDTH(140),
|
||||
.C_ARPAYLD_WIDTH(140),
|
||||
.C_SSC_ROUTE_WIDTH(4),
|
||||
.C_AWPAYLD_WIDTH(142),
|
||||
.C_ARPAYLD_WIDTH(142),
|
||||
.C_WPAYLD_WIDTH(52),
|
||||
.C_RPAYLD_WIDTH(53),
|
||||
.C_BPAYLD_WIDTH(7)
|
||||
.C_RPAYLD_WIDTH(56),
|
||||
.C_BPAYLD_WIDTH(10)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.s_sc_r_req(1'D0),
|
||||
.s_sc_r_info(1'D0),
|
||||
.s_sc_r_send(1'D0),
|
||||
.s_sc_r_recv(),
|
||||
.s_sc_r_payld(53'D0),
|
||||
.s_sc_r_payld(56'D0),
|
||||
.s_sc_b_req(s_sc_b_req),
|
||||
.s_sc_b_info(s_sc_b_info),
|
||||
.s_sc_b_send(s_sc_b_send),
|
||||
@@ -240,7 +240,7 @@ input wire s_axi_bready;
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(2'H0),
|
||||
.s_axi_arid(3'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arlock(1'H0),
|
||||
|
||||
+19
-19
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -52,8 +52,8 @@
|
||||
|
||||
(* X_CORE_INFO = "sc_axi2sc_v1_0_8_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_s01a2s_0,sc_axi2sc_v1_0_8_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_s01a2s_0,sc_axi2sc_v1_0_8_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_axi2sc,x_ipVersion=1.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_AXI_ADDR_WIDTH=32,C_AXI_ID_WIDTH=2,C_AXI_RDATA_WIDTH=32,C_AXI_WDATA_WIDTH=32,C_SC_ADDR_WIDTH=32,C_SC_ID_WIDTH=2,C_SC_RDATA_WIDTH=32,C_SC_WDATA_WIDTH=32,C_SC_RUSER_BITS_PER_BYTE=0,C_SC_WUSER_BITS_PER_BYTE=0,C_SC_ARUSER_WIDTH=0,C_SC_AWUSER_WIDTH=0,C_SC_BUSER_WIDTH=0,C_MSC_ROUTE_WIDTH=1,C_SSC_ROUTE_WI\
|
||||
DTH=2,C_AWPAYLD_WIDTH=140,C_ARPAYLD_WIDTH=140,C_WPAYLD_WIDTH=52,C_RPAYLD_WIDTH=53,C_BPAYLD_WIDTH=7}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_s01a2s_0,sc_axi2sc_v1_0_8_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_axi2sc,x_ipVersion=1.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_AXI_ADDR_WIDTH=32,C_AXI_ID_WIDTH=3,C_AXI_RDATA_WIDTH=32,C_AXI_WDATA_WIDTH=32,C_SC_ADDR_WIDTH=32,C_SC_ID_WIDTH=3,C_SC_RDATA_WIDTH=32,C_SC_WDATA_WIDTH=32,C_SC_RUSER_BITS_PER_BYTE=0,C_SC_WUSER_BITS_PER_BYTE=0,C_SC_ARUSER_WIDTH=0,C_SC_AWUSER_WIDTH=0,C_SC_BUSER_WIDTH=0,C_MSC_ROUTE_WIDTH=1,C_SSC_ROUTE_WI\
|
||||
DTH=4,C_AWPAYLD_WIDTH=142,C_ARPAYLD_WIDTH=142,C_WPAYLD_WIDTH=52,C_RPAYLD_WIDTH=56,C_BPAYLD_WIDTH=10}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_s01a2s_0 (
|
||||
aclk,
|
||||
@@ -95,7 +95,7 @@ module bd_962a_s01a2s_0 (
|
||||
s_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B REQ" *)
|
||||
@@ -107,7 +107,7 @@ input wire s_sc_b_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B RECV" *)
|
||||
output wire s_sc_b_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B PAYLD" *)
|
||||
input wire [6 : 0] s_sc_b_payld;
|
||||
input wire [9 : 0] s_sc_b_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW REQ" *)
|
||||
output wire m_sc_aw_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW INFO" *)
|
||||
@@ -117,7 +117,7 @@ output wire m_sc_aw_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW RECV" *)
|
||||
input wire m_sc_aw_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW PAYLD" *)
|
||||
output wire [139 : 0] m_sc_aw_payld;
|
||||
output wire [141 : 0] m_sc_aw_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W REQ" *)
|
||||
output wire m_sc_w_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W INFO" *)
|
||||
@@ -129,7 +129,7 @@ input wire m_sc_w_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W PAYLD" *)
|
||||
output wire [51 : 0] m_sc_w_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [1 : 0] s_axi_awid;
|
||||
input wire [2 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
@@ -161,25 +161,25 @@ input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [1 : 0] s_axi_bid;
|
||||
output wire [2 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_R\
|
||||
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
|
||||
sc_axi2sc_v1_0_8_top #(
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ID_WIDTH(2),
|
||||
.C_AXI_ID_WIDTH(3),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_SC_ADDR_WIDTH(32),
|
||||
.C_SC_ID_WIDTH(2),
|
||||
.C_SC_ID_WIDTH(3),
|
||||
.C_SC_RDATA_WIDTH(32),
|
||||
.C_SC_WDATA_WIDTH(32),
|
||||
.C_SC_RUSER_BITS_PER_BYTE(0),
|
||||
@@ -188,19 +188,19 @@ input wire s_axi_bready;
|
||||
.C_SC_AWUSER_WIDTH(0),
|
||||
.C_SC_BUSER_WIDTH(0),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_SSC_ROUTE_WIDTH(2),
|
||||
.C_AWPAYLD_WIDTH(140),
|
||||
.C_ARPAYLD_WIDTH(140),
|
||||
.C_SSC_ROUTE_WIDTH(4),
|
||||
.C_AWPAYLD_WIDTH(142),
|
||||
.C_ARPAYLD_WIDTH(142),
|
||||
.C_WPAYLD_WIDTH(52),
|
||||
.C_RPAYLD_WIDTH(53),
|
||||
.C_BPAYLD_WIDTH(7)
|
||||
.C_RPAYLD_WIDTH(56),
|
||||
.C_BPAYLD_WIDTH(10)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.s_sc_r_req(1'D0),
|
||||
.s_sc_r_info(1'D0),
|
||||
.s_sc_r_send(1'D0),
|
||||
.s_sc_r_recv(),
|
||||
.s_sc_r_payld(53'D0),
|
||||
.s_sc_r_payld(56'D0),
|
||||
.s_sc_b_req(s_sc_b_req),
|
||||
.s_sc_b_info(s_sc_b_info),
|
||||
.s_sc_b_send(s_sc_b_send),
|
||||
@@ -242,7 +242,7 @@ input wire s_axi_bready;
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(2'H0),
|
||||
.s_axi_arid(3'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arlock(1'H0),
|
||||
|
||||
+9
-9
@@ -22,8 +22,8 @@
|
||||
"MAX_PAYLD_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ARBITER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ROUTE_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "140", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "142", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USER_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_PIPELINE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -95,14 +95,14 @@
|
||||
"C_NUM_SI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CHANNEL": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PAYLD_WIDTH": [ { "value": "140", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PAYLD_WIDTH": [ { "value": "142", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_NUM_BYTES_ARRAY": [ { "value": "0x00000004", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_M_NUM_BYTES_ARRAY": [ { "value": "0x00000004", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_PRIORITY_ARB_ARRAY": [ { "value": "0b0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ARBITER_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ROUTE_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MAX_PAYLD_BYTES": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -118,7 +118,7 @@
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
@@ -146,14 +146,14 @@
|
||||
"s_sc_info": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_send": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"s_sc_recv": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"s_sc_payld": [ { "direction": "in", "size_left": "139", "size_right": "0" } ],
|
||||
"s_sc_payld": [ { "direction": "in", "size_left": "141", "size_right": "0" } ],
|
||||
"m_sc_aclk": [ { "direction": "in" } ],
|
||||
"m_sc_aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_sc_recv": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_send": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_req": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_info": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_payld": [ { "direction": "out", "size_left": "139", "size_right": "0" } ]
|
||||
"m_sc_payld": [ { "direction": "out", "size_left": "141", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_SC": {
|
||||
@@ -190,7 +190,7 @@
|
||||
"ASSOCIATED_CLKEN": [ { "value": "s_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
@@ -221,7 +221,7 @@
|
||||
"ASSOCIATED_CLKEN": [ { "value": "m_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
|
||||
+19
-19
@@ -470,7 +470,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -622,7 +622,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -735,7 +735,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a82b5786</spirit:value>
|
||||
<spirit:value>9:27063d7b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -754,11 +754,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:02720c54</spirit:value>
|
||||
<spirit:value>9:a95fa7f8</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -774,11 +774,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:34 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:02720c54</spirit:value>
|
||||
<spirit:value>9:a95fa7f8</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -797,11 +797,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a82b5786</spirit:value>
|
||||
<spirit:value>9:27063d7b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -817,11 +817,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:34 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a82b5786</spirit:value>
|
||||
<spirit:value>9:27063d7b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -958,7 +958,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">139</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">141</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1095,7 +1095,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">139</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">141</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1301,7 +1301,7 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_PAYLD_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_PAYLD_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PAYLD_WIDTH" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">140</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PAYLD_WIDTH" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">142</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="bitstring">
|
||||
<spirit:name>C_S_NUM_BYTES_ARRAY</spirit:name>
|
||||
@@ -1336,7 +1336,7 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ID_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ID_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_ADDR_WIDTH</spirit:name>
|
||||
@@ -1603,12 +1603,12 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="16" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="16" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PAYLD_WIDTH</spirit:name>
|
||||
<spirit:displayName>PAYLD_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PAYLD_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">140</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PAYLD_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">142</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ADDR_WIDTH</spirit:name>
|
||||
@@ -1916,7 +1916,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ARESETN.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.ASSOCIATED_CLKEN" xilinx:valuePermission="bd"/>
|
||||
@@ -1925,7 +1925,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ARESETN.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLKEN_CONVERSION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RELATIONSHIP" xilinx:valueSource="user"/>
|
||||
|
||||
+7
-7
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -70,7 +70,7 @@ module bd_962a_sawn_0 (
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -85,8 +85,8 @@ input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [139 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
input wire [141 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -101,7 +101,7 @@ output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
output wire [141 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
@@ -115,14 +115,14 @@ output wire [139 : 0] m_sc_payld;
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(3),
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.C_PAYLD_WIDTH(142),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
|
||||
+9
-9
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -52,8 +52,8 @@
|
||||
|
||||
(* X_CORE_INFO = "sc_node_v1_0_14_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_sawn_0,sc_node_v1_0_14_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_sawn_0,sc_node_v1_0_14_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=3,C_PAYLD_WIDTH=140,C_S_NUM_BYTES_ARRAY=0x00000004,C_M_NUM_BYTES_ARRAY=0x00000004,C_PRIORITY_ARB_ARRAY=0b0,C_USER_BITS_PER_BYTE=0,C_\
|
||||
ARBITER_MODE=1,C_SC_ROUTE_WIDTH=1,C_ID_WIDTH=2,C_ADDR_WIDTH=32,C_USER_WIDTH=0,C_MAX_PAYLD_BYTES=4,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=1,C_S_LATENCY=0,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_sawn_0,sc_node_v1_0_14_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=3,C_PAYLD_WIDTH=142,C_S_NUM_BYTES_ARRAY=0x00000004,C_M_NUM_BYTES_ARRAY=0x00000004,C_PRIORITY_ARB_ARRAY=0b0,C_USER_BITS_PER_BYTE=0,C_\
|
||||
ARBITER_MODE=1,C_SC_ROUTE_WIDTH=1,C_ID_WIDTH=3,C_ADDR_WIDTH=32,C_USER_WIDTH=0,C_MAX_PAYLD_BYTES=4,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=1,C_S_LATENCY=0,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_sawn_0 (
|
||||
s_sc_aclk,
|
||||
@@ -72,7 +72,7 @@ module bd_962a_sawn_0 (
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -87,8 +87,8 @@ input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [139 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
input wire [141 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -103,7 +103,7 @@ output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
output wire [141 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
@@ -117,14 +117,14 @@ output wire [139 : 0] m_sc_payld;
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(3),
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.C_PAYLD_WIDTH(142),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
|
||||
+5
-5
@@ -22,7 +22,7 @@
|
||||
"MAX_PAYLD_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ARBITER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ROUTE_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "52", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USER_WIDTH": [ { "value": "512", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -102,7 +102,7 @@
|
||||
"C_USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ARBITER_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ROUTE_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MAX_PAYLD_BYTES": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -118,7 +118,7 @@
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
@@ -190,7 +190,7 @@
|
||||
"ASSOCIATED_CLKEN": [ { "value": "s_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
@@ -221,7 +221,7 @@
|
||||
"ASSOCIATED_CLKEN": [ { "value": "m_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
|
||||
+15
-15
@@ -470,7 +470,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -622,7 +622,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -735,7 +735,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:03b5d4a9</spirit:value>
|
||||
<spirit:value>9:0a706341</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -754,11 +754,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:eee82ab8</spirit:value>
|
||||
<spirit:value>9:598d3e07</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -774,11 +774,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:34 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:eee82ab8</spirit:value>
|
||||
<spirit:value>9:598d3e07</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -797,11 +797,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:03b5d4a9</spirit:value>
|
||||
<spirit:value>9:0a706341</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -817,11 +817,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:34 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:03b5d4a9</spirit:value>
|
||||
<spirit:value>9:0a706341</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1336,7 +1336,7 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ID_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ID_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_ADDR_WIDTH</spirit:name>
|
||||
@@ -1603,7 +1603,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="16" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="16" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PAYLD_WIDTH</spirit:name>
|
||||
@@ -1916,7 +1916,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ARESETN.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.ASSOCIATED_CLKEN" xilinx:valuePermission="bd"/>
|
||||
@@ -1925,7 +1925,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ARESETN.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLKEN_CONVERSION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RELATIONSHIP" xilinx:valueSource="user"/>
|
||||
|
||||
+4
-4
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -70,7 +70,7 @@ module bd_962a_swn_0 (
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -86,7 +86,7 @@ input wire [0 : 0] s_sc_send;
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [51 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -122,7 +122,7 @@ output wire [51 : 0] m_sc_payld;
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(512),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
|
||||
+5
-5
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -53,7 +53,7 @@
|
||||
(* X_CORE_INFO = "sc_node_v1_0_14_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_swn_0,sc_node_v1_0_14_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_swn_0,sc_node_v1_0_14_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=1,C_PAYLD_WIDTH=52,C_S_NUM_BYTES_ARRAY=0x00000004,C_M_NUM_BYTES_ARRAY=0x00000004,C_PRIORITY_ARB_ARRAY=0b0,C_USER_BITS_PER_BYTE=0,C_AR\
|
||||
BITER_MODE=1,C_SC_ROUTE_WIDTH=1,C_ID_WIDTH=2,C_ADDR_WIDTH=32,C_USER_WIDTH=512,C_MAX_PAYLD_BYTES=4,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=1,C_S_LATENCY=0,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
BITER_MODE=1,C_SC_ROUTE_WIDTH=1,C_ID_WIDTH=3,C_ADDR_WIDTH=32,C_USER_WIDTH=512,C_MAX_PAYLD_BYTES=4,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=1,C_S_LATENCY=0,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_swn_0 (
|
||||
s_sc_aclk,
|
||||
@@ -72,7 +72,7 @@ module bd_962a_swn_0 (
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -88,7 +88,7 @@ input wire [0 : 0] s_sc_send;
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [51 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -124,7 +124,7 @@ output wire [51 : 0] m_sc_payld;
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(512),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
|
||||
+11
-11
@@ -21,9 +21,9 @@
|
||||
"USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MAX_PAYLD_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ARBITER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ROUTE_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ROUTE_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USER_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_PIPELINE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -95,14 +95,14 @@
|
||||
"C_NUM_SI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CHANNEL": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PAYLD_WIDTH": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PAYLD_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_NUM_BYTES_ARRAY": [ { "value": "0x00000004", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_M_NUM_BYTES_ARRAY": [ { "value": "0x00000004", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_PRIORITY_ARB_ARRAY": [ { "value": "0b0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ARBITER_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ROUTE_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ROUTE_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MAX_PAYLD_BYTES": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -118,7 +118,7 @@
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
@@ -146,14 +146,14 @@
|
||||
"s_sc_info": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_send": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"s_sc_recv": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"s_sc_payld": [ { "direction": "in", "size_left": "6", "size_right": "0" } ],
|
||||
"s_sc_payld": [ { "direction": "in", "size_left": "9", "size_right": "0" } ],
|
||||
"m_sc_aclk": [ { "direction": "in" } ],
|
||||
"m_sc_aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_sc_recv": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_send": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_req": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_info": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_payld": [ { "direction": "out", "size_left": "6", "size_right": "0" } ]
|
||||
"m_sc_payld": [ { "direction": "out", "size_left": "9", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_SC": {
|
||||
@@ -190,7 +190,7 @@
|
||||
"ASSOCIATED_CLKEN": [ { "value": "s_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
@@ -221,7 +221,7 @@
|
||||
"ASSOCIATED_CLKEN": [ { "value": "m_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
|
||||
+21
-21
@@ -470,7 +470,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -622,7 +622,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -735,7 +735,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:428b23fb</spirit:value>
|
||||
<spirit:value>9:c5b455f0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -754,11 +754,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:28c24d2b</spirit:value>
|
||||
<spirit:value>9:02b8cd6e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -774,11 +774,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:34 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:28c24d2b</spirit:value>
|
||||
<spirit:value>9:02b8cd6e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -797,11 +797,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Apr 10 07:55:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 28 12:57:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:428b23fb</spirit:value>
|
||||
<spirit:value>9:c5b455f0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -817,11 +817,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Apr 29 13:30:34 UTC 2024</spirit:value>
|
||||
<spirit:value>Thu Aug 20 05:41:24 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:428b23fb</spirit:value>
|
||||
<spirit:value>9:c5b455f0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -958,7 +958,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">6</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">9</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1095,7 +1095,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">6</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_PAYLD_WIDTH')) - 1)">9</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -1301,7 +1301,7 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_PAYLD_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_PAYLD_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PAYLD_WIDTH" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">7</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PAYLD_WIDTH" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">10</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="bitstring">
|
||||
<spirit:name>C_S_NUM_BYTES_ARRAY</spirit:name>
|
||||
@@ -1331,12 +1331,12 @@
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_SC_ROUTE_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_SC_ROUTE_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SC_ROUTE_WIDTH" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SC_ROUTE_WIDTH" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>C_ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ID_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ID_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="long">
|
||||
<spirit:name>C_ADDR_WIDTH</spirit:name>
|
||||
@@ -1598,17 +1598,17 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>SC_ROUTE_WIDTH</spirit:name>
|
||||
<spirit:displayName>SC_ROUTE_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SC_ROUTE_WIDTH" spirit:order="15" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SC_ROUTE_WIDTH" spirit:order="15" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ID_WIDTH</spirit:name>
|
||||
<spirit:displayName>ID_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="16" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="16" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PAYLD_WIDTH</spirit:name>
|
||||
<spirit:displayName>PAYLD_WIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PAYLD_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">7</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PAYLD_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="1854" spirit:rangeType="long">10</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ADDR_WIDTH</spirit:name>
|
||||
@@ -1916,7 +1916,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ARESETN.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.ASSOCIATED_CLKEN" xilinx:valuePermission="bd"/>
|
||||
@@ -1925,7 +1925,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ARESETN.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLKEN_CONVERSION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RELATIONSHIP" xilinx:valueSource="user"/>
|
||||
|
||||
+8
-8
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -70,7 +70,7 @@ module bd_962a_sbn_0 (
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -85,8 +85,8 @@ input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [6 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
input wire [9 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -101,7 +101,7 @@ output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [6 : 0] m_sc_payld;
|
||||
output wire [9 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
@@ -115,14 +115,14 @@ output wire [6 : 0] m_sc_payld;
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(4),
|
||||
.C_PAYLD_WIDTH(7),
|
||||
.C_PAYLD_WIDTH(10),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(2),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_SC_ROUTE_WIDTH(4),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
|
||||
+10
-10
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -52,8 +52,8 @@
|
||||
|
||||
(* X_CORE_INFO = "sc_node_v1_0_14_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_sbn_0,sc_node_v1_0_14_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_sbn_0,sc_node_v1_0_14_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=4,C_PAYLD_WIDTH=7,C_S_NUM_BYTES_ARRAY=0x00000004,C_M_NUM_BYTES_ARRAY=0x00000004,C_PRIORITY_ARB_ARRAY=0b0,C_USER_BITS_PER_BYTE=0,C_ARB\
|
||||
ITER_MODE=1,C_SC_ROUTE_WIDTH=2,C_ID_WIDTH=2,C_ADDR_WIDTH=32,C_USER_WIDTH=0,C_MAX_PAYLD_BYTES=4,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=0,C_S_LATENCY=1,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_sbn_0,sc_node_v1_0_14_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=4,C_PAYLD_WIDTH=10,C_S_NUM_BYTES_ARRAY=0x00000004,C_M_NUM_BYTES_ARRAY=0x00000004,C_PRIORITY_ARB_ARRAY=0b0,C_USER_BITS_PER_BYTE=0,C_AR\
|
||||
BITER_MODE=1,C_SC_ROUTE_WIDTH=4,C_ID_WIDTH=3,C_ADDR_WIDTH=32,C_USER_WIDTH=0,C_MAX_PAYLD_BYTES=4,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=0,C_S_LATENCY=1,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_sbn_0 (
|
||||
s_sc_aclk,
|
||||
@@ -72,7 +72,7 @@ module bd_962a_sbn_0 (
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -87,8 +87,8 @@ input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [6 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
input wire [9 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
@@ -103,7 +103,7 @@ output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [6 : 0] m_sc_payld;
|
||||
output wire [9 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
@@ -117,14 +117,14 @@ output wire [6 : 0] m_sc_payld;
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(4),
|
||||
.C_PAYLD_WIDTH(7),
|
||||
.C_PAYLD_WIDTH(10),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(2),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_SC_ROUTE_WIDTH(4),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
|
||||
+56
-26
@@ -11,14 +11,14 @@
|
||||
"S_PIPELINES": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_PIPELINES": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_LATENCY": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SI": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TESTING_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "140", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "142", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_S00_CONNECTIVITY": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_S01_CONNECTIVITY": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_S02_CONNECTIVITY": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_S03_CONNECTIVITY": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -274,21 +274,21 @@
|
||||
"Component_Name": [ { "value": "bd_962a_arsw_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_PAYLD_WIDTH": [ { "value": "140", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PAYLD_WIDTH": [ { "value": "142", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"K_MAX_INFO_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_PIPELINES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_PIPELINES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_LATENCY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_SI": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_SI": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TESTING_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CONNECTIVITY": [ { "value": "\"11\"", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ]
|
||||
"C_CONNECTIVITY": [ { "value": "0b1111", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
@@ -312,16 +312,16 @@
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aclken": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_sc_send": [ { "direction": "in", "size_left": "1", "size_right": "0" } ],
|
||||
"s_sc_req": [ { "direction": "in", "size_left": "1", "size_right": "0" } ],
|
||||
"s_sc_info": [ { "direction": "in", "size_left": "1", "size_right": "0" } ],
|
||||
"s_sc_payld": [ { "direction": "in", "size_left": "279", "size_right": "0" } ],
|
||||
"s_sc_recv": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_sc_recv": [ { "direction": "in", "size_left": "1", "size_right": "0" } ],
|
||||
"m_sc_send": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_sc_req": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_sc_info": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_sc_payld": [ { "direction": "out", "size_left": "139", "size_right": "0" } ]
|
||||
"s_sc_send": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s_sc_req": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s_sc_info": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s_sc_payld": [ { "direction": "in", "size_left": "567", "size_right": "0" } ],
|
||||
"s_sc_recv": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_sc_recv": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"m_sc_send": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_sc_req": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_sc_info": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_sc_payld": [ { "direction": "out", "size_left": "141", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"aclk": {
|
||||
@@ -331,7 +331,7 @@
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC:S00_SC:S01_SC:S02_SC:S03_SC:S04_SC:S05_SC:S06_SC:S07_SC:S08_SC:S09_SC:S10_SC:S11_SC:S12_SC:S13_SC:S14_SC:S15_SC", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -364,7 +364,7 @@
|
||||
"SEND": [ { "physical_name": "s_sc_send", "physical_left": "0", "physical_right": "0" } ],
|
||||
"REQ": [ { "physical_name": "s_sc_req", "physical_left": "0", "physical_right": "0" } ],
|
||||
"INFO": [ { "physical_name": "s_sc_info", "physical_left": "0", "physical_right": "0" } ],
|
||||
"PAYLD": [ { "physical_name": "s_sc_payld", "physical_left": "139", "physical_right": "0" } ],
|
||||
"PAYLD": [ { "physical_name": "s_sc_payld", "physical_left": "141", "physical_right": "0" } ],
|
||||
"RECV": [ { "physical_name": "s_sc_recv", "physical_left": "0", "physical_right": "0" } ]
|
||||
}
|
||||
},
|
||||
@@ -373,11 +373,11 @@
|
||||
"abstraction_type": "xilinx.com:interface:sc_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"RECV": [ { "physical_name": "m_sc_recv", "physical_left": "1", "physical_right": "0" } ],
|
||||
"SEND": [ { "physical_name": "m_sc_send", "physical_left": "1", "physical_right": "0" } ],
|
||||
"REQ": [ { "physical_name": "m_sc_req", "physical_left": "1", "physical_right": "0" } ],
|
||||
"INFO": [ { "physical_name": "m_sc_info", "physical_left": "1", "physical_right": "0" } ],
|
||||
"PAYLD": [ { "physical_name": "m_sc_payld", "physical_left": "139", "physical_right": "0" } ]
|
||||
"RECV": [ { "physical_name": "m_sc_recv", "physical_left": "3", "physical_right": "0" } ],
|
||||
"SEND": [ { "physical_name": "m_sc_send", "physical_left": "3", "physical_right": "0" } ],
|
||||
"REQ": [ { "physical_name": "m_sc_req", "physical_left": "3", "physical_right": "0" } ],
|
||||
"INFO": [ { "physical_name": "m_sc_info", "physical_left": "3", "physical_right": "0" } ],
|
||||
"PAYLD": [ { "physical_name": "m_sc_payld", "physical_left": "141", "physical_right": "0" } ]
|
||||
}
|
||||
},
|
||||
"S01_SC": {
|
||||
@@ -391,9 +391,39 @@
|
||||
"SEND": [ { "physical_name": "s_sc_send", "physical_left": "1", "physical_right": "1" } ],
|
||||
"REQ": [ { "physical_name": "s_sc_req", "physical_left": "1", "physical_right": "1" } ],
|
||||
"INFO": [ { "physical_name": "s_sc_info", "physical_left": "1", "physical_right": "1" } ],
|
||||
"PAYLD": [ { "physical_name": "s_sc_payld", "physical_left": "279", "physical_right": "140" } ],
|
||||
"PAYLD": [ { "physical_name": "s_sc_payld", "physical_left": "283", "physical_right": "142" } ],
|
||||
"RECV": [ { "physical_name": "s_sc_recv", "physical_left": "1", "physical_right": "1" } ]
|
||||
}
|
||||
},
|
||||
"S02_SC": {
|
||||
"vlnv": "xilinx.com:interface:sc:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:sc_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BRIDGES": [ { "value": "M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"SEND": [ { "physical_name": "s_sc_send", "physical_left": "2", "physical_right": "2" } ],
|
||||
"REQ": [ { "physical_name": "s_sc_req", "physical_left": "2", "physical_right": "2" } ],
|
||||
"INFO": [ { "physical_name": "s_sc_info", "physical_left": "2", "physical_right": "2" } ],
|
||||
"PAYLD": [ { "physical_name": "s_sc_payld", "physical_left": "425", "physical_right": "284" } ],
|
||||
"RECV": [ { "physical_name": "s_sc_recv", "physical_left": "2", "physical_right": "2" } ]
|
||||
}
|
||||
},
|
||||
"S03_SC": {
|
||||
"vlnv": "xilinx.com:interface:sc:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:sc_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BRIDGES": [ { "value": "M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"SEND": [ { "physical_name": "s_sc_send", "physical_left": "3", "physical_right": "3" } ],
|
||||
"REQ": [ { "physical_name": "s_sc_req", "physical_left": "3", "physical_right": "3" } ],
|
||||
"INFO": [ { "physical_name": "s_sc_info", "physical_left": "3", "physical_right": "3" } ],
|
||||
"PAYLD": [ { "physical_name": "s_sc_payld", "physical_left": "567", "physical_right": "426" } ],
|
||||
"RECV": [ { "physical_name": "s_sc_recv", "physical_left": "3", "physical_right": "3" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
+220
-216
File diff suppressed because it is too large
Load Diff
+23
-22
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -68,48 +68,49 @@ module bd_962a_arsw_0 (
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC:S00_SC:S01_SC:S02_SC:S03_SC:S04_SC:S05_SC:S06_SC:S07_SC:S08_SC:S09_SC:S10_SC:S11_SC:S12_SC:S13_SC:S14_SC:S15_SC, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC:S00_SC:S01_SC:S02_SC:S03_SC:S04_SC:S05_SC:S06_SC:S07_SC:S08_SC:S09_SC:S10_SC:S11_SC:S12_SC:S13_SC:S14_SC:S15_SC, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclken, POLARITY ACTIVE_LOW" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 aclken CE" *)
|
||||
input wire aclken;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC SEND [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC SEND [0:0] [1:1]" *)
|
||||
input wire [1 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC REQ [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC REQ [0:0] [1:1]" *)
|
||||
input wire [1 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC INFO [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC INFO [0:0] [1:1]" *)
|
||||
input wire [1 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC PAYLD [139:0] [139:0], xilinx.com:interface:sc:1.0 S01_SC PAYLD [139:0] [279:140]" *)
|
||||
input wire [279 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S01_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC RECV [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC RECV [0:0] [1:1]" *)
|
||||
output wire [1 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC SEND [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC SEND [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC SEND [0:0] [2:2], xilinx.com:interface:sc:1.0 S03_SC SEND [0:0] [3:3]" *)
|
||||
input wire [3 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC REQ [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC REQ [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC REQ [0:0] [2:2], xilinx.com:interface:sc:1.0 S03_SC REQ [0:0] [3:3]" *)
|
||||
input wire [3 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC INFO [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC INFO [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC INFO [0:0] [2:2], xilinx.com:interface:sc:1.0 S03_SC INFO [0:0] [3:3]" *)
|
||||
input wire [3 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC PAYLD [141:0] [141:0], xilinx.com:interface:sc:1.0 S01_SC PAYLD [141:0] [283:142], xilinx.com:interface:sc:1.0 S02_SC PAYLD [141:0] [425:284], xilinx.com:interface:sc:1.0 S03_SC PAYLD [141:0] [567:426]" *)
|
||||
input wire [567 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S01_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S02_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S03_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_\
|
||||
SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC RECV [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC RECV [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC RECV [0:0] [2:2], xilinx.com:interface:sc:1.0 S03_SC RECV [0:0] [3:3]" *)
|
||||
output wire [3 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC RECV" *)
|
||||
input wire [1 : 0] m_sc_recv;
|
||||
input wire [3 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC SEND" *)
|
||||
output wire [1 : 0] m_sc_send;
|
||||
output wire [3 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC REQ" *)
|
||||
output wire [1 : 0] m_sc_req;
|
||||
output wire [3 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC INFO" *)
|
||||
output wire [1 : 0] m_sc_info;
|
||||
output wire [3 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
output wire [141 : 0] m_sc_payld;
|
||||
|
||||
sc_switchboard_v1_0_6_top #(
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.C_PAYLD_WIDTH(142),
|
||||
.K_MAX_INFO_WIDTH(1),
|
||||
.C_S_PIPELINES(0),
|
||||
.C_M_PIPELINES(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_SI(2),
|
||||
.C_NUM_SI(4),
|
||||
.C_NUM_MI(1),
|
||||
.C_TESTING_MODE(0),
|
||||
.C_CONNECTIVITY(2'B11)
|
||||
.C_CONNECTIVITY(4'B1111)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(aclken),
|
||||
.connectivity(2'H3),
|
||||
.connectivity(4'B1111),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
|
||||
+24
-23
@@ -1,5 +1,5 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
@@ -52,7 +52,7 @@
|
||||
|
||||
(* X_CORE_INFO = "sc_switchboard_v1_0_6_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_arsw_0,sc_switchboard_v1_0_6_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_arsw_0,sc_switchboard_v1_0_6_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_switchboard,x_ipVersion=1.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_PAYLD_WIDTH=140,K_MAX_INFO_WIDTH=1,C_S_PIPELINES=0,C_M_PIPELINES=1,C_S_LATENCY=0,C_NUM_SI=2,C_NUM_MI=1,C_TESTING_MODE=0,C_CONNECTIVITY=11}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_arsw_0,sc_switchboard_v1_0_6_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_switchboard,x_ipVersion=1.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_PAYLD_WIDTH=142,K_MAX_INFO_WIDTH=1,C_S_PIPELINES=0,C_M_PIPELINES=1,C_S_LATENCY=0,C_NUM_SI=4,C_NUM_MI=1,C_TESTING_MODE=0,C_CONNECTIVITY=0b1111}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_arsw_0 (
|
||||
aclk,
|
||||
@@ -69,48 +69,49 @@ module bd_962a_arsw_0 (
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC:S00_SC:S01_SC:S02_SC:S03_SC:S04_SC:S05_SC:S06_SC:S07_SC:S08_SC:S09_SC:S10_SC:S11_SC:S12_SC:S13_SC:S14_SC:S15_SC, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC:S00_SC:S01_SC:S02_SC:S03_SC:S04_SC:S05_SC:S06_SC:S07_SC:S08_SC:S09_SC:S10_SC:S11_SC:S12_SC:S13_SC:S14_SC:S15_SC, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclken, POLARITY ACTIVE_LOW" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 aclken CE" *)
|
||||
input wire aclken;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC SEND [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC SEND [0:0] [1:1]" *)
|
||||
input wire [1 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC REQ [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC REQ [0:0] [1:1]" *)
|
||||
input wire [1 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC INFO [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC INFO [0:0] [1:1]" *)
|
||||
input wire [1 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC PAYLD [139:0] [139:0], xilinx.com:interface:sc:1.0 S01_SC PAYLD [139:0] [279:140]" *)
|
||||
input wire [279 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S01_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC RECV [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC RECV [0:0] [1:1]" *)
|
||||
output wire [1 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC SEND [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC SEND [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC SEND [0:0] [2:2], xilinx.com:interface:sc:1.0 S03_SC SEND [0:0] [3:3]" *)
|
||||
input wire [3 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC REQ [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC REQ [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC REQ [0:0] [2:2], xilinx.com:interface:sc:1.0 S03_SC REQ [0:0] [3:3]" *)
|
||||
input wire [3 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC INFO [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC INFO [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC INFO [0:0] [2:2], xilinx.com:interface:sc:1.0 S03_SC INFO [0:0] [3:3]" *)
|
||||
input wire [3 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC PAYLD [141:0] [141:0], xilinx.com:interface:sc:1.0 S01_SC PAYLD [141:0] [283:142], xilinx.com:interface:sc:1.0 S02_SC PAYLD [141:0] [425:284], xilinx.com:interface:sc:1.0 S03_SC PAYLD [141:0] [567:426]" *)
|
||||
input wire [567 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S01_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S02_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S03_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_\
|
||||
SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC RECV [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC RECV [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC RECV [0:0] [2:2], xilinx.com:interface:sc:1.0 S03_SC RECV [0:0] [3:3]" *)
|
||||
output wire [3 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC RECV" *)
|
||||
input wire [1 : 0] m_sc_recv;
|
||||
input wire [3 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC SEND" *)
|
||||
output wire [1 : 0] m_sc_send;
|
||||
output wire [3 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC REQ" *)
|
||||
output wire [1 : 0] m_sc_req;
|
||||
output wire [3 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC INFO" *)
|
||||
output wire [1 : 0] m_sc_info;
|
||||
output wire [3 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
output wire [141 : 0] m_sc_payld;
|
||||
|
||||
sc_switchboard_v1_0_6_top #(
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.C_PAYLD_WIDTH(142),
|
||||
.K_MAX_INFO_WIDTH(1),
|
||||
.C_S_PIPELINES(0),
|
||||
.C_M_PIPELINES(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_SI(2),
|
||||
.C_NUM_SI(4),
|
||||
.C_NUM_MI(1),
|
||||
.C_TESTING_MODE(0),
|
||||
.C_CONNECTIVITY(2'B11)
|
||||
.C_CONNECTIVITY(4'B1111)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(aclken),
|
||||
.connectivity(2'H3),
|
||||
.connectivity(4'B1111),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
|
||||
+2352
File diff suppressed because it is too large
Load Diff
+14450
File diff suppressed because it is too large
Load Diff
+313
@@ -0,0 +1,313 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_mmu:1.0
|
||||
// IP Revision: 11
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_s02mmu_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 128, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
|
||||
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_mmu_v1_0_11_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_SEG(1),
|
||||
.C_SEG_BASE_ADDR_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SIZE_ARRAY(32'H0000001d),
|
||||
.C_SEG_SEP_ROUTE_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SUPPORTS_READ_ARRAY(1'B1),
|
||||
.C_SEG_SUPPORTS_WRITE_ARRAY(1'B1),
|
||||
.C_SEG_SECURE_READ_ARRAY(1'B0),
|
||||
.C_SEG_SECURE_WRITE_ARRAY(1'B0),
|
||||
.C_NUM_MSC(1),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_MSC_ROUTE_ARRAY(1'B1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(0),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_AWUSER_WIDTH(0),
|
||||
.C_S_ARUSER_WIDTH(0),
|
||||
.C_S_RUSER_WIDTH(0),
|
||||
.C_S_WUSER_WIDTH(0),
|
||||
.C_S_BUSER_WIDTH(0),
|
||||
.C_S_PROTOCOL(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_SUPPORTS_WRAP(1),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_SUPPORTS_READ_DECERR(1),
|
||||
.C_SUPPORTS_WRITE_DECERR(1)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.aclken(1'B1),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(1'H0),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H00),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(1'H0),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(1'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
+315
@@ -0,0 +1,315 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_mmu:1.0
|
||||
// IP Revision: 11
|
||||
|
||||
(* X_CORE_INFO = "sc_mmu_v1_0_11_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_s02mmu_0,sc_mmu_v1_0_11_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_s02mmu_0,sc_mmu_v1_0_11_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_mmu,x_ipVersion=1.0,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_IS_CASCADED=0,C_ENABLE_PIPELINING=0x1,C_NUM_SEG=1,C_SEG_BASE_ADDR_ARRAY=0x0000000000000000,C_SEG_SIZE_ARRAY=0x0000001d,C_SEG_SEP_ROUTE_ARRAY=0x0000000000000000,C_SEG_SUPPORTS_READ_ARRAY=0b1,C_SEG_SUPPORTS_WRITE_ARRAY=0b1,C_SEG_SECURE_READ_ARRAY=0b0,C_SEG_SECURE_WRITE_ARRAY=0b0,C_NUM_MSC=1\
|
||||
,C_MSC_ROUTE_WIDTH=1,C_MSC_ROUTE_ARRAY=0b1,C_ADDR_WIDTH=32,C_ID_WIDTH=0,C_RDATA_WIDTH=32,C_WDATA_WIDTH=32,C_S_AWUSER_WIDTH=0,C_S_ARUSER_WIDTH=0,C_S_RUSER_WIDTH=0,C_S_WUSER_WIDTH=0,C_S_BUSER_WIDTH=0,C_S_PROTOCOL=0,C_READ_ACCEPTANCE=32,C_WRITE_ACCEPTANCE=32,C_NUM_READ_OUTSTANDING=2,C_NUM_WRITE_OUTSTANDING=16,C_SINGLE_ISSUING=0,C_SUPPORTS_WRAP=1,C_SUPPORTS_NARROW=0,C_SUPPORTS_READ_DECERR=1,C_SUPPORTS_WRITE_DECERR=1}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_s02mmu_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 128, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
|
||||
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_mmu_v1_0_11_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_SEG(1),
|
||||
.C_SEG_BASE_ADDR_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SIZE_ARRAY(32'H0000001d),
|
||||
.C_SEG_SEP_ROUTE_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SUPPORTS_READ_ARRAY(1'B1),
|
||||
.C_SEG_SUPPORTS_WRITE_ARRAY(1'B1),
|
||||
.C_SEG_SECURE_READ_ARRAY(1'B0),
|
||||
.C_SEG_SECURE_WRITE_ARRAY(1'B0),
|
||||
.C_NUM_MSC(1),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_MSC_ROUTE_ARRAY(1'B1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(0),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_AWUSER_WIDTH(0),
|
||||
.C_S_ARUSER_WIDTH(0),
|
||||
.C_S_RUSER_WIDTH(0),
|
||||
.C_S_WUSER_WIDTH(0),
|
||||
.C_S_BUSER_WIDTH(0),
|
||||
.C_S_PROTOCOL(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_SUPPORTS_WRAP(1),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_SUPPORTS_READ_DECERR(1),
|
||||
.C_SUPPORTS_WRITE_DECERR(1)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.aclken(1'B1),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(1'H0),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H00),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(1'H0),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(1'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
+289
@@ -0,0 +1,289 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_962a_s02tr_0",
|
||||
"cell_name": "s02_entry_pipeline/s02_transaction_regulator",
|
||||
"component_reference": "xilinx.com:ip:sc_transaction_regulator:1.0",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"IS_CASCADED": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_PIPELINING": [ { "value": "0x1", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"MEP_IDENTIFIER": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MEP_IDENTIFIER_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_ID_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_ID_WIDTH": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"WDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SEP_ROUTE_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"READ_ACCEPTANCE": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"WRITE_ACCEPTANCE": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SUPPORTS_READ_DEADLOCK": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SUPPORTS_WRITE_DEADLOCK": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SINGLE_ISSUING": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "bd_962a_s02tr_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_IS_CASCADED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_PIPELINING": [ { "value": "0x1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEP_IDENTIFIER_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEP_IDENTIFIER": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SEP_ROUTE_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_ID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SUPPORTS_READ_DEADLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SUPPORTS_WRITE_DEADLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_ACCEPTANCE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_ACCEPTANCE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_READ_OUTSTANDING": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_WRITE_OUTSTANDING": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SINGLE_ISSUING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "9" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awuser": [ { "direction": "in", "size_left": "1023", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
|
||||
"s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axi_wuser": [ { "direction": "in", "size_left": "1023", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_buser": [ { "direction": "out", "size_left": "1023", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_awid": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_axi_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_awuser": [ { "direction": "out", "size_left": "1023", "size_right": "0" } ],
|
||||
"m_axi_awvalid": [ { "direction": "out" } ],
|
||||
"m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_wlast": [ { "direction": "out" } ],
|
||||
"m_axi_wuser": [ { "direction": "out", "size_left": "1023", "size_right": "0" } ],
|
||||
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_bid": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_buser": [ { "direction": "in", "size_left": "1023", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_bready": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BRIDGES": [ { "value": "M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "s_axi_awqos" } ],
|
||||
"AWUSER": [ { "physical_name": "s_axi_awuser" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WUSER": [ { "physical_name": "s_axi_wuser" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BUSER": [ { "physical_name": "s_axi_buser" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWID": [ { "physical_name": "m_axi_awid" } ],
|
||||
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "m_axi_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "m_axi_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "m_axi_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "m_axi_awqos" } ],
|
||||
"AWUSER": [ { "physical_name": "m_axi_awuser" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "m_axi_wlast" } ],
|
||||
"WUSER": [ { "physical_name": "m_axi_wuser" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||
"BID": [ { "physical_name": "m_axi_bid" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||
"BUSER": [ { "physical_name": "m_axi_buser" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_bready" } ]
|
||||
}
|
||||
},
|
||||
"CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+4065
File diff suppressed because it is too large
Load Diff
+315
@@ -0,0 +1,315 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_transaction_regulator:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_s02tr_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCL\
|
||||
K_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [2 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [2 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_transaction_regulator_v1_0_9_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(3),
|
||||
.C_MEP_IDENTIFIER(5),
|
||||
.C_SEP_ROUTE_WIDTH(1),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_ID_WIDTH(0),
|
||||
.C_M_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_SUPPORTS_READ_DEADLOCK(0),
|
||||
.C_SUPPORTS_WRITE_DEADLOCK(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_SINGLE_ISSUING(0)
|
||||
) inst (
|
||||
.mep_identifier(3'H5),
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1024'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(3'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
+317
@@ -0,0 +1,317 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_transaction_regulator:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
(* X_CORE_INFO = "sc_transaction_regulator_v1_0_9_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_s02tr_0,sc_transaction_regulator_v1_0_9_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_s02tr_0,sc_transaction_regulator_v1_0_9_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_transaction_regulator,x_ipVersion=1.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_IS_CASCADED=0,C_ENABLE_PIPELINING=0x1,C_NUM_READ_THREADS=1,C_NUM_WRITE_THREADS=1,C_MEP_IDENTIFIER_WIDTH=3,C_MEP_IDENTIFIER=5,C_SEP_ROUTE_WIDTH=1,C_RDATA_WIDTH=32,C_WDATA_WIDTH=32,C_S_ID_WIDTH=0,C_M_ID_WIDTH=3,C_ADDR_WIDTH=32,C_SUPPORTS_READ_DEADLOCK=0,C_SU\
|
||||
PPORTS_WRITE_DEADLOCK=0,C_READ_ACCEPTANCE=32,C_WRITE_ACCEPTANCE=32,C_NUM_READ_OUTSTANDING=2,C_NUM_WRITE_OUTSTANDING=16,C_SINGLE_ISSUING=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_s02tr_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCL\
|
||||
K_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [2 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [2 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_transaction_regulator_v1_0_9_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(3),
|
||||
.C_MEP_IDENTIFIER(5),
|
||||
.C_SEP_ROUTE_WIDTH(1),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_ID_WIDTH(0),
|
||||
.C_M_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_SUPPORTS_READ_DEADLOCK(0),
|
||||
.C_SUPPORTS_WRITE_DEADLOCK(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_SINGLE_ISSUING(0)
|
||||
) inst (
|
||||
.mep_identifier(3'H5),
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1024'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(3'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
+1587
File diff suppressed because it is too large
Load Diff
+10465
File diff suppressed because it is too large
Load Diff
+319
@@ -0,0 +1,319 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_si_converter:1.0
|
||||
// IP Revision: 11
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_s02sic_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [2 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [2 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCL\
|
||||
K_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [2 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [2 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_si_converter_v1_0_11_top #(
|
||||
.C_AXILITE_CONV(0),
|
||||
.C_LIMIT_WRITE_LENGTH(0),
|
||||
.C_LIMIT_READ_LENGTH(0),
|
||||
.C_WRITE_WATERMARK(0),
|
||||
.C_READ_WATERMARK(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(3),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_HAS_BURST(0),
|
||||
.C_NUM_SEG(1),
|
||||
.C_SEP_WDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_SEP_RDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_SEP_PROTOCOL_ARRAY(32'H00000001),
|
||||
.C_NUM_MSC(1),
|
||||
.C_MSC_WDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_MSC_RDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_S_WUSER_BITS_PER_BYTE(0),
|
||||
.C_S_RUSER_BITS_PER_BYTE(0),
|
||||
.C_MAX_WUSER_BITS_PER_BYTE(0),
|
||||
.C_MAX_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(2'H1),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(3'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1024'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(3'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
+321
@@ -0,0 +1,321 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_si_converter:1.0
|
||||
// IP Revision: 11
|
||||
|
||||
(* X_CORE_INFO = "sc_si_converter_v1_0_11_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_962a_s02sic_0,sc_si_converter_v1_0_11_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_962a_s02sic_0,sc_si_converter_v1_0_11_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_si_converter,x_ipVersion=1.0,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_AXILITE_CONV=0,C_LIMIT_WRITE_LENGTH=0,C_LIMIT_READ_LENGTH=0,C_WRITE_WATERMARK=0,C_READ_WATERMARK=0,C_ENABLE_PIPELINING=0x1,C_IS_CASCADED=0,C_NUM_WRITE_THREADS=1,C_NUM_READ_THREADS=1,C_MEP_IDENTIFIER_WIDTH=3,C_SUPPORTS_NARROW=0,C_HAS_BURST=0,C_NUM_SEG=1,C_SEP_WDATA_WIDTH_ARRAY=0x000000\
|
||||
20,C_SEP_RDATA_WIDTH_ARRAY=0x00000020,C_SEP_PROTOCOL_ARRAY=0x00000001,C_NUM_MSC=1,C_MSC_WDATA_WIDTH_ARRAY=0x00000020,C_MSC_RDATA_WIDTH_ARRAY=0x00000020,C_ADDR_WIDTH=32,C_ID_WIDTH=3,C_WDATA_WIDTH=32,C_RDATA_WIDTH=32,C_S_WUSER_BITS_PER_BYTE=0,C_S_RUSER_BITS_PER_BYTE=0,C_MAX_WUSER_BITS_PER_BYTE=0,C_MAX_RUSER_BITS_PER_BYTE=0,C_SINGLE_ISSUING=0,C_NUM_READ_OUTSTANDING=2,C_NUM_WRITE_OUTSTANDING=16,C_READ_ACCEPTANCE=32,C_WRITE_ACCEPTANCE=32}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_962a_s02sic_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [2 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [2 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCL\
|
||||
K_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [2 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [2 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
|
||||
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_si_converter_v1_0_11_top #(
|
||||
.C_AXILITE_CONV(0),
|
||||
.C_LIMIT_WRITE_LENGTH(0),
|
||||
.C_LIMIT_READ_LENGTH(0),
|
||||
.C_WRITE_WATERMARK(0),
|
||||
.C_READ_WATERMARK(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(3),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_HAS_BURST(0),
|
||||
.C_NUM_SEG(1),
|
||||
.C_SEP_WDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_SEP_RDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_SEP_PROTOCOL_ARRAY(32'H00000001),
|
||||
.C_NUM_MSC(1),
|
||||
.C_MSC_WDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_MSC_RDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_S_WUSER_BITS_PER_BYTE(0),
|
||||
.C_S_RUSER_BITS_PER_BYTE(0),
|
||||
.C_MAX_WUSER_BITS_PER_BYTE(0),
|
||||
.C_MAX_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(2'H1),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(3'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1024'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(3'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
+234
@@ -0,0 +1,234 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_962a_s02a2s_0",
|
||||
"cell_name": "s02_axi2sc",
|
||||
"component_reference": "xilinx.com:ip:sc_axi2sc:1.0",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_RDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_WDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_RDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_WDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ARUSER_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_AWUSER_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_BUSER_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MSC_ROUTE_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SSC_ROUTE_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "bd_962a_s02a2s_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ARUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MSC_ROUTE_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SSC_ROUTE_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AWPAYLD_WIDTH": [ { "value": "142", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_ARPAYLD_WIDTH": [ { "value": "142", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_WPAYLD_WIDTH": [ { "value": "52", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_RPAYLD_WIDTH": [ { "value": "56", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_BPAYLD_WIDTH": [ { "value": "10", "resolve_type": "dependent", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "8" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"s_sc_b_req": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_sc_b_info": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_b_send": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_sc_b_recv": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_sc_b_payld": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_sc_aw_req": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"m_sc_aw_info": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_sc_aw_send": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"m_sc_aw_recv": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_sc_aw_payld": [ { "direction": "out", "size_left": "141", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_sc_w_req": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"m_sc_w_info": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_sc_w_send": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"m_sc_w_recv": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_sc_w_payld": [ { "direction": "out", "size_left": "51", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awid": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awuser": [ { "direction": "in", "size_left": "1023", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
|
||||
"s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axi_wuser": [ { "direction": "in", "size_left": "1023", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bid": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_buser": [ { "direction": "out", "size_left": "1023", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_SC_B": {
|
||||
"vlnv": "xilinx.com:interface:sc:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:sc_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"INFO": [ { "physical_name": "s_sc_b_info" } ],
|
||||
"PAYLD": [ { "physical_name": "s_sc_b_payld" } ],
|
||||
"RECV": [ { "physical_name": "s_sc_b_recv" } ],
|
||||
"REQ": [ { "physical_name": "s_sc_b_req" } ],
|
||||
"SEND": [ { "physical_name": "s_sc_b_send" } ]
|
||||
}
|
||||
},
|
||||
"M_SC_AW": {
|
||||
"vlnv": "xilinx.com:interface:sc:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:sc_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"INFO": [ { "physical_name": "m_sc_aw_info" } ],
|
||||
"PAYLD": [ { "physical_name": "m_sc_aw_payld" } ],
|
||||
"RECV": [ { "physical_name": "m_sc_aw_recv" } ],
|
||||
"REQ": [ { "physical_name": "m_sc_aw_req" } ],
|
||||
"SEND": [ { "physical_name": "m_sc_aw_send" } ]
|
||||
}
|
||||
},
|
||||
"M_SC_W": {
|
||||
"vlnv": "xilinx.com:interface:sc:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:sc_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"INFO": [ { "physical_name": "m_sc_w_info" } ],
|
||||
"PAYLD": [ { "physical_name": "m_sc_w_payld" } ],
|
||||
"RECV": [ { "physical_name": "m_sc_w_recv" } ],
|
||||
"REQ": [ { "physical_name": "m_sc_w_req" } ],
|
||||
"SEND": [ { "physical_name": "m_sc_w_send" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "1024", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWID": [ { "physical_name": "s_axi_awid" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "s_axi_awqos" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWUSER": [ { "physical_name": "s_axi_awuser" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BID": [ { "physical_name": "s_axi_bid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BUSER": [ { "physical_name": "s_axi_buser" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WUSER": [ { "physical_name": "s_axi_wuser" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+2920
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user