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c64_pro.runs/impl_1/c64pro_top_placed.dcp
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c64_pro.runs/impl_1/c64pro_top_power_routed.rpt
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@@ -1,11 +1,11 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 | Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Sun Aug 4 13:44:39 2024 | Date : Fri Sep 4 15:41:33 2026
| Host : 840-5CG14025H4 running 64-bit major release (build 9200) | Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
| Command : report_power -file c64pro_top_power_routed.rpt -pb c64pro_top_power_summary_routed.pb -rpx c64pro_top_power_routed.rpx | Command : report_power -file c64pro_top_power_routed.rpt -pb c64pro_top_power_summary_routed.pb -rpx c64pro_top_power_routed.rpx
| Design : c64pro_top | Design : c64pro_top
| Device : xc7z010clg400-2 | Device : xc7z020clg400-2
| Design State : routed | Design State : routed
| Grade : commercial | Grade : commercial
| Process : typical | Process : typical
@@ -30,14 +30,14 @@ Table of Contents
---------- ----------
+--------------------------+--------------+ +--------------------------+--------------+
| Total On-Chip Power (W) | 1.263 | | Total On-Chip Power (W) | 1.582 |
| Design Power Budget (W) | Unspecified* | | Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA | | Power Budget Margin (W) | NA |
| Dynamic (W) | 1.145 | | Dynamic (W) | 1.431 |
| Device Static (W) | 0.118 | | Device Static (W) | 0.151 |
| Effective TJA (C/W) | 11.5 | | Effective TJA (C/W) | 11.5 |
| Max Ambient (C) | 70.4 | | Max Ambient (C) | 66.7 |
| Junction Temperature (C) | 39.6 | | Junction Temperature (C) | 43.3 |
| Confidence Level | Low | | Confidence Level | Low |
| Setting File | --- | | Setting File | --- |
| Simulation Activity File | --- | | Simulation Activity File | --- |
@@ -52,22 +52,21 @@ Table of Contents
+--------------------------+-----------+----------+-----------+-----------------+ +--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) | | On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+ +--------------------------+-----------+----------+-----------+-----------------+
| Clocks | 0.033 | 3 | --- | --- | | Clocks | 0.099 | 4 | --- | --- |
| Slice Logic | 0.021 | 37606 | --- | --- | | Slice Logic | 0.038 | 70198 | --- | --- |
| LUT as Logic | 0.019 | 11627 | 17600 | 66.06 | | LUT as Logic | 0.034 | 21761 | 53200 | 40.90 |
| CARRY4 | <0.001 | 565 | 4400 | 12.84 | | Register | 0.002 | 33794 | 106400 | 31.76 |
| Register | <0.001 | 18749 | 35200 | 53.26 | | CARRY4 | 0.001 | 988 | 13300 | 7.43 |
| LUT as Distributed RAM | <0.001 | 444 | 6000 | 7.40 | | F7/F8 Muxes | <0.001 | 2664 | 53200 | 5.01 |
| F7/F8 Muxes | <0.001 | 1473 | 17600 | 8.37 | | LUT as Distributed RAM | <0.001 | 558 | 17400 | 3.21 |
| LUT as Shift Register | <0.001 | 141 | 6000 | 2.35 | | LUT as Shift Register | <0.001 | 1005 | 17400 | 5.78 |
| BUFG | <0.001 | 4 | 32 | 12.50 | | Others | 0.000 | 3660 | --- | --- |
| Others | 0.000 | 1299 | --- | --- | | Signals | 0.050 | 46880 | --- | --- |
| Signals | 0.033 | 26449 | --- | --- | | Block RAM | 0.062 | 105 | 140 | 75.00 |
| Block RAM | 0.012 | 26 | 60 | 43.33 | | I/O | 0.008 | 58 | 125 | 46.40 |
| I/O | 0.003 | 76 | 100 | 76.00 | | PS7 | 1.175 | 1 | --- | --- |
| PS7 | 1.043 | 1 | --- | --- | | Static Power | 0.151 | | | |
| Static Power | 0.118 | | | | | Total | 1.582 | | | |
| Total | 1.263 | | | |
+--------------------------+-----------+----------+-----------+-----------------+ +--------------------------+-----------+----------+-----------+-----------------+
@@ -77,25 +76,25 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint | 1.000 | 0.105 | 0.098 | 0.007 | NA | Unspecified | NA | | Vccint | 1.000 | 0.261 | 0.244 | 0.018 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.007 | 0.000 | 0.007 | NA | Unspecified | NA | | Vccaux | 1.800 | 0.015 | 0.000 | 0.015 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.002 | 0.001 | 0.001 | NA | Unspecified | NA | | Vcco33 | 3.300 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccbram | 1.000 | 0.003 | 0.001 | 0.002 | NA | Unspecified | NA | | Vccbram | 1.000 | 0.012 | 0.005 | 0.007 | NA | Unspecified | NA |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccpint | 1.000 | 0.573 | 0.547 | 0.025 | NA | Unspecified | NA | | Vccpint | 1.000 | 0.707 | 0.678 | 0.029 | NA | Unspecified | NA |
| Vccpaux | 1.800 | 0.035 | 0.025 | 0.010 | NA | Unspecified | NA | | Vccpaux | 1.800 | 0.035 | 0.025 | 0.010 | NA | Unspecified | NA |
| Vccpll | 1.800 | 0.018 | 0.015 | 0.003 | NA | Unspecified | NA | | Vccpll | 1.800 | 0.017 | 0.014 | 0.003 | NA | Unspecified | NA |
| Vcco_ddr | 1.350 | 0.311 | 0.309 | 0.002 | NA | Unspecified | NA | | Vcco_ddr | 1.350 | 0.311 | 0.309 | 0.002 | NA | Unspecified | NA |
| Vcco_mio0 | 3.300 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA | | Vcco_mio0 | 3.300 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
| Vcco_mio1 | 1.800 | 0.002 | 0.001 | 0.001 | NA | Unspecified | NA | | Vcco_mio1 | 1.800 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | | Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
@@ -137,11 +136,12 @@ Table of Contents
2.2 Clock Constraints 2.2 Clock Constraints
--------------------- ---------------------
+------------+--------------------------------------------------------------------------+-----------------+ +--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) | | Clock | Domain | Constraint (ns) |
+------------+--------------------------------------------------------------------------+-----------------+ +--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------+
| clk_fpga_0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | 10.0 | | clk_fpga_0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | 10.0 |
+------------+--------------------------------------------------------------------------+-----------------+ | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TCK | 33.0 |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------+
3. Detailed Reports 3. Detailed Reports
@@ -150,33 +150,53 @@ Table of Contents
3.1 By Hierarchy 3.1 By Hierarchy
---------------- ----------------
+-------------------------------+-----------+ +---------------------------------------------+-----------+
| Name | Power (W) | | Name | Power (W) |
+-------------------------------+-----------+ +---------------------------------------------+-----------+
| c64pro_top | 1.145 | | c64pro_top | 1.431 |
| u_pl_top | 0.043 | | dbg_hub | 0.003 |
| u_eeg_top | 0.007 | | inst | 0.003 |
| u_eeg_upload | 0.002 | | BSCANID.u_xsdbm_id | 0.003 |
| u_rhs2116_top | 0.017 | | u_ila_0 | 0.040 |
| u_sine_wave_gen | 0.003 | | inst | 0.040 |
| u_trans_distribute | 0.003 | | ila_core_inst | 0.040 |
| u_transmit_config | 0.005 | | u_pl_top | 0.082 |
| u_upload_top | 0.018 | | u0_eeg_top | 0.005 |
| u_upload_config | 0.005 | | transmit_arrange[0].u_ads1299_arrange | 0.001 |
| u_upload_protocol_intan | 0.002 | | u_eeg_upload | 0.001 |
| u_upload_protocol_ql | 0.003 | | u0_upload_top | 0.033 |
| u_upload_sort | 0.008 | | u_upload_config | 0.015 |
| u_ps_a9_1 | 1.098 | | u_upload_protocol_intan | 0.003 |
| design_a9_1_i | 1.089 | | u_upload_protocol_ql | 0.004 |
| axi_dma_0 | 0.002 | | u_upload_sort | 0.010 |
| axi_dma_1 | 0.003 | | u1_eeg_top | 0.002 |
| axi_iic_0 | 0.001 | | u1_upload_top | 0.029 |
| axi_iic_1 | 0.001 | | u_upload_config | 0.012 |
| axi_smc | 0.010 | | u_upload_protocol_intan | 0.003 |
| axis_data_fifo_0 | 0.004 | | u_upload_protocol_ql | 0.004 |
| axis_data_fifo_1 | 0.006 | | u_upload_sort | 0.009 |
| processing_system7_0 | 1.043 | | u_cur_mon_top | 0.010 |
| smartconnect_0 | 0.016 | | u0_fifo_generator_1 | 0.002 |
+-------------------------------+-----------+ | u_cur_mon_config | 0.002 |
| u_cur_monitor | 0.001 |
| u_vio_cur_flt_state | 0.002 |
| u_eeg_emg_upload | 0.003 |
| u0_fifo_generator_0 | 0.003 |
| u_ps_a9_1 | 1.304 |
| design_a9_1_i | 1.298 |
| CUR_SPI | 0.004 |
| STIM_SPI | 0.004 |
| ZCHECK_SPI | 0.004 |
| axi_dma_0 | 0.002 |
| axi_dma_1 | 0.005 |
| axi_dma_2 | 0.005 |
| axi_dma_3 | 0.005 |
| axi_smc | 0.020 |
| axis_data_fifo_1 | 0.001 |
| axis_data_fifo_2 | 0.012 |
| axis_data_fifo_3 | 0.033 |
| processing_system7_0 | 1.175 |
| smartconnect_0 | 0.025 |
+---------------------------------------------+-----------+
c64_pro.runs/impl_1/c64pro_top_power_routed.rpx
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c64_pro.runs/impl_1/c64pro_top_power_summary_routed.pb
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c64_pro.runs/impl_1/c64pro_top_route_status.pb
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c64_pro.runs/impl_1/c64pro_top_route_status.rpt
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Design Route Status Design Route Status
: # nets : : # nets :
------------------------------------------- : ----------- : ------------------------------------------- : ----------- :
# of logical nets.......................... : 43247 : # of logical nets.......................... : 84782 :
# of nets not needing routing.......... : 16664 : # of nets not needing routing.......... : 37766 :
# of internally routed nets........ : 16304 : # of internally routed nets........ : 37183 :
# of nets with no loads............ : 360 : # of nets with no loads............ : 583 :
# of routable nets..................... : 26583 : # of routable nets..................... : 47016 :
# of fully routed nets............. : 26583 : # of fully routed nets............. : 47016 :
# of nets with routing errors.......... : 0 : # of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- : ------------------------------------------- : ----------- :
c64_pro.runs/impl_1/c64pro_top_routed.dcp
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c64_pro.runs/impl_1/c64pro_top_timing_summary_routed.pb
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c64_pro.runs/impl_1/c64pro_top_timing_summary_routed.rpt
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c64_pro.runs/impl_1/c64pro_top_timing_summary_routed.rpx
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c64_pro.runs/impl_1/c64pro_top_utilization_placed.pb
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c64_pro.runs/impl_1/c64pro_top_utilization_placed.rpt
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 | Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Sun Aug 4 13:42:57 2024 | Date : Fri Sep 4 15:37:38 2026
| Host : 840-5CG14025H4 running 64-bit major release (build 9200) | Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
| Command : report_utilization -file c64pro_top_utilization_placed.rpt -pb c64pro_top_utilization_placed.pb | Command : report_utilization -file c64pro_top_utilization_placed.rpt -pb c64pro_top_utilization_placed.pb
| Design : c64pro_top | Design : c64pro_top
| Device : xc7z010clg400-2 | Device : xc7z020clg400-2
| Speed File : -2 | Speed File : -2
| Design State : Fully Placed | Design State : Fully Placed
--------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------
@@ -32,16 +32,16 @@ Table of Contents
+----------------------------+-------+-------+------------+-----------+-------+ +----------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% | | Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+-------+-------+------------+-----------+-------+ +----------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs | 12212 | 0 | 0 | 17600 | 69.39 | | Slice LUTs | 23324 | 0 | 0 | 53200 | 43.84 |
| LUT as Logic | 11627 | 0 | 0 | 17600 | 66.06 | | LUT as Logic | 21761 | 0 | 0 | 53200 | 40.90 |
| LUT as Memory | 585 | 0 | 0 | 6000 | 9.75 | | LUT as Memory | 1563 | 0 | 0 | 17400 | 8.98 |
| LUT as Distributed RAM | 444 | 0 | | | | | LUT as Distributed RAM | 558 | 0 | | | |
| LUT as Shift Register | 141 | 0 | | | | | LUT as Shift Register | 1005 | 0 | | | |
| Slice Registers | 18749 | 0 | 0 | 35200 | 53.26 | | Slice Registers | 33794 | 0 | 0 | 106400 | 31.76 |
| Register as Flip Flop | 18621 | 0 | 0 | 35200 | 52.90 | | Register as Flip Flop | 33794 | 0 | 0 | 106400 | 31.76 |
| Register as Latch | 128 | 0 | 0 | 35200 | 0.36 | | Register as Latch | 0 | 0 | 0 | 106400 | 0.00 |
| F7 Muxes | 1013 | 0 | 0 | 8800 | 11.51 | | F7 Muxes | 1872 | 0 | 0 | 26600 | 7.04 |
| F8 Muxes | 460 | 0 | 0 | 4400 | 10.45 | | F8 Muxes | 792 | 0 | 0 | 13300 | 5.95 |
+----------------------------+-------+-------+------------+-----------+-------+ +----------------------------+-------+-------+------------+-----------+-------+
* Warning! LUT value is adjusted to account for LUT combining. * Warning! LUT value is adjusted to account for LUT combining.
@@ -58,10 +58,10 @@ Table of Contents
| 0 | _ | Set | - | | 0 | _ | Set | - |
| 0 | _ | Reset | - | | 0 | _ | Reset | - |
| 0 | Yes | - | - | | 0 | Yes | - | - |
| 370 | Yes | - | Set | | 90 | Yes | - | Set |
| 11101 | Yes | - | Reset | | 12487 | Yes | - | Reset |
| 535 | Yes | Set | - | | 859 | Yes | Set | - |
| 6743 | Yes | Reset | - | | 20367 | Yes | Reset | - |
+-------+--------------+-------------+--------------+ +-------+--------------+-------------+--------------+
@@ -71,28 +71,28 @@ Table of Contents
+--------------------------------------------+-------+-------+------------+-----------+-------+ +--------------------------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% | | Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+-------+-------+------------+-----------+-------+ +--------------------------------------------+-------+-------+------------+-----------+-------+
| Slice | 4395 | 0 | 0 | 4400 | 99.89 | | Slice | 11328 | 0 | 0 | 13300 | 85.17 |
| SLICEL | 2897 | 0 | | | | | SLICEL | 7545 | 0 | | | |
| SLICEM | 1498 | 0 | | | | | SLICEM | 3783 | 0 | | | |
| LUT as Logic | 11627 | 0 | 0 | 17600 | 66.06 | | LUT as Logic | 21761 | 0 | 0 | 53200 | 40.90 |
| using O5 output only | 0 | | | | | | using O5 output only | 0 | | | | |
| using O6 output only | 8850 | | | | | | using O6 output only | 17358 | | | | |
| using O5 and O6 | 2777 | | | | | | using O5 and O6 | 4403 | | | | |
| LUT as Memory | 585 | 0 | 0 | 6000 | 9.75 | | LUT as Memory | 1563 | 0 | 0 | 17400 | 8.98 |
| LUT as Distributed RAM | 444 | 0 | | | | | LUT as Distributed RAM | 558 | 0 | | | |
| using O5 output only | 0 | | | | | | using O5 output only | 0 | | | | |
| using O6 output only | 4 | | | | | | using O6 output only | 6 | | | | |
| using O5 and O6 | 440 | | | | | | using O5 and O6 | 552 | | | | |
| LUT as Shift Register | 141 | 0 | | | | | LUT as Shift Register | 1005 | 0 | | | |
| using O5 output only | 0 | | | | | | using O5 output only | 7 | | | | |
| using O6 output only | 54 | | | | | | using O6 output only | 185 | | | | |
| using O5 and O6 | 87 | | | | | | using O5 and O6 | 813 | | | | |
| Slice Registers | 18749 | 0 | 0 | 35200 | 53.26 | | Slice Registers | 33794 | 0 | 0 | 106400 | 31.76 |
| Register driven from within the Slice | 7217 | | | | | | Register driven from within the Slice | 15274 | | | | |
| Register driven from outside the Slice | 11532 | | | | | | Register driven from outside the Slice | 18520 | | | | |
| LUT in front of the register is unused | 7275 | | | | | | LUT in front of the register is unused | 14377 | | | | |
| LUT in front of the register is used | 4257 | | | | | | LUT in front of the register is used | 4143 | | | | |
| Unique Control Sets | 1031 | | 0 | 4400 | 23.43 | | Unique Control Sets | 1907 | | 0 | 13300 | 14.34 |
+--------------------------------------------+-------+-------+------------+-----------+-------+ +--------------------------------------------+-------+-------+------------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. * * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
@@ -103,11 +103,11 @@ Table of Contents
+-------------------+------+-------+------------+-----------+-------+ +-------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% | | Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------+------+-------+------------+-----------+-------+ +-------------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 26 | 0 | 0 | 60 | 43.33 | | Block RAM Tile | 105 | 0 | 0 | 140 | 75.00 |
| RAMB36/FIFO* | 24 | 0 | 0 | 60 | 40.00 | | RAMB36/FIFO* | 102 | 0 | 0 | 140 | 72.86 |
| RAMB36E1 only | 24 | | | | | | RAMB36E1 only | 102 | | | | |
| RAMB18 | 4 | 0 | 0 | 120 | 3.33 | | RAMB18 | 6 | 0 | 0 | 280 | 2.14 |
| RAMB18E1 only | 4 | | | | | | RAMB18E1 only | 6 | | | | |
+-------------------+------+-------+------------+-----------+-------+ +-------------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -118,7 +118,7 @@ Table of Contents
+-----------+------+-------+------------+-----------+-------+ +-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% | | Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+ +-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 80 | 0.00 | | DSPs | 0 | 0 | 0 | 220 | 0.00 |
+-----------+------+-------+------------+-----------+-------+ +-----------+------+-------+------------+-----------+-------+
@@ -128,22 +128,25 @@ Table of Contents
+-----------------------------+------+-------+------------+-----------+--------+ +-----------------------------+------+-------+------------+-----------+--------+
| Site Type | Used | Fixed | Prohibited | Available | Util% | | Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+--------+ +-----------------------------+------+-------+------------+-----------+--------+
| Bonded IOB | 76 | 76 | 0 | 100 | 76.00 | | Bonded IOB | 58 | 58 | 0 | 125 | 46.40 |
| IOB Master Pads | 37 | | | | | | IOB Master Pads | 22 | | | | |
| IOB Slave Pads | 35 | | | | | | IOB Slave Pads | 34 | | | | |
| IOB Flip Flops | 9 | 9 | | | |
| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | | Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 130 | 130 | 0 | 130 | 100.00 | | Bonded IOPADs | 130 | 130 | 0 | 130 | 100.00 |
| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 | | PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 | | PHASER_REF | 0 | 0 | 0 | 4 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 | | OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 | | IN_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 | | IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 96 | 0.00 | | IBUFDS | 0 | 0 | 0 | 121 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 | | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 | | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 100 | 0.00 | | ILOGIC | 6 | 6 | 0 | 125 | 4.80 |
| OLOGIC | 0 | 0 | 0 | 100 | 0.00 | | IFF_Register | 6 | 6 | | | |
| OLOGIC | 3 | 3 | 0 | 125 | 2.40 |
| OUTFF_Register | 3 | 3 | | | |
+-----------------------------+------+-------+------------+-----------+--------+ +-----------------------------+------+-------+------------+-----------+--------+
@@ -153,13 +156,13 @@ Table of Contents
+------------+------+-------+------------+-----------+-------+ +------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% | | Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+ +------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 | | BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
| BUFIO | 0 | 0 | 0 | 8 | 0.00 | | BUFIO | 0 | 0 | 0 | 16 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 | | MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 | | PLLE2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 | | BUFMRCE | 0 | 0 | 0 | 8 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 48 | 0.00 | | BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 0 | 8 | 0.00 | | BUFR | 0 | 0 | 0 | 16 | 0.00 |
+------------+------+-------+------------+-----------+-------+ +------------+------+-------+------------+-----------+-------+
@@ -169,7 +172,7 @@ Table of Contents
+-------------+------+-------+------------+-----------+-------+ +-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% | | Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+ +-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | | BSCANE2 | 1 | 0 | 0 | 4 | 25.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | | CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | | DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | | EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
@@ -186,31 +189,33 @@ Table of Contents
+----------+-------+----------------------+ +----------+-------+----------------------+
| Ref Name | Used | Functional Category | | Ref Name | Used | Functional Category |
+----------+-------+----------------------+ +----------+-------+----------------------+
| FDCE | 10973 | Flop & Latch | | FDRE | 20367 | Flop & Latch |
| FDRE | 6743 | Flop & Latch | | FDCE | 12487 | Flop & Latch |
| LUT6 | 5463 | LUT | | LUT6 | 9778 | LUT |
| LUT3 | 2377 | LUT | | LUT3 | 4324 | LUT |
| LUT5 | 2076 | LUT | | LUT2 | 3478 | LUT |
| LUT2 | 1977 | LUT | | LUT4 | 3448 | LUT |
| LUT4 | 1895 | LUT | | LUT5 | 3330 | LUT |
| MUXF7 | 1013 | MuxFx | | MUXF7 | 1872 | MuxFx |
| RAMD32 | 666 | Distributed Memory | | LUT1 | 1806 | LUT |
| LUT1 | 616 | LUT | | SRL16E | 1288 | Distributed Memory |
| CARRY4 | 565 | CarryLogic | | CARRY4 | 988 | CarryLogic |
| FDSE | 535 | Flop & Latch | | FDSE | 859 | Flop & Latch |
| MUXF8 | 460 | MuxFx | | RAMD32 | 840 | Distributed Memory |
| FDPE | 370 | Flop & Latch | | MUXF8 | 792 | MuxFx |
| SRL16E | 228 | Distributed Memory | | SRLC32E | 528 | Distributed Memory |
| RAMS32 | 218 | Distributed Memory | | RAMS32 | 270 | Distributed Memory |
| BIBUF | 130 | IO | | BIBUF | 130 | IO |
| LDCE | 128 | Flop & Latch | | RAMB36E1 | 102 | Block Memory |
| OBUF | 56 | IO | | FDPE | 90 | Flop & Latch |
| RAMB36E1 | 24 | Block Memory | | IBUF | 32 | IO |
| IBUF | 20 | IO | | OBUFT | 27 | IO |
| BUFG | 5 | Clock | | OBUF | 26 | IO |
| RAMB18E1 | 4 | Block Memory | | RAMB18E1 | 6 | Block Memory |
| OBUFT | 4 | IO | | SRLC16E | 2 | Distributed Memory |
| BUFG | 2 | Clock |
| PS7 | 1 | Specialized Resource | | PS7 | 1 | Specialized Resource |
| BSCANE2 | 1 | Others |
+----------+-------+----------------------+ +----------+-------+----------------------+
@@ -228,27 +233,43 @@ Table of Contents
+------------------------------------+------+ +------------------------------------+------+
| Ref Name | Used | | Ref Name | Used |
+------------------------------------+------+ +------------------------------------+------+
| mult_gen_au8_bu9_p8 | 4 | | c_add_s16_s32 | 3 |
| axis_data_fifo_w32_d32 | 4 | | axis_data_fifo_w8_d128 | 2 |
| vio_cur_flt_state | 1 |
| u_ila_0 | 1 |
| fifo_generator_1 | 1 |
| fifo_generator_0 | 1 |
| design_a9_1_smartconnect_0_0 | 1 | | design_a9_1_smartconnect_0_0 | 1 |
| design_a9_1_rst_ps7_0_50M_0 | 1 | | design_a9_1_rst_ps7_0_50M_0 | 1 |
| design_a9_1_processing_system7_0_0 | 1 | | design_a9_1_processing_system7_0_0 | 1 |
| design_a9_1_axis_data_fifo_2_0 | 1 |
| design_a9_1_axis_data_fifo_1_1 | 1 |
| design_a9_1_axis_data_fifo_1_0 | 1 | | design_a9_1_axis_data_fifo_1_0 | 1 |
| design_a9_1_axis_data_fifo_0_0 | 1 | | design_a9_1_axis_data_fifo_0_0 | 1 |
| design_a9_1_axi_smc_0 | 1 | | design_a9_1_axi_smc_0 | 1 |
| design_a9_1_axi_iic_1_0 | 1 | | design_a9_1_axi_quad_spi_0_0 | 1 |
| design_a9_1_axi_iic_0_0 | 1 | | design_a9_1_axi_gpio_1_0 | 1 |
| design_a9_1_axi_gpio_0_0 | 1 | | design_a9_1_axi_gpio_0_0 | 1 |
| design_a9_1_axi_dma_2_0 | 1 |
| design_a9_1_axi_dma_1_1 | 1 |
| design_a9_1_axi_dma_1_0 | 1 | | design_a9_1_axi_dma_1_0 | 1 |
| design_a9_1_axi_dma_0_0 | 1 | | design_a9_1_axi_dma_0_0 | 1 |
| design_a9_1_axi_bram_ctrl_6_0 | 1 |
| design_a9_1_axi_bram_ctrl_5_0 | 1 |
| design_a9_1_axi_bram_ctrl_4_0 | 1 | | design_a9_1_axi_bram_ctrl_4_0 | 1 |
| design_a9_1_axi_bram_ctrl_3_1 | 1 |
| design_a9_1_axi_bram_ctrl_3_0 | 1 | | design_a9_1_axi_bram_ctrl_3_0 | 1 |
| design_a9_1_axi_bram_ctrl_2_0 | 1 | | design_a9_1_axi_bram_ctrl_2_0 | 1 |
| design_a9_1_axi_bram_ctrl_1_0 | 1 | | design_a9_1_axi_bram_ctrl_1_0 | 1 |
| design_a9_1_axi_bram_ctrl_0_0 | 1 | | design_a9_1_axi_bram_ctrl_0_0 | 1 |
| dds_stim_16ch | 1 | | design_a9_1_Z_IO_0 | 1 |
| axis_data_fifo_w8_d128 | 1 | | design_a9_1_ZCHECK_SPI_0 | 1 |
| axis_data_fifo_w32_d16 | 1 | | design_a9_1_STIM_SPI_0 | 1 |
| design_a9_1_CHANN_SEL_0 | 1 |
| design_a9_1_CHANN_EN_2 | 1 |
| design_a9_1_CHANN_EN_1 | 1 |
| design_a9_1_CHANN_EN_0 | 1 |
| dbg_hub | 1 |
+------------------------------------+------+ +------------------------------------+------+
c64_pro.runs/impl_1/debug_nets.ltx
+3333
View File
File diff suppressed because it is too large Load Diff
c64_pro.runs/impl_1/gen_run.xml
+106 -157
View File
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7z010clg400-2" LaunchTime="1722749886"> <GenRun Id="impl_1" LaunchPart="xc7z020clg400-2" LaunchTime="1788506600">
<File Type="ROUTE-PWR" Name="c64pro_top_power_routed.rpt"/> <File Type="ROUTE-PWR" Name="c64pro_top_power_routed.rpt"/>
<File Type="PA-TCL" Name="c64pro_top.tcl"/> <File Type="PA-TCL" Name="c64pro_top.tcl"/>
<File Type="ROUTE-PWR-SUM" Name="c64pro_top_power_summary_routed.pb"/> <File Type="ROUTE-PWR-SUM" Name="c64pro_top_power_summary_routed.pb"/>
@@ -86,13 +86,6 @@
<File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/> <File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/design_a9_1/design_a9_1.bd"> <File Path="$PSRCDIR/sources_1/bd/design_a9_1/design_a9_1.bd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -107,13 +100,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/switch/adg1414_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_arrange.v"> <File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_arrange.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -121,13 +107,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_spi.v"> <File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_spi.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -142,27 +121,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/switch/channel_switch.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/cnv_res_collect.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/utils/debouncing.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v"> <File Path="$PGENDIR/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -177,6 +135,13 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/upload/eeg_emg_upload.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_top.v"> <File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_top.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -191,13 +156,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/emg/emg_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/led_ctrl.v"> <File Path="$PSRCDIR/sources_1/rtl/led_ctrl.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -219,13 +177,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/rhs2116_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/utils/run_time.v"> <File Path="$PSRCDIR/sources_1/rtl/utils/run_time.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -233,83 +184,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/sine_gen.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/utils/spi_full_duplex_master.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/stim_event_collect.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/stim_monitor.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_arrange.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_distribute.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_timer.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/transmit_config.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/transmit_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/trigger/trigger_detection.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/trigger/trigger_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_config.v"> <File Path="$PSRCDIR/sources_1/rtl/upload/upload_config.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -352,6 +226,90 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_mon_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_mon_config.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_ch_map.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_monitor.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/acq_collect.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/ad7689_dual_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/stim_config.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_top1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_spi1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_if1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="c64pro_top"/> <Option Name="TopModule" Val="c64pro_top"/>
@@ -377,25 +335,8 @@
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_misc.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_pm.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_rsh2116.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config> <Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/c64pro_pins_ic.xdc"/>
<Option Name="ConstrsType" Val="XDC"/> <Option Name="ConstrsType" Val="XDC"/>
</Config> </Config>
</FileSet> </FileSet>
@@ -417,10 +358,18 @@
<Step Id="post_route_phys_opt_design"/> <Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/> <Step Id="write_bitstream"/>
</Strategy> </Strategy>
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w32_d32"/> <BlockFileSet Type="BlockSrcs" Name="design_a9_1_CHANN_EN_1"/>
<BlockFileSet Type="BlockSrcs" Name="dds_stim_16ch"/> <BlockFileSet Type="BlockSrcs" Name="fifo_generator_1"/>
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w32_d16"/>
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w8_d128"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axi_gpio_0_0"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_processing_system7_0_0"/> <BlockFileSet Type="BlockSrcs" Name="design_a9_1_processing_system7_0_0"/>
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w8_d128"/>
<BlockFileSet Type="BlockSrcs" Name="fifo_generator_0"/>
<BlockFileSet Type="BlockSrcs" Name="c_add_s16_s32"/>
<BlockFileSet Type="BlockSrcs" Name="vio_cur_flt_state"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_CHANN_EN_2"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_STIM_SPI_0"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_ZCHECK_SPI_0"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axis_data_fifo_1_1"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axis_data_fifo_2_0"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axi_dma_1_1"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axi_dma_2_0"/>
</GenRun> </GenRun>
c64_pro.runs/impl_1/init_design.pb
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c64_pro.runs/impl_1/opt_design.pb
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c64_pro.runs/impl_1/place_design.pb
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c64_pro.runs/impl_1/project.wdf
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@@ -1,30 +1,70 @@
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3530:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3533:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3530:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3533:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3530:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3533:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:36:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:36:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3530:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3533:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3530:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3533:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3530:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3533:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6432353233623139653262643461386238663261323330623032333436393263:506172656e742050412070726f6a656374204944:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6432353233623139653262643461386238663261323330623032333436393263:506172656e742050412070726f6a656374204944:00
eof:2414909475 eof:1170702916
c64_pro.runs/impl_1/route_design.pb
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c64_pro.runs/impl_1/runme.log
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c64_pro.runs/impl_1/runme.sh
+1 -1
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fi fi
export LD_LIBRARY_PATH export LD_LIBRARY_PATH
HD_PWD='D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1' HD_PWD='D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/impl_1'
cd "$HD_PWD" cd "$HD_PWD"
HD_LOG=runme.log HD_LOG=runme.log
c64_pro.runs/impl_1/vivado.jou
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@@ -3,12 +3,12 @@
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023 # SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023 # IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023 # SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Sun Aug 4 13:40:39 2024 # Start of session at: Fri Sep 4 15:27:55 2026
# Process ID: 63460 # Process ID: 20488
# Current directory: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1 # Current directory: D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/impl_1
# Command line: vivado.exe -log c64pro_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source c64pro_top.tcl -notrace # Command line: vivado.exe -log c64pro_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source c64pro_top.tcl -notrace
# Log file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1/c64pro_top.vdi # Log file: D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/impl_1/c64pro_top.vdi
# Journal file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1\vivado.jou # Journal file: D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/impl_1\vivado.jou
# Running On: 840-5CG14025H4, OS: Windows, CPU Frequency: 2803 MHz, CPU Physical cores: 4, Host memory: 34024 MB # Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
#----------------------------------------------------------- #-----------------------------------------------------------
source c64pro_top.tcl -notrace source c64pro_top.tcl -notrace
c64_pro.runs/impl_1/vivado.pb
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c64_pro.runs/impl_1/write_bitstream.pb
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c64_pro.runs/synth_1/.Xil/c64pro_top_propImpl.xdc
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set_property SRC_FILE_INFO {cfile:D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc id:1} [current_design] set_property SRC_FILE_INFO {cfile:D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc id:1} [current_design]
set_property SRC_FILE_INFO {cfile:D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc id:2} [current_design] set_property SRC_FILE_INFO {cfile:D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc id:2} [current_design]
set_property SRC_FILE_INFO {cfile:D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc id:3} [current_design] set_property SRC_FILE_INFO {cfile:D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc id:3} [current_design]
set_property SRC_FILE_INFO {cfile:D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc id:4} [current_design]
set_property SRC_FILE_INFO {cfile:D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc id:5} [current_design]
set_property SRC_FILE_INFO {cfile:D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc id:6} [current_design]
set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN T15 [get_ports {eeg_ads1299_spi_cs[0]}] set_property PACKAGE_PIN P20 [get_ports {eeg_ads1299_spi_cs[0]}]
set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN R19 [get_ports {eeg_ads1299_spi_cs[1]}] set_property PACKAGE_PIN H20 [get_ports {eeg_ads1299_spi_cs[1]}]
set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y18 [get_ports {eeg_ads1299_spi_cs[2]}] set_property PACKAGE_PIN U18 [get_ports {eeg_ads1299_spi_cs[2]}]
set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN W18 [get_ports {eeg_ads1299_spi_cs[3]}] set_property PACKAGE_PIN T19 [get_ports {eeg_ads1299_spi_cs[3]}]
set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN V20 [get_ports {eeg_ads1299_spi_cs[4]}] set_property PACKAGE_PIN Y16 [get_ports {eeg_ads1299_spi_sclk[0]}]
set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN W20 [get_ports {eeg_ads1299_spi_cs[5]}] set_property PACKAGE_PIN U19 [get_ports {eeg_ads1299_spi_sclk[1]}]
set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN R16 [get_ports {eeg_ads1299_spi_cs[6]}] set_property PACKAGE_PIN W16 [get_ports {eeg_ads1299_spi_mosi[0]}]
set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN R17 [get_ports {eeg_ads1299_spi_cs[7]}] set_property PACKAGE_PIN T15 [get_ports {eeg_ads1299_spi_mosi[1]}]
set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN P18 [get_ports {eeg_ads1299_spi_sclk[0]}] set_property PACKAGE_PIN N20 [get_ports {eeg_ads1299_spi_miso[0]}]
set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN V18 [get_ports {eeg_ads1299_spi_sclk[1]}] set_property PACKAGE_PIN U15 [get_ports {eeg_ads1299_spi_miso[1]}]
set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN P20 [get_ports {eeg_ads1299_spi_sclk[2]}] set_property PACKAGE_PIN T20 [get_ports {eeg_ads1299_drdy_n[0]}]
set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN V16 [get_ports {eeg_ads1299_spi_sclk[3]}] set_property PACKAGE_PIN V17 [get_ports {eeg_ads1299_drdy_n[1]}]
set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN T14 [get_ports {eeg_ads1299_spi_mosi[0]}] set_property PACKAGE_PIN Y17 [get_ports {eeg_ads1299_start[0]}]
set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y19 [get_ports {eeg_ads1299_spi_mosi[1]}] set_property PACKAGE_PIN U17 [get_ports {eeg_ads1299_start[1]}]
set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN U20 [get_ports {eeg_ads1299_spi_mosi[2]}]
set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN R18 [get_ports {eeg_ads1299_spi_mosi[3]}]
set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN P19 [get_ports {eeg_ads1299_spi_miso[0]}]
set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN W19 [get_ports {eeg_ads1299_spi_miso[1]}]
set_property src_info {type:XDC file:1 line:81 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN T20 [get_ports {eeg_ads1299_spi_miso[2]}]
set_property src_info {type:XDC file:1 line:86 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN V17 [get_ports {eeg_ads1299_spi_miso[3]}]
set_property src_info {type:XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN N18 [get_ports {eeg_ads1299_drdy_n[0]}]
set_property src_info {type:XDC file:1 line:96 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN T17 [get_ports {eeg_ads1299_drdy_n[1]}]
set_property src_info {type:XDC file:1 line:100 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN N20 [get_ports {eeg_ads1299_drdy_n[2]}]
set_property src_info {type:XDC file:1 line:104 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN W16 [get_ports {eeg_ads1299_drdy_n[3]}]
set_property src_info {type:XDC file:1 line:109 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN T16 [get_ports {eeg_ads1299_start}]
set_property src_info {type:XDC file:2 line:4 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:2 line:4 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN K17 [get_ports {emg_ads1299_spi_cs}] set_property PACKAGE_PIN L20 [get_ports emg_ads1299_spi_cs]
set_property src_info {type:XDC file:2 line:9 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:2 line:9 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN L17 [get_ports {emg_ads1299_spi_sclk}] set_property PACKAGE_PIN L19 [get_ports emg_ads1299_spi_sclk]
set_property src_info {type:XDC file:2 line:14 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:2 line:14 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN K18 [get_ports {emg_ads1299_spi_mosi}] set_property PACKAGE_PIN J20 [get_ports emg_ads1299_spi_mosi]
set_property src_info {type:XDC file:2 line:19 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:2 line:19 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN H16 [get_ports {emg_ads1299_spi_miso}] set_property PACKAGE_PIN M20 [get_ports emg_ads1299_spi_miso]
set_property src_info {type:XDC file:2 line:24 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:2 line:24 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN L16 [get_ports {emg_ads1299_drdy_n}] set_property PACKAGE_PIN M19 [get_ports emg_ads1299_drdy_n]
set_property src_info {type:XDC file:2 line:29 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:2 line:29 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN H17 [get_ports {emg_ads1299_start}] set_property PACKAGE_PIN K19 [get_ports emg_ads1299_start]
set_property src_info {type:XDC file:2 line:34 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:2 line:34 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN H18 [get_ports {emg_ads1299_reset_n}] set_property PACKAGE_PIN J19 [get_ports emg_ads1299_reset_n]
set_property src_info {type:XDC file:2 line:39 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN J18 [get_ports {emg_ads1299_pwdn_n}]
set_property src_info {type:XDC file:3 line:4 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:4 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN B19 [get_ports adg1414_spi_sync] set_property PACKAGE_PIN C20 [get_ports ad7689_cnv]
set_property src_info {type:XDC file:3 line:8 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:8 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN E17 [get_ports adg1414_spi_sclk] set_property PACKAGE_PIN E19 [get_ports ad7689_spi_sclk]
set_property src_info {type:XDC file:3 line:12 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:12 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN A20 [get_ports adg1414_spi_mosi] set_property PACKAGE_PIN D20 [get_ports ad7689_spi_mosi]
set_property src_info {type:XDC file:3 line:16 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:16 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D18 [get_ports adg1414_spi_miso] set_property PACKAGE_PIN F20 [get_ports ad7689_spi_miso]
set_property src_info {type:XDC file:3 line:21 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:21 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN F20 [get_ports accel_spi_cs] set_property PACKAGE_PIN R19 [get_ports rst_ad5941]
set_property src_info {type:XDC file:3 line:25 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:25 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G17 [get_ports accel_spi_sclk] set_property PACKAGE_PIN P19 [get_ports zcheck_spi_cs]
set_property src_info {type:XDC file:3 line:29 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:29 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN J20 [get_ports accel_spi_mosi] set_property PACKAGE_PIN P18 [get_ports zcheck_spi_sclk]
set_property src_info {type:XDC file:3 line:33 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:33 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G18 [get_ports accel_spi_miso] set_property PACKAGE_PIN N18 [get_ports zcheck_spi_mosi]
set_property src_info {type:XDC file:3 line:37 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:37 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN H20 [get_ports accel_int0] set_property PACKAGE_PIN R18 [get_ports zcheck_spi_miso]
set_property src_info {type:XDC file:3 line:41 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:41 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G19 [get_ports accel_int1] set_property PACKAGE_PIN G19 [get_ports z_io]
set_property src_info {type:XDC file:3 line:46 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:54 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN E19 [get_ports z_scl] set_property PACKAGE_PIN U13 [get_ports pudc]
set_property src_info {type:XDC file:3 line:51 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:58 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN F16 [get_ports z_sda] set_property PACKAGE_PIN F19 [get_ports stim_pwr_en]
set_property src_info {type:XDC file:4 line:4 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:62 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN C20 [get_ports led_state] set_property PACKAGE_PIN A20 [get_ports ref_sw_en]
set_property src_info {type:XDC file:4 line:8 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:66 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN B20 [get_ports led_wifi] set_property PACKAGE_PIN B20 [get_ports ref_sw]
set_property src_info {type:XDC file:4 line:12 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:70 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D20 [get_ports led_stim] set_property PACKAGE_PIN R17 [get_ports {elec_mux_in[0]}]
set_property src_info {type:XDC file:4 line:17 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:74 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN K14 [get_ports {trigger_i[0]}] set_property PACKAGE_PIN R16 [get_ports {elec_mux_in[1]}]
set_property src_info {type:XDC file:4 line:21 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:78 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G15 [get_ports {trigger_i[1]}] set_property PACKAGE_PIN R14 [get_ports {elec_mux_in[2]}]
set_property src_info {type:XDC file:4 line:25 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:82 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN N15 [get_ports {trigger_i[2]}] set_property PACKAGE_PIN T16 [get_ports {elec_mux_in[3]}]
set_property src_info {type:XDC file:4 line:29 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:88 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN N16 [get_ports {trigger_o[0]}] set_property PACKAGE_PIN W18 [get_ports {chann_en[0]}]
set_property src_info {type:XDC file:4 line:34 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:92 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN M14 [get_ports {usb_power_check}] set_property PACKAGE_PIN U20 [get_ports {chann_en[1]}]
set_property src_info {type:XDC file:4 line:39 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:104 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G14 [get_ports {led_pl[0]}] set_property PACKAGE_PIN V20 [get_ports {chann_sel[0]}]
set_property src_info {type:XDC file:4 line:43 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:108 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN J15 [get_ports {led_pl[1]}] set_property PACKAGE_PIN V18 [get_ports {chann_sel[1]}]
set_property src_info {type:XDC file:5 line:4 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:112 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN M17 [get_ports gauge_scl] set_property PACKAGE_PIN W19 [get_ports {chann_sel[2]}]
set_property src_info {type:XDC file:5 line:8 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:116 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN M20 [get_ports gauge_sda] set_property PACKAGE_PIN W20 [get_ports {chann_sel[3]}]
set_property src_info {type:XDC file:5 line:12 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:121 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN K16 [get_ports gauge_indicate] set_property PACKAGE_PIN G20 [get_ports rec_pwr_en]
set_property src_info {type:XDC file:5 line:17 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:126 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN U15 [get_ports power_on_rsh2116_a] set_property PACKAGE_PIN P16 [get_ports mux_pwr_en]
set_property src_info {type:XDC file:5 line:21 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:131 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN W15 [get_ports power_on_rsh2116_d] set_property PACKAGE_PIN W15 [get_ports led_rsv]
set_property src_info {type:XDC file:5 line:25 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:135 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN P15 [get_ports power_on_ads1299] set_property PACKAGE_PIN Y18 [get_ports led_usb]
set_property src_info {type:XDC file:5 line:29 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:139 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN L19 [get_ports power_on_z] set_property PACKAGE_PIN Y19 [get_ports led_state]
set_property src_info {type:XDC file:5 line:33 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:143 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D19 [get_ports power_sw_z] set_property PACKAGE_PIN F16 [get_ports led_stim]
set_property src_info {type:XDC file:6 line:4 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:148 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN T19 [get_ports {rsh2116_enable[0]}] set_property PACKAGE_PIN Y8 [get_ports stim_spi_cs]
set_property src_info {type:XDC file:6 line:8 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:152 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y14 [get_ports {rsh2116_enable[1]}] set_property PACKAGE_PIN W9 [get_ports stim_spi_sclk]
set_property src_info {type:XDC file:6 line:12 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:156 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y16 [get_ports {rsh2116_enable[2]}] set_property PACKAGE_PIN W11 [get_ports stim_spi_mosi]
set_property src_info {type:XDC file:6 line:16 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:160 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN T12 [get_ports {rsh2116_enable[3]}] set_property PACKAGE_PIN W8 [get_ports stim_spi_miso]
set_property src_info {type:XDC file:6 line:21 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:164 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN U18 [get_ports {rsh2116_spi_cs[0]}] set_property PACKAGE_PIN Y9 [get_ports stim_clk400k]
set_property src_info {type:XDC file:6 line:25 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:168 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN V13 [get_ports {rsh2116_spi_cs[1]}] set_property PACKAGE_PIN Y11 [get_ports {gpio[0]}]
set_property src_info {type:XDC file:6 line:29 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:172 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN U14 [get_ports {rsh2116_spi_cs[2]}] set_property PACKAGE_PIN Y12 [get_ports {gpio[1]}]
set_property src_info {type:XDC file:6 line:33 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:176 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN T11 [get_ports {rsh2116_spi_cs[3]}] set_property PACKAGE_PIN Y13 [get_ports {gpio[2]}]
set_property src_info {type:XDC file:6 line:38 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:180 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN U19 [get_ports {rsh2116_spi_sclk[0]}] create_debug_core u_ila_0 ila
set_property src_info {type:XDC file:6 line:42 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:181 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN V12 [get_ports {rsh2116_spi_sclk[1]}] set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:6 line:46 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:182 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN V15 [get_ports {rsh2116_spi_sclk[2]}] set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:6 line:50 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:183 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN T10 [get_ports {rsh2116_spi_sclk[3]}] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:6 line:55 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:184 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN U17 [get_ports {rsh2116_spi_mosi[0]}] set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:6 line:59 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:185 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN U12 [get_ports {rsh2116_spi_mosi[1]}] set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:6 line:63 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:186 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN W14 [get_ports {rsh2116_spi_mosi[2]}] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:6 line:67 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:187 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN R14 [get_ports {rsh2116_spi_mosi[3]}] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:6 line:72 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:188 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y17 [get_ports {rsh2116_spi_miso[0]}] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:6 line:76 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:189 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN W13 [get_ports {rsh2116_spi_miso[1]}] set_property port_width 1 [get_debug_ports u_ila_0/clk]
set_property src_info {type:XDC file:6 line:80 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:190 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN U13 [get_ports {rsh2116_spi_miso[2]}] connect_debug_port u_ila_0/clk [get_nets [list u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0]]
set_property src_info {type:XDC file:6 line:84 export:INPUT save:INPUT read:READ} [current_design] set_property src_info {type:XDC file:3 line:191 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN P14 [get_ports {rsh2116_spi_miso[3]}] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property src_info {type:XDC file:3 line:192 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
set_property src_info {type:XDC file:3 line:193 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe0 [get_nets [list {u_pl_top/axis_eeg24_tdata[0]} {u_pl_top/axis_eeg24_tdata[1]} {u_pl_top/axis_eeg24_tdata[2]} {u_pl_top/axis_eeg24_tdata[3]} {u_pl_top/axis_eeg24_tdata[4]} {u_pl_top/axis_eeg24_tdata[5]} {u_pl_top/axis_eeg24_tdata[6]} {u_pl_top/axis_eeg24_tdata[7]} {u_pl_top/axis_eeg24_tdata[8]} {u_pl_top/axis_eeg24_tdata[9]} {u_pl_top/axis_eeg24_tdata[10]} {u_pl_top/axis_eeg24_tdata[11]} {u_pl_top/axis_eeg24_tdata[12]} {u_pl_top/axis_eeg24_tdata[13]} {u_pl_top/axis_eeg24_tdata[14]} {u_pl_top/axis_eeg24_tdata[15]} {u_pl_top/axis_eeg24_tdata[16]} {u_pl_top/axis_eeg24_tdata[17]} {u_pl_top/axis_eeg24_tdata[18]} {u_pl_top/axis_eeg24_tdata[19]} {u_pl_top/axis_eeg24_tdata[20]} {u_pl_top/axis_eeg24_tdata[21]} {u_pl_top/axis_eeg24_tdata[22]} {u_pl_top/axis_eeg24_tdata[23]} {u_pl_top/axis_eeg24_tdata[24]} {u_pl_top/axis_eeg24_tdata[25]} {u_pl_top/axis_eeg24_tdata[26]} {u_pl_top/axis_eeg24_tdata[27]} {u_pl_top/axis_eeg24_tdata[28]} {u_pl_top/axis_eeg24_tdata[29]} {u_pl_top/axis_eeg24_tdata[30]} {u_pl_top/axis_eeg24_tdata[31]}]]
set_property src_info {type:XDC file:3 line:194 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:195 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property src_info {type:XDC file:3 line:196 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
set_property src_info {type:XDC file:3 line:197 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe1 [get_nets [list {u_pl_top/axis_emg_tdata[0]} {u_pl_top/axis_emg_tdata[1]} {u_pl_top/axis_emg_tdata[2]} {u_pl_top/axis_emg_tdata[3]} {u_pl_top/axis_emg_tdata[4]} {u_pl_top/axis_emg_tdata[5]} {u_pl_top/axis_emg_tdata[6]} {u_pl_top/axis_emg_tdata[7]} {u_pl_top/axis_emg_tdata[8]} {u_pl_top/axis_emg_tdata[9]} {u_pl_top/axis_emg_tdata[10]} {u_pl_top/axis_emg_tdata[11]} {u_pl_top/axis_emg_tdata[12]} {u_pl_top/axis_emg_tdata[13]} {u_pl_top/axis_emg_tdata[14]} {u_pl_top/axis_emg_tdata[15]} {u_pl_top/axis_emg_tdata[16]} {u_pl_top/axis_emg_tdata[17]} {u_pl_top/axis_emg_tdata[18]} {u_pl_top/axis_emg_tdata[19]} {u_pl_top/axis_emg_tdata[20]} {u_pl_top/axis_emg_tdata[21]} {u_pl_top/axis_emg_tdata[22]} {u_pl_top/axis_emg_tdata[23]} {u_pl_top/axis_emg_tdata[24]} {u_pl_top/axis_emg_tdata[25]} {u_pl_top/axis_emg_tdata[26]} {u_pl_top/axis_emg_tdata[27]} {u_pl_top/axis_emg_tdata[28]} {u_pl_top/axis_emg_tdata[29]} {u_pl_top/axis_emg_tdata[30]} {u_pl_top/axis_emg_tdata[31]}]]
set_property src_info {type:XDC file:3 line:198 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:199 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property src_info {type:XDC file:3 line:200 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 32 [get_debug_ports u_ila_0/probe2]
set_property src_info {type:XDC file:3 line:201 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe2 [get_nets [list {u_pl_top/axis_emg_tdata_tmp[0]} {u_pl_top/axis_emg_tdata_tmp[1]} {u_pl_top/axis_emg_tdata_tmp[2]} {u_pl_top/axis_emg_tdata_tmp[3]} {u_pl_top/axis_emg_tdata_tmp[4]} {u_pl_top/axis_emg_tdata_tmp[5]} {u_pl_top/axis_emg_tdata_tmp[6]} {u_pl_top/axis_emg_tdata_tmp[7]} {u_pl_top/axis_emg_tdata_tmp[8]} {u_pl_top/axis_emg_tdata_tmp[9]} {u_pl_top/axis_emg_tdata_tmp[10]} {u_pl_top/axis_emg_tdata_tmp[11]} {u_pl_top/axis_emg_tdata_tmp[12]} {u_pl_top/axis_emg_tdata_tmp[13]} {u_pl_top/axis_emg_tdata_tmp[14]} {u_pl_top/axis_emg_tdata_tmp[15]} {u_pl_top/axis_emg_tdata_tmp[16]} {u_pl_top/axis_emg_tdata_tmp[17]} {u_pl_top/axis_emg_tdata_tmp[18]} {u_pl_top/axis_emg_tdata_tmp[19]} {u_pl_top/axis_emg_tdata_tmp[20]} {u_pl_top/axis_emg_tdata_tmp[21]} {u_pl_top/axis_emg_tdata_tmp[22]} {u_pl_top/axis_emg_tdata_tmp[23]} {u_pl_top/axis_emg_tdata_tmp[24]} {u_pl_top/axis_emg_tdata_tmp[25]} {u_pl_top/axis_emg_tdata_tmp[26]} {u_pl_top/axis_emg_tdata_tmp[27]} {u_pl_top/axis_emg_tdata_tmp[28]} {u_pl_top/axis_emg_tdata_tmp[29]} {u_pl_top/axis_emg_tdata_tmp[30]} {u_pl_top/axis_emg_tdata_tmp[31]}]]
set_property src_info {type:XDC file:3 line:202 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:203 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property src_info {type:XDC file:3 line:204 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 2 [get_debug_ports u_ila_0/probe3]
set_property src_info {type:XDC file:3 line:205 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe3 [get_nets [list {u_pl_top/eeg_emg_sel[0]} {u_pl_top/eeg_emg_sel[1]}]]
set_property src_info {type:XDC file:3 line:206 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:207 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property src_info {type:XDC file:3 line:208 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 16 [get_debug_ports u_ila_0/probe4]
set_property src_info {type:XDC file:3 line:209 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe4 [get_nets [list {u_pl_top/eeg_send_package_num[0]} {u_pl_top/eeg_send_package_num[1]} {u_pl_top/eeg_send_package_num[2]} {u_pl_top/eeg_send_package_num[3]} {u_pl_top/eeg_send_package_num[4]} {u_pl_top/eeg_send_package_num[5]} {u_pl_top/eeg_send_package_num[6]} {u_pl_top/eeg_send_package_num[7]} {u_pl_top/eeg_send_package_num[8]} {u_pl_top/eeg_send_package_num[9]} {u_pl_top/eeg_send_package_num[10]} {u_pl_top/eeg_send_package_num[11]} {u_pl_top/eeg_send_package_num[12]} {u_pl_top/eeg_send_package_num[13]} {u_pl_top/eeg_send_package_num[14]} {u_pl_top/eeg_send_package_num[15]}]]
set_property src_info {type:XDC file:3 line:210 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:211 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property src_info {type:XDC file:3 line:212 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 16 [get_debug_ports u_ila_0/probe5]
set_property src_info {type:XDC file:3 line:213 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe5 [get_nets [list {u_pl_top/emg_send_package_num[0]} {u_pl_top/emg_send_package_num[1]} {u_pl_top/emg_send_package_num[2]} {u_pl_top/emg_send_package_num[3]} {u_pl_top/emg_send_package_num[4]} {u_pl_top/emg_send_package_num[5]} {u_pl_top/emg_send_package_num[6]} {u_pl_top/emg_send_package_num[7]} {u_pl_top/emg_send_package_num[8]} {u_pl_top/emg_send_package_num[9]} {u_pl_top/emg_send_package_num[10]} {u_pl_top/emg_send_package_num[11]} {u_pl_top/emg_send_package_num[12]} {u_pl_top/emg_send_package_num[13]} {u_pl_top/emg_send_package_num[14]} {u_pl_top/emg_send_package_num[15]}]]
set_property src_info {type:XDC file:3 line:214 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:215 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property src_info {type:XDC file:3 line:216 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 8 [get_debug_ports u_ila_0/probe6]
set_property src_info {type:XDC file:3 line:217 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe6 [get_nets [list {u_pl_top/m_axis_eeg_tdata[0]} {u_pl_top/m_axis_eeg_tdata[1]} {u_pl_top/m_axis_eeg_tdata[2]} {u_pl_top/m_axis_eeg_tdata[3]} {u_pl_top/m_axis_eeg_tdata[4]} {u_pl_top/m_axis_eeg_tdata[5]} {u_pl_top/m_axis_eeg_tdata[6]} {u_pl_top/m_axis_eeg_tdata[7]}]]
set_property src_info {type:XDC file:3 line:218 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:219 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property src_info {type:XDC file:3 line:220 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 16 [get_debug_ports u_ila_0/probe7]
set_property src_info {type:XDC file:3 line:221 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe7 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16[0]} {u_pl_top/u_eeg_emg_upload/crc16[1]} {u_pl_top/u_eeg_emg_upload/crc16[2]} {u_pl_top/u_eeg_emg_upload/crc16[3]} {u_pl_top/u_eeg_emg_upload/crc16[4]} {u_pl_top/u_eeg_emg_upload/crc16[5]} {u_pl_top/u_eeg_emg_upload/crc16[6]} {u_pl_top/u_eeg_emg_upload/crc16[7]} {u_pl_top/u_eeg_emg_upload/crc16[8]} {u_pl_top/u_eeg_emg_upload/crc16[9]} {u_pl_top/u_eeg_emg_upload/crc16[10]} {u_pl_top/u_eeg_emg_upload/crc16[11]} {u_pl_top/u_eeg_emg_upload/crc16[12]} {u_pl_top/u_eeg_emg_upload/crc16[13]} {u_pl_top/u_eeg_emg_upload/crc16[14]} {u_pl_top/u_eeg_emg_upload/crc16[15]}]]
set_property src_info {type:XDC file:3 line:222 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:223 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property src_info {type:XDC file:3 line:224 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 16 [get_debug_ports u_ila_0/probe8]
set_property src_info {type:XDC file:3 line:225 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe8 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[0]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[1]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[2]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[3]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[4]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[5]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[6]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[7]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[8]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[9]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[10]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[11]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[12]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[13]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[14]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[15]}]]
set_property src_info {type:XDC file:3 line:226 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:227 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property src_info {type:XDC file:3 line:228 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 2 [get_debug_ports u_ila_0/probe9]
set_property src_info {type:XDC file:3 line:229 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe9 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[1]}]]
set_property src_info {type:XDC file:3 line:230 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:231 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property src_info {type:XDC file:3 line:232 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 9 [get_debug_ports u_ila_0/probe10]
set_property src_info {type:XDC file:3 line:233 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe10 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[7]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[8]}]]
set_property src_info {type:XDC file:3 line:234 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:235 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property src_info {type:XDC file:3 line:236 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 8 [get_debug_ports u_ila_0/probe11]
set_property src_info {type:XDC file:3 line:237 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe11 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[7]}]]
set_property src_info {type:XDC file:3 line:238 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:239 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property src_info {type:XDC file:3 line:240 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 8 [get_debug_ports u_ila_0/probe12]
set_property src_info {type:XDC file:3 line:241 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe12 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[7]}]]
set_property src_info {type:XDC file:3 line:242 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:243 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property src_info {type:XDC file:3 line:244 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 16 [get_debug_ports u_ila_0/probe13]
set_property src_info {type:XDC file:3 line:245 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe13 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16_out[0]} {u_pl_top/u_eeg_emg_upload/crc16_out[1]} {u_pl_top/u_eeg_emg_upload/crc16_out[2]} {u_pl_top/u_eeg_emg_upload/crc16_out[3]} {u_pl_top/u_eeg_emg_upload/crc16_out[4]} {u_pl_top/u_eeg_emg_upload/crc16_out[5]} {u_pl_top/u_eeg_emg_upload/crc16_out[6]} {u_pl_top/u_eeg_emg_upload/crc16_out[7]} {u_pl_top/u_eeg_emg_upload/crc16_out[8]} {u_pl_top/u_eeg_emg_upload/crc16_out[9]} {u_pl_top/u_eeg_emg_upload/crc16_out[10]} {u_pl_top/u_eeg_emg_upload/crc16_out[11]} {u_pl_top/u_eeg_emg_upload/crc16_out[12]} {u_pl_top/u_eeg_emg_upload/crc16_out[13]} {u_pl_top/u_eeg_emg_upload/crc16_out[14]} {u_pl_top/u_eeg_emg_upload/crc16_out[15]}]]
set_property src_info {type:XDC file:3 line:246 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:247 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property src_info {type:XDC file:3 line:248 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 8 [get_debug_ports u_ila_0/probe14]
set_property src_info {type:XDC file:3 line:249 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe14 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[7]}]]
set_property src_info {type:XDC file:3 line:250 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:251 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property src_info {type:XDC file:3 line:252 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 16 [get_debug_ports u_ila_0/probe15]
set_property src_info {type:XDC file:3 line:253 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe15 [get_nets [list {u_pl_top/u_eeg_emg_upload/emg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[15]}]]
set_property src_info {type:XDC file:3 line:254 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:255 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property src_info {type:XDC file:3 line:256 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 16 [get_debug_ports u_ila_0/probe16]
set_property src_info {type:XDC file:3 line:257 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe16 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[8]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[9]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[10]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[11]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[12]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[13]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[14]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[15]}]]
set_property src_info {type:XDC file:3 line:258 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:259 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property src_info {type:XDC file:3 line:260 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 9 [get_debug_ports u_ila_0/probe17]
set_property src_info {type:XDC file:3 line:261 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe17 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_data[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[8]}]]
set_property src_info {type:XDC file:3 line:262 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:263 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property src_info {type:XDC file:3 line:264 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 8 [get_debug_ports u_ila_0/probe18]
set_property src_info {type:XDC file:3 line:265 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe18 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[0][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][7]}]]
set_property src_info {type:XDC file:3 line:266 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:267 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property src_info {type:XDC file:3 line:268 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 8 [get_debug_ports u_ila_0/probe19]
set_property src_info {type:XDC file:3 line:269 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe19 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[1][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][7]}]]
set_property src_info {type:XDC file:3 line:270 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:271 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property src_info {type:XDC file:3 line:272 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 8 [get_debug_ports u_ila_0/probe20]
set_property src_info {type:XDC file:3 line:273 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe20 [get_nets [list {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[0]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[1]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[2]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[3]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[4]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[5]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[6]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[7]}]]
set_property src_info {type:XDC file:3 line:274 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:275 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property src_info {type:XDC file:3 line:276 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 8 [get_debug_ports u_ila_0/probe21]
set_property src_info {type:XDC file:3 line:277 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe21 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[7]}]]
set_property src_info {type:XDC file:3 line:278 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:279 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property src_info {type:XDC file:3 line:280 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 16 [get_debug_ports u_ila_0/probe22]
set_property src_info {type:XDC file:3 line:281 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe22 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[15]}]]
set_property src_info {type:XDC file:3 line:282 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:283 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
set_property src_info {type:XDC file:3 line:284 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 13 [get_debug_ports u_ila_0/probe23]
set_property src_info {type:XDC file:3 line:285 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe23 [get_nets [list {u_pl_top/u_stim_config/bram_addr[0]} {u_pl_top/u_stim_config/bram_addr[1]} {u_pl_top/u_stim_config/bram_addr[2]} {u_pl_top/u_stim_config/bram_addr[3]} {u_pl_top/u_stim_config/bram_addr[4]} {u_pl_top/u_stim_config/bram_addr[5]} {u_pl_top/u_stim_config/bram_addr[6]} {u_pl_top/u_stim_config/bram_addr[7]} {u_pl_top/u_stim_config/bram_addr[8]} {u_pl_top/u_stim_config/bram_addr[9]} {u_pl_top/u_stim_config/bram_addr[10]} {u_pl_top/u_stim_config/bram_addr[11]} {u_pl_top/u_stim_config/bram_addr[12]}]]
set_property src_info {type:XDC file:3 line:286 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:287 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
set_property src_info {type:XDC file:3 line:288 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 4 [get_debug_ports u_ila_0/probe24]
set_property src_info {type:XDC file:3 line:289 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe24 [get_nets [list {u_pl_top/u_stim_config/bram_we[0]} {u_pl_top/u_stim_config/bram_we[1]} {u_pl_top/u_stim_config/bram_we[2]} {u_pl_top/u_stim_config/bram_we[3]}]]
set_property src_info {type:XDC file:3 line:290 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:291 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
set_property src_info {type:XDC file:3 line:292 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 32 [get_debug_ports u_ila_0/probe25]
set_property src_info {type:XDC file:3 line:293 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe25 [get_nets [list {u_pl_top/u_stim_config/bram_din[0]} {u_pl_top/u_stim_config/bram_din[1]} {u_pl_top/u_stim_config/bram_din[2]} {u_pl_top/u_stim_config/bram_din[3]} {u_pl_top/u_stim_config/bram_din[4]} {u_pl_top/u_stim_config/bram_din[5]} {u_pl_top/u_stim_config/bram_din[6]} {u_pl_top/u_stim_config/bram_din[7]} {u_pl_top/u_stim_config/bram_din[8]} {u_pl_top/u_stim_config/bram_din[9]} {u_pl_top/u_stim_config/bram_din[10]} {u_pl_top/u_stim_config/bram_din[11]} {u_pl_top/u_stim_config/bram_din[12]} {u_pl_top/u_stim_config/bram_din[13]} {u_pl_top/u_stim_config/bram_din[14]} {u_pl_top/u_stim_config/bram_din[15]} {u_pl_top/u_stim_config/bram_din[16]} {u_pl_top/u_stim_config/bram_din[17]} {u_pl_top/u_stim_config/bram_din[18]} {u_pl_top/u_stim_config/bram_din[19]} {u_pl_top/u_stim_config/bram_din[20]} {u_pl_top/u_stim_config/bram_din[21]} {u_pl_top/u_stim_config/bram_din[22]} {u_pl_top/u_stim_config/bram_din[23]} {u_pl_top/u_stim_config/bram_din[24]} {u_pl_top/u_stim_config/bram_din[25]} {u_pl_top/u_stim_config/bram_din[26]} {u_pl_top/u_stim_config/bram_din[27]} {u_pl_top/u_stim_config/bram_din[28]} {u_pl_top/u_stim_config/bram_din[29]} {u_pl_top/u_stim_config/bram_din[30]} {u_pl_top/u_stim_config/bram_din[31]}]]
set_property src_info {type:XDC file:3 line:294 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:295 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
set_property src_info {type:XDC file:3 line:296 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 8 [get_debug_ports u_ila_0/probe26]
set_property src_info {type:XDC file:3 line:297 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe26 [get_nets [list {u_pl_top/m_axis_emg_tdata[0]} {u_pl_top/m_axis_emg_tdata[1]} {u_pl_top/m_axis_emg_tdata[2]} {u_pl_top/m_axis_emg_tdata[3]} {u_pl_top/m_axis_emg_tdata[4]} {u_pl_top/m_axis_emg_tdata[5]} {u_pl_top/m_axis_emg_tdata[6]} {u_pl_top/m_axis_emg_tdata[7]}]]
set_property src_info {type:XDC file:3 line:298 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:299 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
set_property src_info {type:XDC file:3 line:300 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
set_property src_info {type:XDC file:3 line:301 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe27 [get_nets [list {u_pl_top/m_axis_record_tkeep[0]}]]
set_property src_info {type:XDC file:3 line:302 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:303 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
set_property src_info {type:XDC file:3 line:304 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 8 [get_debug_ports u_ila_0/probe28]
set_property src_info {type:XDC file:3 line:305 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe28 [get_nets [list {u_pl_top/m_axis_record_tdata[0]} {u_pl_top/m_axis_record_tdata[1]} {u_pl_top/m_axis_record_tdata[2]} {u_pl_top/m_axis_record_tdata[3]} {u_pl_top/m_axis_record_tdata[4]} {u_pl_top/m_axis_record_tdata[5]} {u_pl_top/m_axis_record_tdata[6]} {u_pl_top/m_axis_record_tdata[7]}]]
set_property src_info {type:XDC file:3 line:306 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:307 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
set_property src_info {type:XDC file:3 line:308 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
set_property src_info {type:XDC file:3 line:309 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe29 [get_nets [list u_pl_top/axis_eeg24_tlast]]
set_property src_info {type:XDC file:3 line:310 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:311 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
set_property src_info {type:XDC file:3 line:312 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
set_property src_info {type:XDC file:3 line:313 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe30 [get_nets [list u_pl_top/axis_eeg24_tvalid]]
set_property src_info {type:XDC file:3 line:314 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:315 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
set_property src_info {type:XDC file:3 line:316 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
set_property src_info {type:XDC file:3 line:317 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe31 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp]]
set_property src_info {type:XDC file:3 line:318 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:319 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
set_property src_info {type:XDC file:3 line:320 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
set_property src_info {type:XDC file:3 line:321 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe32 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp]]
set_property src_info {type:XDC file:3 line:322 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:323 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
set_property src_info {type:XDC file:3 line:324 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
set_property src_info {type:XDC file:3 line:325 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe33 [get_nets [list u_pl_top/axis_emg_tlast]]
set_property src_info {type:XDC file:3 line:326 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:327 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
set_property src_info {type:XDC file:3 line:328 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
set_property src_info {type:XDC file:3 line:329 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe34 [get_nets [list u_pl_top/axis_emg_tlast_tmp]]
set_property src_info {type:XDC file:3 line:330 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:331 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
set_property src_info {type:XDC file:3 line:332 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
set_property src_info {type:XDC file:3 line:333 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe35 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp]]
set_property src_info {type:XDC file:3 line:334 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:335 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
set_property src_info {type:XDC file:3 line:336 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
set_property src_info {type:XDC file:3 line:337 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe36 [get_nets [list u_pl_top/axis_emg_tvalid]]
set_property src_info {type:XDC file:3 line:338 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:339 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
set_property src_info {type:XDC file:3 line:340 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
set_property src_info {type:XDC file:3 line:341 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe37 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp]]
set_property src_info {type:XDC file:3 line:342 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:343 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
set_property src_info {type:XDC file:3 line:344 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
set_property src_info {type:XDC file:3 line:345 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe38 [get_nets [list u_pl_top/axis_emg_tvalid_tmp]]
set_property src_info {type:XDC file:3 line:346 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:347 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
set_property src_info {type:XDC file:3 line:348 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
set_property src_info {type:XDC file:3 line:349 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe39 [get_nets [list u_pl_top/u_stim_config/bram_en]]
set_property src_info {type:XDC file:3 line:350 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:351 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
set_property src_info {type:XDC file:3 line:352 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
set_property src_info {type:XDC file:3 line:353 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe40 [get_nets [list u_pl_top/u_stim_config/bram_rd_valid]]
set_property src_info {type:XDC file:3 line:354 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:355 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
set_property src_info {type:XDC file:3 line:356 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
set_property src_info {type:XDC file:3 line:357 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe41 [get_nets [list u_pl_top/u_stim_config/bram_wr_valid]]
set_property src_info {type:XDC file:3 line:358 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:359 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
set_property src_info {type:XDC file:3 line:360 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
set_property src_info {type:XDC file:3 line:361 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe42 [get_nets [list u_pl_top/u_eeg_emg_upload/crc_vld]]
set_property src_info {type:XDC file:3 line:362 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:363 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
set_property src_info {type:XDC file:3 line:364 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
set_property src_info {type:XDC file:3 line:365 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe43 [get_nets [list u_pl_top/u_stim_config/diff_pkt_data_sel]]
set_property src_info {type:XDC file:3 line:366 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:367 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
set_property src_info {type:XDC file:3 line:368 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
set_property src_info {type:XDC file:3 line:369 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe44 [get_nets [list u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel]]
set_property src_info {type:XDC file:3 line:370 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:371 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
set_property src_info {type:XDC file:3 line:372 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
set_property src_info {type:XDC file:3 line:373 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe45 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast]]
set_property src_info {type:XDC file:3 line:374 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:375 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
set_property src_info {type:XDC file:3 line:376 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
set_property src_info {type:XDC file:3 line:377 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe46 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp]]
set_property src_info {type:XDC file:3 line:378 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:379 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
set_property src_info {type:XDC file:3 line:380 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
set_property src_info {type:XDC file:3 line:381 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe47 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid]]
set_property src_info {type:XDC file:3 line:382 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:383 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
set_property src_info {type:XDC file:3 line:384 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
set_property src_info {type:XDC file:3 line:385 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe48 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp]]
set_property src_info {type:XDC file:3 line:386 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:387 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
set_property src_info {type:XDC file:3 line:388 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
set_property src_info {type:XDC file:3 line:389 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe49 [get_nets [list u_pl_top/emg_ads1299_spi_cs]]
set_property src_info {type:XDC file:3 line:390 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:391 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
set_property src_info {type:XDC file:3 line:392 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
set_property src_info {type:XDC file:3 line:393 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe50 [get_nets [list u_pl_top/emg_ads1299_spi_miso]]
set_property src_info {type:XDC file:3 line:394 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:395 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
set_property src_info {type:XDC file:3 line:396 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
set_property src_info {type:XDC file:3 line:397 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe51 [get_nets [list u_pl_top/emg_ads1299_spi_mosi]]
set_property src_info {type:XDC file:3 line:398 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:399 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
set_property src_info {type:XDC file:3 line:400 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
set_property src_info {type:XDC file:3 line:401 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe52 [get_nets [list u_pl_top/emg_ads1299_spi_sclk]]
set_property src_info {type:XDC file:3 line:402 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:403 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
set_property src_info {type:XDC file:3 line:404 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
set_property src_info {type:XDC file:3 line:405 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe53 [get_nets [list u_pl_top/emg_ads1299_spi_sclk_tmp]]
set_property src_info {type:XDC file:3 line:406 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:407 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
set_property src_info {type:XDC file:3 line:408 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
set_property src_info {type:XDC file:3 line:409 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe54 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en]]
set_property src_info {type:XDC file:3 line:410 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:411 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
set_property src_info {type:XDC file:3 line:412 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
set_property src_info {type:XDC file:3 line:413 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe55 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly]]
set_property src_info {type:XDC file:3 line:414 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:415 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
set_property src_info {type:XDC file:3 line:416 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
set_property src_info {type:XDC file:3 line:417 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe56 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_rst]]
set_property src_info {type:XDC file:3 line:418 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:419 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
set_property src_info {type:XDC file:3 line:420 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
set_property src_info {type:XDC file:3 line:421 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe57 [get_nets [list u_pl_top/in004_out]]
set_property src_info {type:XDC file:3 line:422 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:423 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
set_property src_info {type:XDC file:3 line:424 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
set_property src_info {type:XDC file:3 line:425 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe58 [get_nets [list u_pl_top/m_axis_eeg_tlast]]
set_property src_info {type:XDC file:3 line:426 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:427 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
set_property src_info {type:XDC file:3 line:428 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
set_property src_info {type:XDC file:3 line:429 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe59 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast]]
set_property src_info {type:XDC file:3 line:430 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:431 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
set_property src_info {type:XDC file:3 line:432 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
set_property src_info {type:XDC file:3 line:433 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe60 [get_nets [list u_pl_top/m_axis_eeg_tvalid]]
set_property src_info {type:XDC file:3 line:434 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:435 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
set_property src_info {type:XDC file:3 line:436 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
set_property src_info {type:XDC file:3 line:437 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe61 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid]]
set_property src_info {type:XDC file:3 line:438 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:439 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
set_property src_info {type:XDC file:3 line:440 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
set_property src_info {type:XDC file:3 line:441 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe62 [get_nets [list u_pl_top/m_axis_emg_tlast]]
set_property src_info {type:XDC file:3 line:442 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:443 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
set_property src_info {type:XDC file:3 line:444 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
set_property src_info {type:XDC file:3 line:445 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe63 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid]]
set_property src_info {type:XDC file:3 line:446 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:447 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
set_property src_info {type:XDC file:3 line:448 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
set_property src_info {type:XDC file:3 line:449 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe64 [get_nets [list u_pl_top/m_axis_emg_tvalid]]
set_property src_info {type:XDC file:3 line:450 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:451 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
set_property src_info {type:XDC file:3 line:452 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe65]
set_property src_info {type:XDC file:3 line:453 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe65 [get_nets [list u_pl_top/m_axis_record_tfull]]
set_property src_info {type:XDC file:3 line:454 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:455 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
set_property src_info {type:XDC file:3 line:456 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe66]
set_property src_info {type:XDC file:3 line:457 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe66 [get_nets [list u_pl_top/m_axis_record_tlast]]
set_property src_info {type:XDC file:3 line:458 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:459 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
set_property src_info {type:XDC file:3 line:460 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe67]
set_property src_info {type:XDC file:3 line:461 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe67 [get_nets [list u_pl_top/m_axis_record_tready]]
set_property src_info {type:XDC file:3 line:462 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:463 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
set_property src_info {type:XDC file:3 line:464 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe68]
set_property src_info {type:XDC file:3 line:465 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe68 [get_nets [list u_pl_top/m_axis_record_tvalid]]
set_property src_info {type:XDC file:3 line:466 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:467 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
set_property src_info {type:XDC file:3 line:468 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe69]
set_property src_info {type:XDC file:3 line:469 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe69 [get_nets [list mux_pwr_en_OBUF]]
set_property src_info {type:XDC file:3 line:470 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:3 line:471 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
set_property src_info {type:XDC file:3 line:472 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe70]
set_property src_info {type:XDC file:3 line:473 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe70 [get_nets [list u_pl_top/stop_sample]]
set_property src_info {type:XDC file:3 line:474 export:INPUT save:INPUT read:READ} [current_design]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property src_info {type:XDC file:3 line:475 export:INPUT save:INPUT read:READ} [current_design]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property src_info {type:XDC file:3 line:476 export:INPUT save:INPUT read:READ} [current_design]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
set_property src_info {type:XDC file:3 line:477 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port dbg_hub/clk [get_nets clk]
c64_pro.runs/synth_1/.vivado.begin.rst
+1 -1
View File
@@ -1,5 +1,5 @@
<?xml version="1.0"?> <?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0"> <ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="wenlibin" Host="840-5CG14025H4" Pid="55560" HostCore="8" HostMemory="034024464384"> <Process Command="vivado.bat" Owner="lixiangfu" Host="DESKTOP-VN054CM" Pid="44992" HostCore="20" HostMemory="0171579695104">
</Process> </Process>
</ProcessHandle> </ProcessHandle>
c64_pro.runs/synth_1/c64pro_top.dcp
BIN
View File
Binary file not shown.
c64_pro.runs/synth_1/c64pro_top.tcl
+376 -198
View File
@@ -4,7 +4,7 @@
set TIME_start [clock seconds] set TIME_start [clock seconds]
namespace eval ::optrace { namespace eval ::optrace {
variable script "D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/c64pro_top.tcl" variable script "D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/c64pro_top.tcl"
variable category "vivado_synth" variable category "vivado_synth"
} }
@@ -71,205 +71,392 @@ proc create_report { reportName command } {
} }
OPTRACE "synth_1" START { ROLLUP_AUTO } OPTRACE "synth_1" START { ROLLUP_AUTO }
OPTRACE "Creating in-memory project" START { } OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7z010clg400-2 create_project -in_memory -part xc7z020clg400-2
set_param project.singleFileAddWarning.threshold 0 set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0 set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir D:/projects/vivadoPrj/c64_pro/c64_pro.cache/wt [current_project] set_property webtalk.parent_dir D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.cache/wt [current_project]
set_property parent.project_path D:/projects/vivadoPrj/c64_pro/c64_pro.xpr [current_project] set_property parent.project_path D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.xpr [current_project]
set_property XPM_LIBRARIES {XPM_CDC XPM_FIFO XPM_MEMORY} [current_project] set_property XPM_LIBRARIES {XPM_CDC XPM_FIFO XPM_MEMORY} [current_project]
set_property default_lib xil_defaultlib [current_project] set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project] set_property target_language Verilog [current_project]
set_property ip_output_repo d:/projects/vivadoPrj/c64_pro/c64_pro.cache/ip [current_project] set_property ip_output_repo d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project] set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { } OPTRACE "Creating in-memory project" END { }
OPTRACE "Adding files" START { } OPTRACE "Adding files" START { }
read_verilog -library xil_defaultlib { read_verilog -library xil_defaultlib {
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/accel/accel_top.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/accel/accel_top.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/switch/adg1414_if.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/switch/channel_switch.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/debouncing.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v
D:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/led_ctrl.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/utils/run_time.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/emg/emg_top.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_config.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/led_ctrl.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_top.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/run_time.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/stim_event_collect.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/stim_monitor.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/trans_arrange.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/trans_distribute.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/stim_config.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_if.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/trigger/trigger_detection.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi1.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/trigger/trigger_top.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_config.v D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if1.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/c64pro_top.v
} }
read_ip -quiet D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8.xci add_files D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/bd/design_a9_1/design_a9_1.bd
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8_ooc.xdc] set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_2/bd_6e35_arinsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_3/bd_6e35_rinsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_4/bd_6e35_awinsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_5/bd_6e35_winsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_6/bd_6e35_binsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_7/bd_6e35_arni_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_8/bd_6e35_rni_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_9/bd_6e35_awni_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_10/bd_6e35_wni_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_11/bd_6e35_bni_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_12/bd_6e35_arni_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_13/bd_6e35_rni_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_14/bd_6e35_awni_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_15/bd_6e35_wni_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_16/bd_6e35_bni_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_17/bd_6e35_arni_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_18/bd_6e35_rni_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_19/bd_6e35_awni_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_20/bd_6e35_wni_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_21/bd_6e35_bni_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_22/bd_6e35_arni_3_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_23/bd_6e35_rni_3_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_24/bd_6e35_awni_3_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_25/bd_6e35_wni_3_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_26/bd_6e35_bni_3_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_27/bd_6e35_arni_4_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_28/bd_6e35_rni_4_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_29/bd_6e35_awni_4_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_30/bd_6e35_wni_4_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_31/bd_6e35_bni_4_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_32/bd_6e35_arni_5_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_33/bd_6e35_rni_5_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_34/bd_6e35_awni_5_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_35/bd_6e35_wni_5_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_36/bd_6e35_bni_5_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_37/bd_6e35_arni_6_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_38/bd_6e35_rni_6_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_39/bd_6e35_awni_6_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_40/bd_6e35_wni_6_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_41/bd_6e35_bni_6_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_42/bd_6e35_arni_7_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_43/bd_6e35_rni_7_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_44/bd_6e35_awni_7_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_45/bd_6e35_wni_7_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_46/bd_6e35_bni_7_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_47/bd_6e35_arinsw_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_48/bd_6e35_rinsw_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_49/bd_6e35_awinsw_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_50/bd_6e35_winsw_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_51/bd_6e35_binsw_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_52/bd_6e35_arinsw_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_53/bd_6e35_rinsw_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_54/bd_6e35_awinsw_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_55/bd_6e35_winsw_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_56/bd_6e35_binsw_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_57/bd_6e35_arinsw_3_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_58/bd_6e35_rinsw_3_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_59/bd_6e35_awinsw_3_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_60/bd_6e35_winsw_3_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_61/bd_6e35_binsw_3_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_62/bd_6e35_arinsw_4_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_63/bd_6e35_rinsw_4_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_64/bd_6e35_awinsw_4_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_65/bd_6e35_winsw_4_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_66/bd_6e35_binsw_4_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_67/bd_6e35_arinsw_5_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_68/bd_6e35_rinsw_5_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_69/bd_6e35_awinsw_5_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_70/bd_6e35_winsw_5_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_71/bd_6e35_binsw_5_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_72/bd_6e35_arinsw_6_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_73/bd_6e35_rinsw_6_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_74/bd_6e35_awinsw_6_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_75/bd_6e35_winsw_6_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_76/bd_6e35_binsw_6_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_77/bd_6e35_arinsw_7_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_78/bd_6e35_rinsw_7_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_79/bd_6e35_awinsw_7_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_80/bd_6e35_winsw_7_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_81/bd_6e35_binsw_7_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_82/bd_6e35_arinsw_8_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_83/bd_6e35_rinsw_8_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_84/bd_6e35_awinsw_8_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_85/bd_6e35_winsw_8_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_86/bd_6e35_binsw_8_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_90/bd_6e35_s00a2s_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_91/bd_6e35_sarn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_92/bd_6e35_srn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_93/bd_6e35_sawn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_94/bd_6e35_swn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_95/bd_6e35_sbn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_96/bd_6e35_m00s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_97/bd_6e35_m00arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_98/bd_6e35_m00rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_99/bd_6e35_m00awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_100/bd_6e35_m00wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_101/bd_6e35_m00bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_103/bd_6e35_m01s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_104/bd_6e35_m01arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_105/bd_6e35_m01rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_106/bd_6e35_m01awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_107/bd_6e35_m01wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_108/bd_6e35_m01bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_110/bd_6e35_m02s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_111/bd_6e35_m02arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_112/bd_6e35_m02rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_113/bd_6e35_m02awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_114/bd_6e35_m02wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_115/bd_6e35_m02bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_117/bd_6e35_m03s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_118/bd_6e35_m03arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_119/bd_6e35_m03rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_120/bd_6e35_m03awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_121/bd_6e35_m03wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_122/bd_6e35_m03bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_124/bd_6e35_m04s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_125/bd_6e35_m04arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_126/bd_6e35_m04rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_127/bd_6e35_m04awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_128/bd_6e35_m04wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_129/bd_6e35_m04bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_131/bd_6e35_m05s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_132/bd_6e35_m05arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_133/bd_6e35_m05rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_134/bd_6e35_m05awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_135/bd_6e35_m05wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_136/bd_6e35_m05bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_138/bd_6e35_m06s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_139/bd_6e35_m06arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_140/bd_6e35_m06rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_141/bd_6e35_m06awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_142/bd_6e35_m06wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_143/bd_6e35_m06bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_145/bd_6e35_m07s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_146/bd_6e35_m07arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_147/bd_6e35_m07rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_148/bd_6e35_m07awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_149/bd_6e35_m07wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_150/bd_6e35_m07bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_152/bd_6e35_m08s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_153/bd_6e35_m08arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_154/bd_6e35_m08rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_155/bd_6e35_m08awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_156/bd_6e35_m08wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_157/bd_6e35_m08bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_159/bd_6e35_m09s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_160/bd_6e35_m09arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_161/bd_6e35_m09rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_162/bd_6e35_m09awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_163/bd_6e35_m09wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_164/bd_6e35_m09bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_166/bd_6e35_m10s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_167/bd_6e35_m10arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_168/bd_6e35_m10rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_169/bd_6e35_m10awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_170/bd_6e35_m10wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_171/bd_6e35_m10bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_173/bd_6e35_m11s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_174/bd_6e35_m11arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_175/bd_6e35_m11rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_176/bd_6e35_m11awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_177/bd_6e35_m11wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_178/bd_6e35_m11bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_180/bd_6e35_m12s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_181/bd_6e35_m12arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_182/bd_6e35_m12rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_183/bd_6e35_m12awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_184/bd_6e35_m12wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_185/bd_6e35_m12bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_187/bd_6e35_m13s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_188/bd_6e35_m13arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_189/bd_6e35_m13rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_190/bd_6e35_m13awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_191/bd_6e35_m13wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_192/bd_6e35_m13bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_194/bd_6e35_m14s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_195/bd_6e35_m14arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_196/bd_6e35_m14rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_197/bd_6e35_m14awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_198/bd_6e35_m14wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_199/bd_6e35_m14bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_201/bd_6e35_m15s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_202/bd_6e35_m15arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_203/bd_6e35_m15rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_204/bd_6e35_m15awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_205/bd_6e35_m15wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_206/bd_6e35_m15bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_208/bd_6e35_m16s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_209/bd_6e35_m16arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_210/bd_6e35_m16rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_211/bd_6e35_m16awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_212/bd_6e35_m16wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_213/bd_6e35_m16bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_215/bd_6e35_m17s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_216/bd_6e35_m17arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_217/bd_6e35_m17rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_218/bd_6e35_m17awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_219/bd_6e35_m17wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_220/bd_6e35_m17bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_222/bd_6e35_m18s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_223/bd_6e35_m18arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_224/bd_6e35_m18rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_225/bd_6e35_m18awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_226/bd_6e35_m18wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_227/bd_6e35_m18bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_229/bd_6e35_m19s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_230/bd_6e35_m19arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_231/bd_6e35_m19rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_232/bd_6e35_m19awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_233/bd_6e35_m19wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_234/bd_6e35_m19bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_236/bd_6e35_m20s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_237/bd_6e35_m20arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_238/bd_6e35_m20rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_239/bd_6e35_m20awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_240/bd_6e35_m20wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_241/bd_6e35_m20bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_243/bd_6e35_m21s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_244/bd_6e35_m21arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_245/bd_6e35_m21rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_246/bd_6e35_m21awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_247/bd_6e35_m21wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_248/bd_6e35_m21bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_2/bd_962a_arsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_3/bd_962a_rsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_4/bd_962a_awsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_5/bd_962a_wsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_6/bd_962a_bsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_10/bd_962a_s00a2s_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_11/bd_962a_sarn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_12/bd_962a_srn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_16/bd_962a_s01a2s_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_17/bd_962a_sawn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_18/bd_962a_swn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_19/bd_962a_sbn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_23/bd_962a_s02a2s_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_24/bd_962a_sawn_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_25/bd_962a_swn_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_26/bd_962a_sbn_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_30/bd_962a_s03a2s_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_31/bd_962a_sawn_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_32/bd_962a_swn_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_33/bd_962a_sbn_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_34/bd_962a_m00s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_35/bd_962a_m00arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_36/bd_962a_m00rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_37/bd_962a_m00awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_38/bd_962a_m00wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_39/bd_962a_m00bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_1/design_a9_1_axi_bram_ctrl_3_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_1/design_a9_1_axis_data_fifo_1_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1_clocks.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_clocks.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_2_0/design_a9_1_axis_data_fifo_2_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_clocks.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_5_0/design_a9_1_axi_bram_ctrl_5_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_6_0/design_a9_1_axi_bram_ctrl_6_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_clocks.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/design_a9_1_ooc.xdc]
add_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/bd/design_a9_1/design_a9_1.bd read_ip -quiet D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.xci
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_2/bd_6e35_arinsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_3/bd_6e35_rinsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_4/bd_6e35_awinsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_5/bd_6e35_winsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_6/bd_6e35_binsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_7/bd_6e35_aroutsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_8/bd_6e35_routsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_9/bd_6e35_awoutsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_10/bd_6e35_woutsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_11/bd_6e35_boutsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_12/bd_6e35_arni_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_13/bd_6e35_rni_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_14/bd_6e35_awni_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_15/bd_6e35_wni_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_16/bd_6e35_bni_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_20/bd_6e35_s00a2s_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_21/bd_6e35_sarn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_22/bd_6e35_srn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_23/bd_6e35_sawn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_24/bd_6e35_swn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_25/bd_6e35_sbn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_26/bd_6e35_m00s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_27/bd_6e35_m00arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_28/bd_6e35_m00rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_29/bd_6e35_m00awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_30/bd_6e35_m00wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_31/bd_6e35_m00bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_33/bd_6e35_m01s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_34/bd_6e35_m01arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_35/bd_6e35_m01rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_36/bd_6e35_m01awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_37/bd_6e35_m01wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_38/bd_6e35_m01bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_40/bd_6e35_m02s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_41/bd_6e35_m02arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_42/bd_6e35_m02rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_43/bd_6e35_m02awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_44/bd_6e35_m02wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_45/bd_6e35_m02bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_47/bd_6e35_m03s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_48/bd_6e35_m03arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_49/bd_6e35_m03rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_50/bd_6e35_m03awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_51/bd_6e35_m03wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_52/bd_6e35_m03bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_54/bd_6e35_m04s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_55/bd_6e35_m04arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_56/bd_6e35_m04rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_57/bd_6e35_m04awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_58/bd_6e35_m04wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_59/bd_6e35_m04bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_61/bd_6e35_m05s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_62/bd_6e35_m05arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_63/bd_6e35_m05rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_64/bd_6e35_m05awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_65/bd_6e35_m05wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_66/bd_6e35_m05bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_68/bd_6e35_m06s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_69/bd_6e35_m06arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_70/bd_6e35_m06rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_71/bd_6e35_m06awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_72/bd_6e35_m06wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_73/bd_6e35_m06bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_75/bd_6e35_m07s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_76/bd_6e35_m07arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_77/bd_6e35_m07rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_78/bd_6e35_m07awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_79/bd_6e35_m07wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_80/bd_6e35_m07bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_82/bd_6e35_m08s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_83/bd_6e35_m08arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_84/bd_6e35_m08rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_85/bd_6e35_m08awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_86/bd_6e35_m08wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_87/bd_6e35_m08bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_89/bd_6e35_m09s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_90/bd_6e35_m09arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_91/bd_6e35_m09rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_92/bd_6e35_m09awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_93/bd_6e35_m09wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_94/bd_6e35_m09bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_2/bd_962a_arsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_3/bd_962a_rsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_4/bd_962a_awsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_5/bd_962a_wsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_6/bd_962a_bsw_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_10/bd_962a_s00a2s_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_11/bd_962a_sarn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_12/bd_962a_srn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_16/bd_962a_s01a2s_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_17/bd_962a_sawn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_18/bd_962a_swn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_19/bd_962a_sbn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_20/bd_962a_m00s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_21/bd_962a_m00arn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_22/bd_962a_m00rn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_23/bd_962a_m00awn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_24/bd_962a_m00wn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_25/bd_962a_m00bn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_1_0_board.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_1_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0_ooc.xdc]
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/design_a9_1_ooc.xdc]
read_ip -quiet D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32.xci read_ip -quiet D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xci
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_ooc.xdc] set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_ooc.xdc]
read_ip -quiet D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/dds_stim_16ch/dds_stim_16ch.xci read_ip -quiet D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/ip/fifo_generator_1/fifo_generator_1.xci
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch_ooc.xdc] set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_clocks.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_ooc.xdc]
read_ip -quiet D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/axis_data_fifo_w32_d16/axis_data_fifo_w32_d16.xci read_ip -quiet D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xci
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d16/axis_data_fifo_w32_d16_ooc.xdc] set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_ooc.xdc]
read_ip -quiet D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.xci read_ip -quiet D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/ip/c_add_s16_s32/c_add_s16_s32.xci
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc] set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32_ooc.xdc]
OPTRACE "Adding files" END { } OPTRACE "Adding files" END { }
# Mark all dcp files as not used in implementation to prevent them from being # Mark all dcp files as not used in implementation to prevent them from being
@@ -280,23 +467,14 @@ OPTRACE "Adding files" END { }
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp set_property used_in_implementation false $dcp
} }
read_xdc D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc read_xdc D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc
set_property used_in_implementation false [get_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc] set_property used_in_implementation false [get_files D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
read_xdc D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc read_xdc D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc
set_property used_in_implementation false [get_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc] set_property used_in_implementation false [get_files D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
read_xdc D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc read_xdc D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc
set_property used_in_implementation false [get_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc] set_property used_in_implementation false [get_files D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
read_xdc D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc
set_property used_in_implementation false [get_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc]
read_xdc D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc
set_property used_in_implementation false [get_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc]
read_xdc D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc
set_property used_in_implementation false [get_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc]
read_xdc dont_touch.xdc read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc] set_property used_in_implementation false [get_files dont_touch.xdc]
@@ -304,7 +482,7 @@ set_param ips.enableIPCacheLiteLoad 1
close [open __synthesis_is_running__ w] close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { } OPTRACE "synth_design" START { }
synth_design -top c64pro_top -part xc7z010clg400-2 synth_design -top c64pro_top -part xc7z020clg400-2
OPTRACE "synth_design" END { } OPTRACE "synth_design" END { }
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
c64_pro.runs/synth_1/c64pro_top.vds
+1003 -873
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c64_pro.runs/synth_1/c64pro_top_utilization_synth.pb
BIN
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c64_pro.runs/synth_1/c64pro_top_utilization_synth.rpt
+75 -62
View File
@@ -1,11 +1,11 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 | Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Sun Aug 4 13:40:31 2024 | Date : Fri Sep 4 15:27:46 2026
| Host : 840-5CG14025H4 running 64-bit major release (build 9200) | Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
| Command : report_utilization -file c64pro_top_utilization_synth.rpt -pb c64pro_top_utilization_synth.pb | Command : report_utilization -file c64pro_top_utilization_synth.rpt -pb c64pro_top_utilization_synth.pb
| Design : c64pro_top | Design : c64pro_top
| Device : xc7z010clg400-2 | Device : xc7z020clg400-2
| Speed File : -2 | Speed File : -2
| Design State : Synthesized | Design State : Synthesized
--------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------
@@ -31,14 +31,14 @@ Table of Contents
+-------------------------+-------+-------+------------+-----------+-------+ +-------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% | | Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+-------+-------+------------+-----------+-------+ +-------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs* | 6173 | 0 | 0 | 17600 | 35.07 | | Slice LUTs* | 7721 | 0 | 0 | 53200 | 14.51 |
| LUT as Logic | 6173 | 0 | 0 | 17600 | 35.07 | | LUT as Logic | 7721 | 0 | 0 | 53200 | 14.51 |
| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 | | LUT as Memory | 0 | 0 | 0 | 17400 | 0.00 |
| Slice Registers | 11236 | 0 | 0 | 35200 | 31.92 | | Slice Registers | 11803 | 0 | 0 | 106400 | 11.09 |
| Register as Flip Flop | 11108 | 0 | 0 | 35200 | 31.56 | | Register as Flip Flop | 11803 | 0 | 0 | 106400 | 11.09 |
| Register as Latch | 128 | 0 | 0 | 35200 | 0.36 | | Register as Latch | 0 | 0 | 0 | 106400 | 0.00 |
| F7 Muxes | 997 | 0 | 0 | 8800 | 11.33 | | F7 Muxes | 1594 | 0 | 0 | 26600 | 5.99 |
| F8 Muxes | 452 | 0 | 0 | 4400 | 10.27 | | F8 Muxes | 712 | 0 | 0 | 13300 | 5.35 |
+-------------------------+-------+-------+------------+-----------+-------+ +-------------------------+-------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining. Warning! LUT value is adjusted to account for LUT combining.
@@ -56,10 +56,10 @@ Warning! LUT value is adjusted to account for LUT combining.
| 0 | _ | Set | - | | 0 | _ | Set | - |
| 0 | _ | Reset | - | | 0 | _ | Reset | - |
| 0 | Yes | - | - | | 0 | Yes | - | - |
| 366 | Yes | - | Set | | 49 | Yes | - | Set |
| 10838 | Yes | - | Reset | | 11681 | Yes | - | Reset |
| 32 | Yes | Set | - | | 64 | Yes | Set | - |
| 0 | Yes | Reset | - | | 9 | Yes | Reset | - |
+-------+--------------+-------------+--------------+ +-------+--------------+-------------+--------------+
@@ -69,9 +69,9 @@ Warning! LUT value is adjusted to account for LUT combining.
+----------------+------+-------+------------+-----------+-------+ +----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% | | Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+ +----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 60 | 0.00 | | Block RAM Tile | 0 | 0 | 0 | 140 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 60 | 0.00 | | RAMB36/FIFO* | 0 | 0 | 0 | 140 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 120 | 0.00 | | RAMB18 | 0 | 0 | 0 | 280 | 0.00 |
+----------------+------+-------+------------+-----------+-------+ +----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -82,7 +82,7 @@ Warning! LUT value is adjusted to account for LUT combining.
+-----------+------+-------+------------+-----------+-------+ +-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% | | Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+ +-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 80 | 0.00 | | DSPs | 0 | 0 | 0 | 220 | 0.00 |
+-----------+------+-------+------------+-----------+-------+ +-----------+------+-------+------------+-----------+-------+
@@ -92,20 +92,20 @@ Warning! LUT value is adjusted to account for LUT combining.
+-----------------------------+------+-------+------------+-----------+-------+ +-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% | | Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+ +-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 76 | 0 | 0 | 100 | 76.00 | | Bonded IOB | 58 | 0 | 0 | 125 | 46.40 |
| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | | Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 | | Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 | | PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 | | PHASER_REF | 0 | 0 | 0 | 4 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 | | OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 | | IN_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 | | IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 96 | 0.00 | | IBUFDS | 0 | 0 | 0 | 121 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 | | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 | | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 100 | 0.00 | | ILOGIC | 0 | 0 | 0 | 125 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 100 | 0.00 | | OLOGIC | 0 | 0 | 0 | 125 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+ +-----------------------------+------+-------+------------+-----------+-------+
@@ -115,13 +115,13 @@ Warning! LUT value is adjusted to account for LUT combining.
+------------+------+-------+------------+-----------+-------+ +------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% | | Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+ +------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 4 | 0 | 0 | 32 | 12.50 | | BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
| BUFIO | 0 | 0 | 0 | 8 | 0.00 | | BUFIO | 0 | 0 | 0 | 16 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 | | MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 | | PLLE2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 | | BUFMRCE | 0 | 0 | 0 | 8 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 48 | 0.00 | | BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 0 | 8 | 0.00 | | BUFR | 0 | 0 | 0 | 16 | 0.00 |
+------------+------+-------+------------+-----------+-------+ +------------+------+-------+------------+-----------+-------+
@@ -148,23 +148,22 @@ Warning! LUT value is adjusted to account for LUT combining.
+----------+-------+---------------------+ +----------+-------+---------------------+
| Ref Name | Used | Functional Category | | Ref Name | Used | Functional Category |
+----------+-------+---------------------+ +----------+-------+---------------------+
| FDCE | 10710 | Flop & Latch | | FDCE | 11681 | Flop & Latch |
| LUT6 | 3858 | LUT | | LUT6 | 4593 | LUT |
| MUXF7 | 997 | MuxFx | | MUXF7 | 1594 | MuxFx |
| LUT3 | 855 | LUT | | LUT2 | 1186 | LUT |
| LUT5 | 846 | LUT | | LUT3 | 794 | LUT |
| LUT2 | 841 | LUT | | LUT5 | 783 | LUT |
| LUT4 | 672 | LUT | | MUXF8 | 712 | MuxFx |
| MUXF8 | 452 | MuxFx | | LUT1 | 653 | LUT |
| FDPE | 366 | Flop & Latch | | LUT4 | 541 | LUT |
| CARRY4 | 274 | CarryLogic | | CARRY4 | 436 | CarryLogic |
| LUT1 | 133 | LUT | | FDSE | 64 | Flop & Latch |
| LDCE | 128 | Flop & Latch | | FDPE | 49 | Flop & Latch |
| OBUF | 56 | IO | | IBUF | 32 | IO |
| FDSE | 32 | Flop & Latch | | OBUFT | 27 | IO |
| IBUF | 20 | IO | | OBUF | 26 | IO |
| OBUFT | 4 | IO | | FDRE | 9 | Flop & Latch |
| BUFG | 4 | Clock |
+----------+-------+---------------------+ +----------+-------+---------------------+
@@ -174,27 +173,41 @@ Warning! LUT value is adjusted to account for LUT combining.
+------------------------------------+------+ +------------------------------------+------+
| Ref Name | Used | | Ref Name | Used |
+------------------------------------+------+ +------------------------------------+------+
| mult_gen_au8_bu9_p8 | 4 | | c_add_s16_s32 | 3 |
| axis_data_fifo_w32_d32 | 4 | | axis_data_fifo_w8_d128 | 2 |
| vio_cur_flt_state | 1 |
| fifo_generator_1 | 1 |
| fifo_generator_0 | 1 |
| design_a9_1_smartconnect_0_0 | 1 | | design_a9_1_smartconnect_0_0 | 1 |
| design_a9_1_rst_ps7_0_50M_0 | 1 | | design_a9_1_rst_ps7_0_50M_0 | 1 |
| design_a9_1_processing_system7_0_0 | 1 | | design_a9_1_processing_system7_0_0 | 1 |
| design_a9_1_axis_data_fifo_2_0 | 1 |
| design_a9_1_axis_data_fifo_1_1 | 1 |
| design_a9_1_axis_data_fifo_1_0 | 1 | | design_a9_1_axis_data_fifo_1_0 | 1 |
| design_a9_1_axis_data_fifo_0_0 | 1 | | design_a9_1_axis_data_fifo_0_0 | 1 |
| design_a9_1_axi_smc_0 | 1 | | design_a9_1_axi_smc_0 | 1 |
| design_a9_1_axi_iic_1_0 | 1 | | design_a9_1_axi_quad_spi_0_0 | 1 |
| design_a9_1_axi_iic_0_0 | 1 | | design_a9_1_axi_gpio_1_0 | 1 |
| design_a9_1_axi_gpio_0_0 | 1 | | design_a9_1_axi_gpio_0_0 | 1 |
| design_a9_1_axi_dma_2_0 | 1 |
| design_a9_1_axi_dma_1_1 | 1 |
| design_a9_1_axi_dma_1_0 | 1 | | design_a9_1_axi_dma_1_0 | 1 |
| design_a9_1_axi_dma_0_0 | 1 | | design_a9_1_axi_dma_0_0 | 1 |
| design_a9_1_axi_bram_ctrl_6_0 | 1 |
| design_a9_1_axi_bram_ctrl_5_0 | 1 |
| design_a9_1_axi_bram_ctrl_4_0 | 1 | | design_a9_1_axi_bram_ctrl_4_0 | 1 |
| design_a9_1_axi_bram_ctrl_3_1 | 1 |
| design_a9_1_axi_bram_ctrl_3_0 | 1 | | design_a9_1_axi_bram_ctrl_3_0 | 1 |
| design_a9_1_axi_bram_ctrl_2_0 | 1 | | design_a9_1_axi_bram_ctrl_2_0 | 1 |
| design_a9_1_axi_bram_ctrl_1_0 | 1 | | design_a9_1_axi_bram_ctrl_1_0 | 1 |
| design_a9_1_axi_bram_ctrl_0_0 | 1 | | design_a9_1_axi_bram_ctrl_0_0 | 1 |
| dds_stim_16ch | 1 | | design_a9_1_Z_IO_0 | 1 |
| axis_data_fifo_w8_d128 | 1 | | design_a9_1_ZCHECK_SPI_0 | 1 |
| axis_data_fifo_w32_d16 | 1 | | design_a9_1_STIM_SPI_0 | 1 |
| design_a9_1_CHANN_SEL_0 | 1 |
| design_a9_1_CHANN_EN_2 | 1 |
| design_a9_1_CHANN_EN_1 | 1 |
| design_a9_1_CHANN_EN_0 | 1 |
+------------------------------------+------+ +------------------------------------+------+
c64_pro.runs/synth_1/dont_touch.xdc
+79 -46
View File
@@ -7,67 +7,100 @@
# XDC: new/c64pro_pins_ic.xdc # XDC: new/c64pro_pins_ic.xdc
# XDC: new/c64pro_pins_misc.xdc
# XDC: new/c64pro_pins_pm.xdc
# XDC: new/c64pro_pins_rsh2116.xdc
# IP: ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==mult_gen_au8_bu9_p8 || ORIG_REF_NAME==mult_gen_au8_bu9_p8} -quiet] -quiet
# Block Designs: bd/design_a9_1/design_a9_1.bd # Block Designs: bd/design_a9_1/design_a9_1.bd
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1 || ORIG_REF_NAME==design_a9_1} -quiet] -quiet set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1 || ORIG_REF_NAME==design_a9_1} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_processing_system7_0_0 || ORIG_REF_NAME==design_a9_1_processing_system7_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_iic_0_0 || ORIG_REF_NAME==design_a9_1_axi_iic_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_gpio_0_0 || ORIG_REF_NAME==design_a9_1_axi_gpio_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_rst_ps7_0_50M_0 || ORIG_REF_NAME==design_a9_1_rst_ps7_0_50M_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/design_a9_1_xlconcat_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_xlconcat_0_0 || ORIG_REF_NAME==design_a9_1_xlconcat_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0.xci # IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_0_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_0_0} -quiet] -quiet set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_0_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_smc_0 || ORIG_REF_NAME==design_a9_1_axi_smc_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_dma_0_0 || ORIG_REF_NAME==design_a9_1_axi_dma_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axis_data_fifo_0_0 || ORIG_REF_NAME==design_a9_1_axis_data_fifo_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axis_data_fifo_1_0 || ORIG_REF_NAME==design_a9_1_axis_data_fifo_1_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_smartconnect_0_0 || ORIG_REF_NAME==design_a9_1_smartconnect_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0.xci # IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_1_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_1_0} -quiet] -quiet set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_1_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_1_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0.xci # IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_2_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_2_0} -quiet] -quiet set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_2_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_2_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_1_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_iic_1_0 || ORIG_REF_NAME==design_a9_1_axi_iic_1_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_dma_1_0 || ORIG_REF_NAME==design_a9_1_axi_dma_1_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0.xci # IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_3_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_3_0} -quiet] -quiet set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_3_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_3_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0.xci # IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_4_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_4_0} -quiet] -quiet set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_4_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_4_0} -quiet] -quiet
# XDC: d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/design_a9_1_ooc.xdc # IP: bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_dma_0_0 || ORIG_REF_NAME==design_a9_1_axi_dma_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_dma_1_0 || ORIG_REF_NAME==design_a9_1_axi_dma_1_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_gpio_0_0 || ORIG_REF_NAME==design_a9_1_axi_gpio_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_smc_0 || ORIG_REF_NAME==design_a9_1_axi_smc_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axis_data_fifo_0_0 || ORIG_REF_NAME==design_a9_1_axis_data_fifo_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axis_data_fifo_1_0 || ORIG_REF_NAME==design_a9_1_axis_data_fifo_1_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_processing_system7_0_0 || ORIG_REF_NAME==design_a9_1_processing_system7_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_rst_ps7_0_50M_0 || ORIG_REF_NAME==design_a9_1_rst_ps7_0_50M_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_smartconnect_0_0 || ORIG_REF_NAME==design_a9_1_smartconnect_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/design_a9_1_xlconcat_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_xlconcat_0_0 || ORIG_REF_NAME==design_a9_1_xlconcat_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_gpio_1_0 || ORIG_REF_NAME==design_a9_1_axi_gpio_1_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_CHANN_EN_0 || ORIG_REF_NAME==design_a9_1_CHANN_EN_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_CHANN_SEL_0 || ORIG_REF_NAME==design_a9_1_CHANN_SEL_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_quad_spi_0_0 || ORIG_REF_NAME==design_a9_1_axi_quad_spi_0_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_CHANN_EN_1 || ORIG_REF_NAME==design_a9_1_CHANN_EN_1} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_1/design_a9_1_axi_bram_ctrl_3_1.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_3_1 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_3_1} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_CHANN_EN_2 || ORIG_REF_NAME==design_a9_1_CHANN_EN_2} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_1/design_a9_1_axis_data_fifo_1_1.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axis_data_fifo_1_1 || ORIG_REF_NAME==design_a9_1_axis_data_fifo_1_1} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_dma_1_1 || ORIG_REF_NAME==design_a9_1_axi_dma_1_1} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_dma_2_0 || ORIG_REF_NAME==design_a9_1_axi_dma_2_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axis_data_fifo_2_0/design_a9_1_axis_data_fifo_2_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axis_data_fifo_2_0 || ORIG_REF_NAME==design_a9_1_axis_data_fifo_2_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_ZCHECK_SPI_0 || ORIG_REF_NAME==design_a9_1_ZCHECK_SPI_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_Z_IO_0 || ORIG_REF_NAME==design_a9_1_Z_IO_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_5_0/design_a9_1_axi_bram_ctrl_5_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_5_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_5_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_6_0/design_a9_1_axi_bram_ctrl_6_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_6_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_6_0} -quiet] -quiet
# IP: bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_STIM_SPI_0 || ORIG_REF_NAME==design_a9_1_STIM_SPI_0} -quiet] -quiet
# XDC: d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/design_a9_1_ooc.xdc
c64_pro.runs/synth_1/gen_run.xml
+106 -157
View File
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7z010clg400-2" LaunchTime="1722749885"> <GenRun Id="synth_1" LaunchPart="xc7z020clg400-2" LaunchTime="1788506600">
<File Type="PA-TCL" Name="c64pro_top.tcl"/> <File Type="PA-TCL" Name="c64pro_top.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="c64pro_top_drc_synth.rpt"/> <File Type="RDS-PROPCONSTRS" Name="c64pro_top_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="c64pro_top_reports.tcl"/> <File Type="REPORTS-TCL" Name="c64pro_top_reports.tcl"/>
@@ -11,13 +11,6 @@
<File Type="VDS-TIMING-PB" Name="c64pro_top_timing_summary_synth.pb"/> <File Type="VDS-TIMING-PB" Name="c64pro_top_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/design_a9_1/design_a9_1.bd"> <File Path="$PSRCDIR/sources_1/bd/design_a9_1/design_a9_1.bd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -32,13 +25,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/switch/adg1414_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_arrange.v"> <File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_arrange.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -46,13 +32,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_spi.v"> <File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_spi.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -67,27 +46,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/switch/channel_switch.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/cnv_res_collect.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/utils/debouncing.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v"> <File Path="$PGENDIR/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -102,6 +60,13 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/upload/eeg_emg_upload.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_top.v"> <File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_top.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -116,13 +81,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/emg/emg_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/led_ctrl.v"> <File Path="$PSRCDIR/sources_1/rtl/led_ctrl.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -144,13 +102,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/rhs2116_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/utils/run_time.v"> <File Path="$PSRCDIR/sources_1/rtl/utils/run_time.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -158,83 +109,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/sine_gen.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/utils/spi_full_duplex_master.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/stim_event_collect.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/stim_monitor.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_arrange.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_distribute.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_timer.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/transmit_config.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/transmit_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/trigger/trigger_detection.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/trigger/trigger_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_config.v"> <File Path="$PSRCDIR/sources_1/rtl/upload/upload_config.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -277,6 +151,90 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_mon_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_mon_config.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_ch_map.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_monitor.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/acq_collect.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/ad7689_dual_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/stim_config.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_top1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_spi1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_if1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="c64pro_top"/> <Option Name="TopModule" Val="c64pro_top"/>
@@ -302,25 +260,8 @@
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_misc.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_pm.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_rsh2116.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config> <Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/c64pro_pins_ic.xdc"/>
<Option Name="ConstrsType" Val="XDC"/> <Option Name="ConstrsType" Val="XDC"/>
</Config> </Config>
</FileSet> </FileSet>
@@ -334,10 +275,18 @@
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w32_d32"/> <BlockFileSet Type="BlockSrcs" Name="design_a9_1_CHANN_EN_1"/>
<BlockFileSet Type="BlockSrcs" Name="dds_stim_16ch"/> <BlockFileSet Type="BlockSrcs" Name="fifo_generator_1"/>
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w32_d16"/>
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w8_d128"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axi_gpio_0_0"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_processing_system7_0_0"/> <BlockFileSet Type="BlockSrcs" Name="design_a9_1_processing_system7_0_0"/>
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w8_d128"/>
<BlockFileSet Type="BlockSrcs" Name="fifo_generator_0"/>
<BlockFileSet Type="BlockSrcs" Name="c_add_s16_s32"/>
<BlockFileSet Type="BlockSrcs" Name="vio_cur_flt_state"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_CHANN_EN_2"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_STIM_SPI_0"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_ZCHECK_SPI_0"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axis_data_fifo_1_1"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axis_data_fifo_2_0"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axi_dma_1_1"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axi_dma_2_0"/>
</GenRun> </GenRun>
c64_pro.runs/synth_1/runme.log
+997 -867
View File
File diff suppressed because it is too large Load Diff
c64_pro.runs/synth_1/runme.sh
+1 -1
View File
@@ -25,7 +25,7 @@ else
fi fi
export LD_LIBRARY_PATH export LD_LIBRARY_PATH
HD_PWD='D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1' HD_PWD='D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1'
cd "$HD_PWD" cd "$HD_PWD"
HD_LOG=runme.log HD_LOG=runme.log
c64_pro.runs/synth_1/vivado.jou
+6 -6
View File
@@ -3,12 +3,12 @@
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023 # SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023 # IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023 # SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Sun Aug 4 13:38:09 2024 # Start of session at: Fri Sep 4 15:23:24 2026
# Process ID: 52932 # Process ID: 8436
# Current directory: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1 # Current directory: D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1
# Command line: vivado.exe -log c64pro_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source c64pro_top.tcl # Command line: vivado.exe -log c64pro_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source c64pro_top.tcl
# Log file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/c64pro_top.vds # Log file: D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/c64pro_top.vds
# Journal file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1\vivado.jou # Journal file: D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1\vivado.jou
# Running On: 840-5CG14025H4, OS: Windows, CPU Frequency: 2803 MHz, CPU Physical cores: 4, Host memory: 34024 MB # Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
#----------------------------------------------------------- #-----------------------------------------------------------
source c64pro_top.tcl -notrace source c64pro_top.tcl -notrace
c64_pro.runs/synth_1/vivado.pb
BIN
View File
Binary file not shown.
c64_pro.runs/vio_cur_flt_state_synth_1/.Vivado_Synthesis.queue.rst
View File
c64_pro.runs/vio_cur_flt_state_synth_1/.Xil/vio_cur_flt_state_propImpl.xdc
+5
View File
@@ -0,0 +1,5 @@
set_property SRC_FILE_INFO {cfile:d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc rfile:../../../LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc id:1 order:EARLY} [current_design]
set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design]
create_waiver -type CDC -id CDC-4 -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter {NAME =~ "*probe_in_reg_reg*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*data_int_sync1_reg*"}]] -user "vio" -description {The path has combinational circuit. But from hardware prospective the design works perfectly and the signals crossing happen after a very long time from the source has the value.} -tags "1050886" -scope -internal
set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design]
create_waiver -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*Hold_probe_in*" && IS_SEQUENTIAL } ]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter { NAME =~ "*PROBE_IN_INST/probe_in_reg*" && IS_SEQUENTIAL} ]] -user "vio" -description {The path has combinational circuit. But from hardware prospective the design works perfectly and the signals crossing happen after a very long time from the source has the value.} -tags "1050886" -scope -internal
c64_pro.runs/vio_cur_flt_state_synth_1/.vivado.begin.rst
+5
View File
@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="lixiangfu" Host="DESKTOP-VN054CM" Pid="34400" HostCore="20" HostMemory="0171579695104">
</Process>
</ProcessHandle>
c64_pro.runs/vio_cur_flt_state_synth_1/.vivado.end.rst
View File
c64_pro.runs/vio_cur_flt_state_synth_1/ISEWrap.js
+270
View File
@@ -0,0 +1,270 @@
//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var wbemFlagReturnImmediately = 0x10;
var wbemFlagForwardOnly = 0x20;
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
var NOC = 0;
var NOLP = 0;
var TPM = 0;
var cpuInfos = new Enumerator(processor);
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
var cpuInfo = cpuInfos.item();
NOC += cpuInfo.NumberOfCores;
NOLP += cpuInfo.NumberOfLogicalProcessors;
}
var csInfos = new Enumerator(computerSystem);
for(;!csInfos.atEnd(); csInfos.moveNext()) {
var csInfo = csInfos.item();
TPM += csInfo.TotalPhysicalMemory;
}
var ISEHOSTCORE = NOLP
var ISEMEMTOTAL = TPM
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\" HostCore=\"" + ISEHOSTCORE +
"\" HostMemory=\"" + ISEMEMTOTAL +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}
c64_pro.runs/vio_cur_flt_state_synth_1/ISEWrap.sh
+85
View File
@@ -0,0 +1,85 @@
#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
#
cmd_exists()
{
command -v "$1" >/dev/null 2>&1
}
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
HostNameFile=/proc/sys/kernel/hostname
if cmd_exists hostname
then
ISE_HOST=$(hostname)
elif cmd_exists uname
then
ISE_HOST=$(uname -n)
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
then
ISE_HOST=$(cat $HostNameFile)
elif [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL
c64_pro.runs/vio_cur_flt_state_synth_1/__synthesis_is_complete__
View File
c64_pro.runs/vio_cur_flt_state_synth_1/gen_run.xml
+45
View File
@@ -0,0 +1,45 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_cur_flt_state_synth_1" LaunchPart="xc7z020clg400-2" LaunchTime="1782280322">
<File Type="PA-TCL" Name="vio_cur_flt_state.tcl"/>
<File Type="REPORTS-TCL" Name="vio_cur_flt_state_reports.tcl"/>
<File Type="RDS-RDS" Name="vio_cur_flt_state.vds"/>
<File Type="RDS-UTIL" Name="vio_cur_flt_state_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="vio_cur_flt_state_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="vio_cur_flt_state.dcp"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_cur_flt_state" RelGenDir="$PGENDIR/vio_cur_flt_state">
<File Path="$PSRCDIR/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="vio_cur_flt_state"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_cur_flt_state" RelGenDir="$PGENDIR/vio_cur_flt_state">
<File Path="$PSRCDIR/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="vio_cur_flt_state"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
c64_pro.runs/vio_cur_flt_state_synth_1/htr.txt
+10
View File
@@ -0,0 +1,10 @@
REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
REM Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
REM
vivado -log vio_cur_flt_state.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_cur_flt_state.tcl
c64_pro.runs/vio_cur_flt_state_synth_1/rundef.js
+37
View File
@@ -0,0 +1,37 @@
//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
//
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "C:/Xilinx/Vitis/2023.1/bin;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2023.1/bin;";
} else {
PathVal = "C:/Xilinx/Vitis/2023.1/bin;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2023.1/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
ISEStep( "vivado",
"-log vio_cur_flt_state.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_cur_flt_state.tcl" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}
c64_pro.runs/vio_cur_flt_state_synth_1/runme.bat
+11
View File
@@ -0,0 +1,11 @@
@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
c64_pro.runs/vio_cur_flt_state_synth_1/runme.log
+374
View File
@@ -0,0 +1,374 @@
*** Running vivado
with args -log vio_cur_flt_state.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_cur_flt_state.tcl
****** Vivado v2023.1 (64-bit)
**** SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
**** IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
**** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source vio_cur_flt_state.tcl -notrace
create_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1468.434 ; gain = 161.480
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: vio_cur_flt_state
Command: synth_design -top vio_cur_flt_state -part xc7z020clg400-2 -incremental_mode off -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 29808
WARNING: [Synth 8-10515] begin/end is required for generate-for in this mode of Verilog [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/hdl/vio_v3_0_syn_rfs.v:1365]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2327.035 ; gain = 409.660
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'vio_cur_flt_state' [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/synth/vio_cur_flt_state.v:49]
INFO: [Synth 8-6155] done synthesizing module 'vio_cur_flt_state' (0#1) [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/synth/vio_cur_flt_state.v:49]
WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_cur_flt_state does not have driver. [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/synth/vio_cur_flt_state.v:73]
WARNING: [Synth 8-7129] Port probe_in3[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in4[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in5[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in6[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in7[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in8[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in9[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in10[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in11[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in12[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in13[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in14[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in15[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in16[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in17[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in18[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in19[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in20[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in21[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in22[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in23[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in24[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in25[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in26[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in27[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in28[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in29[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in30[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in31[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in32[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in33[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in34[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in35[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in36[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in37[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in38[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in39[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in40[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in41[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in42[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in43[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in44[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in45[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in46[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in47[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in48[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in49[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in50[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in51[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in52[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in53[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in54[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in55[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in56[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in57[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in58[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in59[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in60[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in61[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in62[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in63[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in64[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in65[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in66[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in67[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in68[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in69[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in70[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in71[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in72[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in73[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in74[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in75[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in76[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in77[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in78[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in79[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in80[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in81[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in82[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in83[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in84[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in85[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in86[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in87[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in88[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in89[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in90[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in91[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in92[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in93[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in94[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in95[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in96[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in97[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in98[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in99[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in100[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in101[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in102[0] in module vio_v3_0_23_vio is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2441.824 ; gain = 524.449
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2441.824 ; gain = 524.449
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2441.824 ; gain = 524.449
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2441.824 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_ooc.xdc]
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_ooc.xdc]
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/vio_cur_flt_state_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/vio_cur_flt_state_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2509.492 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 2514.125 ; gain = 4.633
INFO: [Designutils 20-5008] Incremental synthesis strategy off
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg400-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 6 Bit Adders := 1
2 Input 1 Bit Adders := 1
+---Registers :
128 Bit Registers := 1
97 Bit Registers := 5
16 Bit Registers := 7
7 Bit Registers := 1
6 Bit Registers := 1
5 Bit Registers := 1
3 Bit Registers := 2
1 Bit Registers := 13
+---Muxes :
2 Input 16 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+------+------+
| |Cell |Count |
+------+------+------+
|1 |LUT1 | 3|
|2 |LUT2 | 5|
|3 |LUT3 | 215|
|4 |LUT4 | 11|
|5 |LUT5 | 22|
|6 |LUT6 | 148|
|7 |MUXF7 | 32|
|8 |MUXF8 | 16|
|9 |FDRE | 739|
+------+------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 291 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:34 ; elapsed = 00:00:50 . Memory (MB): peak = 2514.125 ; gain = 524.449
Synthesis Optimization Complete : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 2514.125 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 48 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2514.125 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete | Checksum: 479f714d
INFO: [Common 17-83] Releasing license: Synthesis
20 Infos, 140 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:59 ; elapsed = 00:01:03 . Memory (MB): peak = 2514.125 ; gain = 1001.438
INFO: [Common 17-1381] The checkpoint 'D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_cur_flt_state, cache-ID = 8d048e0917528583
INFO: [Coretcl 2-1174] Renamed 5 cell refs.
INFO: [Common 17-1381] The checkpoint 'D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file vio_cur_flt_state_utilization_synth.rpt -pb vio_cur_flt_state_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed Jun 24 13:53:40 2026...
c64_pro.runs/vio_cur_flt_state_synth_1/runme.sh
+44
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@@ -0,0 +1,44 @@
#!/bin/sh
#
# Vivado(TM)
# runme.sh: a Vivado-generated Runs Script for UNIX
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
#
echo "This script was generated under a different operating system."
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
exit
if [ -z "$PATH" ]; then
PATH=C:/Xilinx/Vitis/2023.1/bin;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2023.1/bin
else
PATH=C:/Xilinx/Vitis/2023.1/bin;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2023.1/bin:$PATH
fi
export PATH
if [ -z "$LD_LIBRARY_PATH" ]; then
LD_LIBRARY_PATH=
else
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
fi
export LD_LIBRARY_PATH
HD_PWD='D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1'
cd "$HD_PWD"
HD_LOG=runme.log
/bin/touch $HD_LOG
ISEStep="./ISEWrap.sh"
EAStep()
{
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
if [ $? -ne 0 ]
then
exit
fi
}
EAStep vivado -log vio_cur_flt_state.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_cur_flt_state.tcl
c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp
BIN
View File
Binary file not shown.
c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.tcl
+243
View File
@@ -0,0 +1,243 @@
#
# Synthesis run script generated by Vivado
#
set TIME_start [clock seconds]
namespace eval ::optrace {
variable script "D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.tcl"
variable category "vivado_synth"
}
# Try to connect to running dispatch if we haven't done so already.
# This code assumes that the Tcl interpreter is not using threads,
# since the ::dispatch::connected variable isn't mutex protected.
if {![info exists ::dispatch::connected]} {
namespace eval ::dispatch {
variable connected false
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
set result "true"
if {[catch {
if {[lsearch -exact [package names] DispatchTcl] < 0} {
set result [load librdi_cd_clienttcl[info sharedlibextension]]
}
if {$result eq "false"} {
puts "WARNING: Could not load dispatch client library"
}
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
if { $connect_id eq "" } {
puts "WARNING: Could not initialize dispatch client"
} else {
puts "INFO: Dispatch client connection id - $connect_id"
set connected true
}
} catch_res]} {
puts "WARNING: failed to connect to dispatch server - $catch_res"
}
}
}
}
if {$::dispatch::connected} {
# Remove the dummy proc if it exists.
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
rename ::OPTRACE ""
}
proc ::OPTRACE { task action {tags {} } } {
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
}
# dispatch is generic. We specifically want to attach logging.
::vitis_log::connect_client
} else {
# Add dummy proc if it doesn't exist.
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
# Do nothing
}
}
}
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
OPTRACE "vio_cur_flt_state_synth_1" START { ROLLUP_AUTO }
set_param project.vivado.isBlockSynthRun true
set_msg_config -msgmgr_mode ooc_run
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7z020clg400-2
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.cache/wt [current_project]
set_property parent.project_path D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.xpr [current_project]
set_property XPM_LIBRARIES {XPM_CDC XPM_FIFO XPM_MEMORY} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
OPTRACE "Adding files" START { }
read_ip -quiet D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.srcs/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xci
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_ooc.xdc]
OPTRACE "Adding files" END { }
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
set_param ips.enableIPCacheLiteLoad 1
OPTRACE "Configure IP Cache" START { }
set cacheID [config_ip_cache -export -no_bom -dir D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1 -new_name vio_cur_flt_state -ip [get_ips vio_cur_flt_state]]
OPTRACE "Configure IP Cache" END { }
if { $cacheID == "" } {
close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { }
synth_design -top vio_cur_flt_state -part xc7z020clg400-2 -incremental_mode off -mode out_of_context
OPTRACE "synth_design" END { }
OPTRACE "Write IP Cache" START { }
#---------------------------------------------------------
# Generate Checkpoint/Stub/Simulation Files For IP Cache
#---------------------------------------------------------
# disable binary constraint mode for IPCache checkpoints
set_param constraints.enableBinaryConstraints false
catch {
write_checkpoint -force -noxdef -rename_prefix vio_cur_flt_state_ vio_cur_flt_state.dcp
set ipCachedFiles {}
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_cur_flt_state_stub.v
lappend ipCachedFiles vio_cur_flt_state_stub.v
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_cur_flt_state_stub.vhdl
lappend ipCachedFiles vio_cur_flt_state_stub.vhdl
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_cur_flt_state_sim_netlist.v
lappend ipCachedFiles vio_cur_flt_state_sim_netlist.v
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_cur_flt_state_sim_netlist.vhdl
lappend ipCachedFiles vio_cur_flt_state_sim_netlist.vhdl
set TIME_taken [expr [clock seconds] - $TIME_start]
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
config_ip_cache -add -dcp vio_cur_flt_state.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips vio_cur_flt_state]
}
OPTRACE "Write IP Cache" END { }
}
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
}
rename_ref -prefix_all vio_cur_flt_state_
OPTRACE "write_checkpoint" START { CHECKPOINT }
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef vio_cur_flt_state.dcp
OPTRACE "write_checkpoint" END { }
OPTRACE "synth reports" START { REPORT }
create_report "vio_cur_flt_state_synth_1_synth_report_utilization_0" "report_utilization -file vio_cur_flt_state_utilization_synth.rpt -pb vio_cur_flt_state_utilization_synth.pb"
OPTRACE "synth reports" END { }
if { [catch {
file copy -force D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.dcp
} _RESULT ] } {
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
write_verilog -force -mode synth_stub d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode synth_stub d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_verilog -force -mode funcsim d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode funcsim d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
} else {
if { [catch {
file copy -force D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.dcp
} _RESULT ] } {
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
file rename -force D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state_stub.v d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state_stub.vhdl d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state_sim_netlist.v d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state_sim_netlist.vhdl d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
close [open .end.used_ip_cache.rst w]
}; # end if cacheID
if {[file isdir D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.ip_user_files/ip/vio_cur_flt_state]} {
catch {
file copy -force d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.v D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.ip_user_files/ip/vio_cur_flt_state
}
}
if {[file isdir D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.ip_user_files/ip/vio_cur_flt_state]} {
catch {
file copy -force d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.vhdl D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.ip_user_files/ip/vio_cur_flt_state
}
}
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]
OPTRACE "vio_cur_flt_state_synth_1" END { }
c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.vds
+374
View File
@@ -0,0 +1,374 @@
#-----------------------------------------------------------
# Vivado v2023.1 (64-bit)
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Wed Jun 24 13:52:09 2026
# Process ID: 30740
# Current directory: D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1
# Command line: vivado.exe -log vio_cur_flt_state.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_cur_flt_state.tcl
# Log file: D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.vds
# Journal file: D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1\vivado.jou
# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
#-----------------------------------------------------------
source vio_cur_flt_state.tcl -notrace
create_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1468.434 ; gain = 161.480
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: vio_cur_flt_state
Command: synth_design -top vio_cur_flt_state -part xc7z020clg400-2 -incremental_mode off -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 29808
WARNING: [Synth 8-10515] begin/end is required for generate-for in this mode of Verilog [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/hdl/vio_v3_0_syn_rfs.v:1365]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2327.035 ; gain = 409.660
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'vio_cur_flt_state' [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/synth/vio_cur_flt_state.v:49]
INFO: [Synth 8-6155] done synthesizing module 'vio_cur_flt_state' (0#1) [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/synth/vio_cur_flt_state.v:49]
WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_cur_flt_state does not have driver. [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/synth/vio_cur_flt_state.v:73]
WARNING: [Synth 8-7129] Port probe_in3[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in4[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in5[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in6[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in7[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in8[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in9[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in10[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in11[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in12[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in13[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in14[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in15[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in16[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in17[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in18[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in19[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in20[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in21[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in22[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in23[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in24[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in25[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in26[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in27[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in28[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in29[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in30[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in31[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in32[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in33[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in34[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in35[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in36[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in37[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in38[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in39[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in40[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in41[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in42[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in43[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in44[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in45[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in46[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in47[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in48[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in49[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in50[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in51[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in52[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in53[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in54[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in55[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in56[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in57[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in58[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in59[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in60[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in61[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in62[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in63[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in64[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in65[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in66[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in67[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in68[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in69[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in70[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in71[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in72[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in73[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in74[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in75[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in76[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in77[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in78[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in79[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in80[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in81[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in82[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in83[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in84[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in85[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in86[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in87[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in88[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in89[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in90[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in91[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in92[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in93[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in94[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in95[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in96[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in97[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in98[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in99[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in100[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in101[0] in module vio_v3_0_23_vio is either unconnected or has no load
WARNING: [Synth 8-7129] Port probe_in102[0] in module vio_v3_0_23_vio is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2441.824 ; gain = 524.449
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2441.824 ; gain = 524.449
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2441.824 ; gain = 524.449
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2441.824 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_ooc.xdc]
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_ooc.xdc]
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/vio_cur_flt_state_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/vio_cur_flt_state_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2509.492 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 2514.125 ; gain = 4.633
INFO: [Designutils 20-5008] Incremental synthesis strategy off
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg400-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 6 Bit Adders := 1
2 Input 1 Bit Adders := 1
+---Registers :
128 Bit Registers := 1
97 Bit Registers := 5
16 Bit Registers := 7
7 Bit Registers := 1
6 Bit Registers := 1
5 Bit Registers := 1
3 Bit Registers := 2
1 Bit Registers := 13
+---Muxes :
2 Input 16 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+------+------+
| |Cell |Count |
+------+------+------+
|1 |LUT1 | 3|
|2 |LUT2 | 5|
|3 |LUT3 | 215|
|4 |LUT4 | 11|
|5 |LUT5 | 22|
|6 |LUT6 | 148|
|7 |MUXF7 | 32|
|8 |MUXF8 | 16|
|9 |FDRE | 739|
+------+------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 291 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:34 ; elapsed = 00:00:50 . Memory (MB): peak = 2514.125 ; gain = 524.449
Synthesis Optimization Complete : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 2514.125 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 48 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2514.125 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete | Checksum: 479f714d
INFO: [Common 17-83] Releasing license: Synthesis
20 Infos, 140 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:59 ; elapsed = 00:01:03 . Memory (MB): peak = 2514.125 ; gain = 1001.438
INFO: [Common 17-1381] The checkpoint 'D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_cur_flt_state, cache-ID = 8d048e0917528583
INFO: [Coretcl 2-1174] Renamed 5 cell refs.
INFO: [Common 17-1381] The checkpoint 'D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file vio_cur_flt_state_utilization_synth.rpt -pb vio_cur_flt_state_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed Jun 24 13:53:40 2026...
c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state_utilization_synth.pb
BIN
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c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state_utilization_synth.rpt
+178
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Wed Jun 24 13:53:39 2026
| Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
| Command : report_utilization -file vio_cur_flt_state_utilization_synth.rpt -pb vio_cur_flt_state_utilization_synth.pb
| Design : vio_cur_flt_state
| Device : xc7z020clg400-2
| Speed File : -2
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 389 | 0 | 0 | 53200 | 0.73 |
| LUT as Logic | 389 | 0 | 0 | 53200 | 0.73 |
| LUT as Memory | 0 | 0 | 0 | 17400 | 0.00 |
| Slice Registers | 739 | 0 | 0 | 106400 | 0.69 |
| Register as Flip Flop | 739 | 0 | 0 | 106400 | 0.69 |
| Register as Latch | 0 | 0 | 0 | 106400 | 0.00 |
| F7 Muxes | 32 | 0 | 0 | 26600 | 0.12 |
| F8 Muxes | 16 | 0 | 0 | 13300 | 0.12 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 739 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 140 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 140 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 280 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 220 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 125 | 0.00 |
| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 4 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 121 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 125 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 125 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
| BUFIO | 0 | 0 | 0 | 16 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 8 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 0 | 16 | 0.00 |
+------------+------+-------+------------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 739 | Flop & Latch |
| LUT3 | 215 | LUT |
| LUT6 | 148 | LUT |
| MUXF7 | 32 | MuxFx |
| LUT5 | 22 | LUT |
| MUXF8 | 16 | MuxFx |
| LUT4 | 11 | LUT |
| LUT2 | 5 | LUT |
| LUT1 | 3 | LUT |
+----------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
c64_pro.runs/vio_cur_flt_state_synth_1/vivado.jou
+14
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@@ -0,0 +1,14 @@
#-----------------------------------------------------------
# Vivado v2023.1 (64-bit)
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Wed Jun 24 13:52:09 2026
# Process ID: 30740
# Current directory: D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1
# Command line: vivado.exe -log vio_cur_flt_state.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_cur_flt_state.tcl
# Log file: D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.vds
# Journal file: D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1\vivado.jou
# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
#-----------------------------------------------------------
source vio_cur_flt_state.tcl -notrace
c64_pro.runs/vio_cur_flt_state_synth_1/vivado.pb
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c64_pro.sim/pl_top_tb_behav.wcfg
+194
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="pl_top_tb_behav.wdb" id="1">
<top_modules>
<top_module name="glbl" />
<top_module name="pl_top_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="190.665000 us"></ZoomStartTime>
<ZoomEndTime time="221.885001 us"></ZoomEndTime>
<Cursor1Time time="215.685000 us"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="246"></NameColumnWidth>
<ValueColumnWidth column_width="58"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="42" />
<wave_markers>
<marker time="187515000" label="" />
</wave_markers>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /send_enable" type="logic">
<obj_property name="ElementShortName">send_enable</obj_property>
<obj_property name="ObjectShortName">send_enable</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /t_cs_n" type="array">
<obj_property name="ElementShortName">t_cs_n[7:0]</obj_property>
<obj_property name="ObjectShortName">t_cs_n[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /t_tready" type="logic">
<obj_property name="ElementShortName">t_tready</obj_property>
<obj_property name="ObjectShortName">t_tready</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /t_tvalid" type="logic">
<obj_property name="ElementShortName">t_tvalid</obj_property>
<obj_property name="ObjectShortName">t_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /rdatac_enable" type="logic">
<obj_property name="ElementShortName">rdatac_enable</obj_property>
<obj_property name="ObjectShortName">rdatac_enable</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /cnv_start" type="logic">
<obj_property name="ElementShortName">cnv_start</obj_property>
<obj_property name="ObjectShortName">cnv_start</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /drdy" type="logic">
<obj_property name="ElementShortName">drdy</obj_property>
<obj_property name="ObjectShortName">drdy</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /cstate" type="array">
<obj_property name="ElementShortName">cstate[3:0]</obj_property>
<obj_property name="ObjectShortName">cstate[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /nstate" type="array">
<obj_property name="ElementShortName">nstate[3:0]</obj_property>
<obj_property name="ObjectShortName">nstate[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /time_cnt" type="array">
<obj_property name="ElementShortName">time_cnt[15:0]</obj_property>
<obj_property name="ObjectShortName">time_cnt[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /t_cnt" type="array">
<obj_property name="ElementShortName">t_cnt[7:0]</obj_property>
<obj_property name="ObjectShortName">t_cnt[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /cnv_drdy_r" type="array">
<obj_property name="ElementShortName">cnv_drdy_r[3:0]</obj_property>
<obj_property name="ObjectShortName">cnv_drdy_r[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/rst_n" type="logic">
<obj_property name="ElementShortName">rst_n</obj_property>
<obj_property name="ObjectShortName">rst_n</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_cs_n" type="array">
<obj_property name="ElementShortName">t_cs_n[7:0]</obj_property>
<obj_property name="ObjectShortName">t_cs_n[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tdata" type="array">
<obj_property name="ElementShortName">t_tdata[7:0]</obj_property>
<obj_property name="ObjectShortName">t_tdata[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tlast" type="logic">
<obj_property name="ElementShortName">t_tlast</obj_property>
<obj_property name="ObjectShortName">t_tlast</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tready" type="logic">
<obj_property name="ElementShortName">t_tready</obj_property>
<obj_property name="ObjectShortName">t_tready</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tvalid" type="logic">
<obj_property name="ElementShortName">t_tvalid</obj_property>
<obj_property name="ObjectShortName">t_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tdata" type="array">
<obj_property name="ElementShortName">r_tdata[7:0]</obj_property>
<obj_property name="ObjectShortName">r_tdata[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tlast" type="logic">
<obj_property name="ElementShortName">r_tlast</obj_property>
<obj_property name="ObjectShortName">r_tlast</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tvalid" type="logic">
<obj_property name="ElementShortName">r_tvalid</obj_property>
<obj_property name="ObjectShortName">r_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs" type="array">
<obj_property name="ElementShortName">cs[0:0]</obj_property>
<obj_property name="ObjectShortName">cs[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sclk" type="logic">
<obj_property name="ElementShortName">sclk</obj_property>
<obj_property name="ObjectShortName">sclk</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/mosi" type="logic">
<obj_property name="ElementShortName">mosi</obj_property>
<obj_property name="ObjectShortName">mosi</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/miso" type="logic">
<obj_property name="ElementShortName">miso</obj_property>
<obj_property name="ObjectShortName">miso</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cstate" type="array">
<obj_property name="ElementShortName">cstate[3:0]</obj_property>
<obj_property name="ObjectShortName">cstate[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sck_neg" type="logic">
<obj_property name="ElementShortName">sck_neg</obj_property>
<obj_property name="ObjectShortName">sck_neg</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/nstate" type="array">
<obj_property name="ElementShortName">nstate[3:0]</obj_property>
<obj_property name="ObjectShortName">nstate[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/trans_cnt" type="array">
<obj_property name="ElementShortName">trans_cnt[7:0]</obj_property>
<obj_property name="ObjectShortName">trans_cnt[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/slv_n" type="array">
<obj_property name="ElementShortName">slv_n[7:0]</obj_property>
<obj_property name="ObjectShortName">slv_n[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs_release" type="array">
<obj_property name="ElementShortName">cs_release[0:0]</obj_property>
<obj_property name="ObjectShortName">cs_release[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/tx_data" type="array">
<obj_property name="ElementShortName">tx_data[7:0]</obj_property>
<obj_property name="ObjectShortName">tx_data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/rx_data" type="array">
<obj_property name="ElementShortName">rx_data[7:0]</obj_property>
<obj_property name="ObjectShortName">rx_data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/clk_en" type="logic">
<obj_property name="ElementShortName">clk_en</obj_property>
<obj_property name="ObjectShortName">clk_en</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cnt" type="array">
<obj_property name="ElementShortName">cnt[8:0]</obj_property>
<obj_property name="ObjectShortName">cnt[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sck_pos" type="logic">
<obj_property name="ElementShortName">sck_pos</obj_property>
<obj_property name="ObjectShortName">sck_pos</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs_r" type="array">
<obj_property name="ElementShortName">cs_r[0:0]</obj_property>
<obj_property name="ObjectShortName">cs_r[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sclk_r" type="logic">
<obj_property name="ElementShortName">sclk_r</obj_property>
<obj_property name="ObjectShortName">sclk_r</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_sccs_cnt" type="array">
<obj_property name="ElementShortName">t_sccs_cnt[7:0]</obj_property>
<obj_property name="ObjectShortName">t_sccs_cnt[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_sch_cnt" type="array">
<obj_property name="ElementShortName">t_sch_cnt[7:0]</obj_property>
<obj_property name="ObjectShortName">t_sch_cnt[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/read_flag" type="logic">
<obj_property name="ElementShortName">read_flag</obj_property>
<obj_property name="ObjectShortName">read_flag</obj_property>
</wvobject>
</wave_config>
c64_pro.sim/sim_1/behav/modelsim/compile.bat
+2 -2
View File
@@ -6,7 +6,7 @@ REM Filename : compile.bat
REM Simulator : Siemens ModelSim Simulator REM Simulator : Siemens ModelSim Simulator
REM Description : Script for compiling the simulation design source files REM Description : Script for compiling the simulation design source files
REM REM
REM Generated by Vivado on Mon Jul 29 14:48:46 +0800 2024 REM Generated by Vivado on Mon Oct 20 14:37:06 +0800 2025
REM SW Build 3865809 on Sun May 7 15:05:29 MDT 2023 REM SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
REM REM
REM IP Build 3864474 on Sun May 7 20:36:21 MDT 2023 REM IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
@@ -14,7 +14,7 @@ REM
REM usage: compile.bat REM usage: compile.bat
REM REM
REM **************************************************************************** REM ****************************************************************************
set bin_path=C:\modeltech64_10.7\win64 set bin_path=D:\Program files\modelsim\win64
call %bin_path%/vsim -c -do "do {pl_top_tb_compile.do}" -l compile.log call %bin_path%/vsim -c -do "do {pl_top_tb_compile.do}" -l compile.log
if "%errorlevel%"=="1" goto END if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS if "%errorlevel%"=="0" goto SUCCESS
c64_pro.sim/sim_1/behav/modelsim/pl_top_tb_compile.do
+1 -2
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@@ -1,7 +1,7 @@
###################################################################### ######################################################################
# #
# File name : pl_top_tb_compile.do # File name : pl_top_tb_compile.do
# Created on: Mon Jul 29 14:48:46 +0800 2024 # Created on: Mon Oct 20 14:37:05 +0800 2025
# #
# Auto generated by Vivado for 'behavioral' simulation # Auto generated by Vivado for 'behavioral' simulation
# #
@@ -117,7 +117,6 @@ vlog -incr -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" \ "../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" \ "../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" \ "../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" \
"../../../../c64_pro.srcs/sources_1/rtl/emg/emg_top.v" \
"../../../../c64_pro.srcs/sources_1/rtl/pl_top.v" \ "../../../../c64_pro.srcs/sources_1/rtl/pl_top.v" \
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" \ "../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" \
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top.v" \ "../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top.v" \
c64_pro.sim/sim_1/behav/xsim/compile.bat
+30
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@@ -0,0 +1,30 @@
@echo off
REM ****************************************************************************
REM Vivado (TM) v2023.1 (64-bit)
REM
REM Filename : compile.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for compiling the simulation design source files
REM
REM Generated by Vivado on Thu Sep 03 09:56:46 +0800 2026
REM SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
REM
REM IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
REM
REM usage: compile.bat
REM
REM ****************************************************************************
REM compile Verilog/System Verilog design sources
echo "xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
call xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj -log xvlog.log
call type xvlog.log > compile.log
REM compile VHDL design sources
echo "xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
call xvhdl --incr --relax -prj pl_top_tb_vhdl.prj -log xvhdl.log
call type xvhdl.log >> compile.log
if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS
:END
exit 1
:SUCCESS
exit 0
c64_pro.sim/sim_1/behav/xsim/compile.log
+143
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@@ -0,0 +1,143 @@
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_962a
INFO: [VRFC 10-311] analyzing module clk_map_imp_MO2W24
INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_1AX6TQV
INFO: [VRFC 10-311] analyzing module m00_nodes_imp_1X4T3QZ
INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_BPMQL0
INFO: [VRFC 10-311] analyzing module s00_nodes_imp_HMS2Z2
INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_1D6QMRK
INFO: [VRFC 10-311] analyzing module s01_nodes_imp_193AQ2G
INFO: [VRFC 10-311] analyzing module switchboards_imp_NFUYHM
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_a9_1_smartconnect_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_a9_1_xlconcat_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_a9_1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/accel/accel_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module accel_top
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ads1299_arrange
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ads1299_if
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ads1299_spi
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module breath_gen
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_a9_1_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eeg_config
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eeg_emg_upload
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eeg_top
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eeg_upload
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module led_ctrl
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module pl_top
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module pwm_gen
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/run_time.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module run_time
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_config.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module upload_config
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module upload_protocol_intan
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module upload_protocol_ql
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module upload_sort
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module upload_top
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/c64pro_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module c64pro_top
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module cur_mon_top
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module cur_mon_config
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module cur_ch_map
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module cur_monitor
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module acq_collect
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ad7689_dual_if
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ad7689_dual_ctrl
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/stim_config.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module stim_config
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eeg_top1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ads1299_mod
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module rhs2116_mod
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module pl_top_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eeg_top_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module spi_full_duplex_master_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module rhs2116_top_tb_stim
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module rhs2116_top_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module sine_gen_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module led_ctrl_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trigger_top_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module channel_switch_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module adg1414_if_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module transmit_config_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module cnv_res_collect_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trans_timer_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v:18]
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v:18]
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_axis
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_base
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_reg_bit
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_rst
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_memory_base
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v:58]
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
WARNING: [VRFC 10-3609] overwriting previous definition of module 'glbl' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v:6]
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_cdc_sync_rst'
INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0\'
INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0\'
INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1\'
INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1\'
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_reg_bit'
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_rst'
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_memory_base'
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_base'
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_axis'
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top'
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
c64_pro.sim/sim_1/behav/xsim/elaborate.bat
+25
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@@ -0,0 +1,25 @@
@echo off
REM ****************************************************************************
REM Vivado (TM) v2023.1 (64-bit)
REM
REM Filename : elaborate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for elaborating the compiled design
REM
REM Generated by Vivado on Thu Sep 03 09:56:56 +0800 2026
REM SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
REM
REM IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
REM
REM usage: elaborate.bat
REM
REM ****************************************************************************
REM elaborate design
echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log"
call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
if "%errorlevel%"=="0" goto SUCCESS
if "%errorlevel%"=="1" goto END
:END
exit 1
:SUCCESS
exit 0
c64_pro.sim/sim_1/behav/xsim/elaborate.log
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Vivado Simulator v2023.1
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2023.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_sclk' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:422]
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:423]
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:424]
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_drdy_n' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:425]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'eeg_ads1299_start' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:426]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_tr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_rr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:124]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cnv' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'sck' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:514]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:515]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'debug_sig' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:521]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 64 for port 'probe_in2' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:292]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:626]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:630]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:632]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:640]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:642]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:678]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:682]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:684]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:692]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:694]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'accel_data' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:696]
WARNING: [VRFC 10-5021] port 'bram_cur_addr' is not connected on this instance [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:329]
WARNING: [VRFC 10-3705] select index 4 into 'emg_ads1299_drdy_w' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1514]
WARNING: [VRFC 10-3705] select index 4 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1520]
WARNING: [VRFC 10-3705] select index 6 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1521]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=6...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=3...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=32,USE_...
Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
Compiling module xil_defaultlib.axis_data_fifo_w32_d32
Compiling module xil_defaultlib.eeg_config(SPIS_QTY=2)
Compiling module xil_defaultlib.ads1299_arrange_default
Compiling module xil_defaultlib.ads1299_spi(NO_OF_SLAVES=2)
Compiling module xil_defaultlib.ads1299_if
Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=2)
Compiling module xil_defaultlib.eeg_top_default
Compiling module xil_defaultlib.ads1299_spi_default
Compiling module xil_defaultlib.ads1299_if(SPI_SLAVE_QTY=1)
Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=1)
Compiling module xil_defaultlib.eeg_top1(CHIPSET_QTY=1,SPIS_QTY=...
Compiling module xil_defaultlib.cur_mon_config(CH_QTY=16)
Compiling module xil_defaultlib.ad7689_dual_ctrl(CLK_PERIOD=500)
Compiling module xil_defaultlib.ad7689_dual_if(CLK_PERIOD=500)
Compiling module xil_defaultlib.acq_collect(CLK_PERIOD=500,SPI_Q...
Compiling module xil_defaultlib.cur_ch_map(CLK_PERIOD=500,CH_QTY...
Compiling module unisims_ver.GND
Compiling module unisims_ver.FDRE_default
Compiling module unisims_ver.CARRY4
Compiling module unisims_ver.x_lut2_mux4
Compiling module unisims_ver.LUT2
Compiling module xil_defaultlib.c_add_s16_s32
Compiling module xil_defaultlib.cur_monitor(CLK_PERIOD=500,CH_QT...
Compiling module unisims_ver.LUT5
Compiling module unisims_ver.LUT6
Compiling module unisims_ver.LUT4
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling module unisims_ver.x_lut3_mux8
Compiling module unisims_ver.LUT3
Compiling module unisims_ver.MUXF8
Compiling module unisims_ver.MUXF7
Compiling module xil_defaultlib.vio_cur_flt_state
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray__2
Compiling module unisims_ver.FDSE_default
Compiling module unisims_ver.SRL16E_default
Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=36,READ_WI...
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single_...
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
Compiling module xil_defaultlib.fifo_generator_1
Compiling module xil_defaultlib.cur_mon_top(CLK_PERIOD=500)
Compiling module xil_defaultlib.accel_top
Compiling module xil_defaultlib.run_time_default
Compiling module xil_defaultlib.upload_config(PRE_MSG_LEN=128)
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=128,TDA...
Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
Compiling module xil_defaultlib.axis_data_fifo_w8_d128
Compiling module xil_defaultlib.upload_sort_default
Compiling module xil_defaultlib.upload_protocol_ql_default
Compiling module xil_defaultlib.upload_protocol_intan
Compiling module xil_defaultlib.upload_top
Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_sync_stag...
Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_bhv_ver_a...
Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_CONV_VER(...
Compiling module fifo_generator_v13_2_8.fifo_generator_vlog_beh(C_DATA_C...
Compiling module xil_defaultlib.fifo_generator_0
Compiling module xil_defaultlib.eeg_emg_upload
Compiling module xil_defaultlib.stim_config
Compiling module xil_defaultlib.pl_top
Compiling module xil_defaultlib.rhs2116_mod
Compiling module xil_defaultlib.ads1299_mod
Compiling module xil_defaultlib.pl_top_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot pl_top_tb_behav
c64_pro.sim/sim_1/behav/xsim/glbl.v
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem
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c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif
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c64_pro.sim/sim_1/behav/xsim/pl_top_tb.tcl
+11
View File
@@ -0,0 +1,11 @@
set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns
c64_pro.sim/sim_1/behav/xsim/pl_top_tb_behav.wdb
BIN
View File
Binary file not shown.
c64_pro.sim/sim_1/behav/xsim/pl_top_tb_vhdl.prj
+32
View File
@@ -0,0 +1,32 @@
# compile vhdl design source files
vhdl xil_defaultlib \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/sim/design_a9_1_CHANN_EN_1.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/sim/design_a9_1_CHANN_EN_2.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/sim/design_a9_1_STIM_SPI_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/sim/design_a9_1_ZCHECK_SPI_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/sim/design_a9_1_axi_dma_2_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/sim/design_a9_1_axi_dma_1_1.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/sim/design_a9_1_axi_bram_ctrl_0_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/sim/design_a9_1_axi_bram_ctrl_1_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/sim/design_a9_1_axi_bram_ctrl_2_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/sim/design_a9_1_axi_bram_ctrl_3_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/sim/design_a9_1_axi_bram_ctrl_4_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/sim/design_a9_1_axi_dma_0_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/sim/design_a9_1_axi_dma_1_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/sim/design_a9_1_axi_gpio_0_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/sim/bd_6e35_psr_aclk_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/sim/design_a9_1_rst_ps7_0_50M_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/sim/bd_962a_psr_aclk_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/sim/design_a9_1_axi_gpio_1_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/sim/design_a9_1_CHANN_EN_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/sim/design_a9_1_CHANN_SEL_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/sim/design_a9_1_axi_quad_spi_0_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_1/sim/design_a9_1_axi_bram_ctrl_3_1.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_Z_IO_0/sim/design_a9_1_Z_IO_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_5_0/sim/design_a9_1_axi_bram_ctrl_5_0.vhd" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_6_0/sim/design_a9_1_axi_bram_ctrl_6_0.vhd" \
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.vhdl" \
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" \
# Do not sort compile order
nosort
c64_pro.sim/sim_1/behav/xsim/pl_top_tb_vlog.prj
+369
View File
@@ -0,0 +1,369 @@
# compile verilog/system verilog design source files
verilog xil_defaultlib --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" --include "../../../../c64_pro.ip_user_files/ipstatic/hdl" --include "C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/sim/design_a9_1_processing_system7_0_0.v" \
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/sim/axis_data_fifo_w8_d128.v" \
"../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v" \
"../../../../LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_sim_netlist.v" \
"../../../../LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_sim_netlist.v" \
"../../../../LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32_sim_netlist.v" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_2_0/sim/design_a9_1_axis_data_fifo_2_0.v" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_1/sim/design_a9_1_axis_data_fifo_1_1.v" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_0/sim/bd_6e35_one_0.v" \
sv xil_defaultlib --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" --include "../../../../c64_pro.ip_user_files/ipstatic/hdl" --include "C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_2/sim/bd_6e35_arinsw_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_3/sim/bd_6e35_rinsw_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_4/sim/bd_6e35_awinsw_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_5/sim/bd_6e35_winsw_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_6/sim/bd_6e35_binsw_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_7/sim/bd_6e35_arni_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_8/sim/bd_6e35_rni_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_9/sim/bd_6e35_awni_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_10/sim/bd_6e35_wni_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_11/sim/bd_6e35_bni_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_12/sim/bd_6e35_arni_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_13/sim/bd_6e35_rni_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_14/sim/bd_6e35_awni_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_15/sim/bd_6e35_wni_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_16/sim/bd_6e35_bni_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_17/sim/bd_6e35_arni_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_18/sim/bd_6e35_rni_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_19/sim/bd_6e35_awni_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_20/sim/bd_6e35_wni_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_21/sim/bd_6e35_bni_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_22/sim/bd_6e35_arni_3.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_23/sim/bd_6e35_rni_3.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_24/sim/bd_6e35_awni_3.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_25/sim/bd_6e35_wni_3.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_26/sim/bd_6e35_bni_3.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_27/sim/bd_6e35_arni_4.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_28/sim/bd_6e35_rni_4.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_29/sim/bd_6e35_awni_4.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_30/sim/bd_6e35_wni_4.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_31/sim/bd_6e35_bni_4.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_32/sim/bd_6e35_arni_5.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_33/sim/bd_6e35_rni_5.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_34/sim/bd_6e35_awni_5.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_35/sim/bd_6e35_wni_5.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_36/sim/bd_6e35_bni_5.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_37/sim/bd_6e35_arni_6.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_38/sim/bd_6e35_rni_6.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_39/sim/bd_6e35_awni_6.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_40/sim/bd_6e35_wni_6.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_41/sim/bd_6e35_bni_6.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_42/sim/bd_6e35_arni_7.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_43/sim/bd_6e35_rni_7.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_44/sim/bd_6e35_awni_7.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_45/sim/bd_6e35_wni_7.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_46/sim/bd_6e35_bni_7.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_47/sim/bd_6e35_arinsw_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_48/sim/bd_6e35_rinsw_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_49/sim/bd_6e35_awinsw_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_50/sim/bd_6e35_winsw_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_51/sim/bd_6e35_binsw_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_52/sim/bd_6e35_arinsw_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_53/sim/bd_6e35_rinsw_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_54/sim/bd_6e35_awinsw_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_55/sim/bd_6e35_winsw_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_56/sim/bd_6e35_binsw_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_57/sim/bd_6e35_arinsw_3.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_58/sim/bd_6e35_rinsw_3.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_59/sim/bd_6e35_awinsw_3.sv" \
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"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_190/sim/bd_6e35_m13awn_0.sv" \
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"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_196/sim/bd_6e35_m14rn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_197/sim/bd_6e35_m14awn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_198/sim/bd_6e35_m14wn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_199/sim/bd_6e35_m14bn_0.sv" \
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"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_207/sim/bd_6e35_m15e_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_208/sim/bd_6e35_m16s2a_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_209/sim/bd_6e35_m16arn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_210/sim/bd_6e35_m16rn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_211/sim/bd_6e35_m16awn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_212/sim/bd_6e35_m16wn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_213/sim/bd_6e35_m16bn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_214/sim/bd_6e35_m16e_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_215/sim/bd_6e35_m17s2a_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_216/sim/bd_6e35_m17arn_0.sv" \
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"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_218/sim/bd_6e35_m17awn_0.sv" \
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"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_220/sim/bd_6e35_m17bn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_221/sim/bd_6e35_m17e_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_222/sim/bd_6e35_m18s2a_0.sv" \
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"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_224/sim/bd_6e35_m18rn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_225/sim/bd_6e35_m18awn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_226/sim/bd_6e35_m18wn_0.sv" \
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"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_229/sim/bd_6e35_m19s2a_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_230/sim/bd_6e35_m19arn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_231/sim/bd_6e35_m19rn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_232/sim/bd_6e35_m19awn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_233/sim/bd_6e35_m19wn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_234/sim/bd_6e35_m19bn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_235/sim/bd_6e35_m19e_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_236/sim/bd_6e35_m20s2a_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_237/sim/bd_6e35_m20arn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_238/sim/bd_6e35_m20rn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_239/sim/bd_6e35_m20awn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_240/sim/bd_6e35_m20wn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_241/sim/bd_6e35_m20bn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_242/sim/bd_6e35_m20e_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_243/sim/bd_6e35_m21s2a_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_244/sim/bd_6e35_m21arn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_245/sim/bd_6e35_m21rn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_246/sim/bd_6e35_m21awn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_247/sim/bd_6e35_m21wn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_248/sim/bd_6e35_m21bn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_249/sim/bd_6e35_m21e_0.sv" \
verilog xil_defaultlib --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" --include "../../../../c64_pro.ip_user_files/ipstatic/hdl" --include "C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/sim/bd_6e35.v" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/sim/design_a9_1_axi_smc_0.v" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/sim/design_a9_1_axis_data_fifo_0_0.v" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/sim/design_a9_1_axis_data_fifo_1_0.v" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_0/sim/bd_962a_one_0.v" \
sv xil_defaultlib --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" --include "../../../../c64_pro.ip_user_files/ipstatic/hdl" --include "C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_2/sim/bd_962a_arsw_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_3/sim/bd_962a_rsw_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_4/sim/bd_962a_awsw_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_5/sim/bd_962a_wsw_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_6/sim/bd_962a_bsw_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_7/sim/bd_962a_s00mmu_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_8/sim/bd_962a_s00tr_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_9/sim/bd_962a_s00sic_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_10/sim/bd_962a_s00a2s_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_11/sim/bd_962a_sarn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_12/sim/bd_962a_srn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_13/sim/bd_962a_s01mmu_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_14/sim/bd_962a_s01tr_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_15/sim/bd_962a_s01sic_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_16/sim/bd_962a_s01a2s_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_17/sim/bd_962a_sawn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_18/sim/bd_962a_swn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_19/sim/bd_962a_sbn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_20/sim/bd_962a_s02mmu_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_21/sim/bd_962a_s02tr_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_22/sim/bd_962a_s02sic_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_23/sim/bd_962a_s02a2s_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_24/sim/bd_962a_sawn_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_25/sim/bd_962a_swn_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_26/sim/bd_962a_sbn_1.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_27/sim/bd_962a_s03mmu_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_28/sim/bd_962a_s03tr_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_29/sim/bd_962a_s03sic_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_30/sim/bd_962a_s03a2s_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_31/sim/bd_962a_sawn_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_32/sim/bd_962a_swn_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_33/sim/bd_962a_sbn_2.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_34/sim/bd_962a_m00s2a_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_35/sim/bd_962a_m00arn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_36/sim/bd_962a_m00rn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_37/sim/bd_962a_m00awn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_38/sim/bd_962a_m00wn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_39/sim/bd_962a_m00bn_0.sv" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_40/sim/bd_962a_m00e_0.sv" \
verilog xil_defaultlib --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" --include "../../../../c64_pro.ip_user_files/ipstatic/hdl" --include "C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" \
"../../../../c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" \
"../../../../c64_pro.srcs/sources_1/rtl/accel/accel_top.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" \
"../../../../c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" \
"../../../../c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" \
"../../../../c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" \
"../../../../c64_pro.srcs/sources_1/rtl/led_ctrl.v" \
"../../../../c64_pro.srcs/sources_1/rtl/pl_top.v" \
"../../../../c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" \
"../../../../c64_pro.srcs/sources_1/rtl/utils/run_time.v" \
"../../../../c64_pro.srcs/sources_1/rtl/upload/upload_config.v" \
"../../../../c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" \
"../../../../c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" \
"../../../../c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" \
"../../../../c64_pro.srcs/sources_1/rtl/upload/upload_top.v" \
"../../../../c64_pro.srcs/sources_1/rtl/c64pro_top.v" \
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" \
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" \
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" \
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" \
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" \
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" \
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" \
"../../../../c64_pro.srcs/sources_1/rtl/stim_config.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" \
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" \
"../../../../c64_pro.srcs/sources_1/rtl/pl_top_tb.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" \
"../../../../c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" \
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" \
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" \
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" \
"../../../../c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" \
"../../../../c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" \
"../../../../c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" \
"../../../../c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" \
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" \
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" \
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" \
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" \
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" \
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" \
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort
c64_pro.sim/sim_1/behav/xsim/protoinst_files/bd_6e35.protoinst
+4521
View File
File diff suppressed because it is too large Load Diff
c64_pro.sim/sim_1/behav/xsim/protoinst_files/bd_962a.protoinst
+1201
View File
File diff suppressed because it is too large Load Diff
c64_pro.sim/sim_1/behav/xsim/protoinst_files/design_a9_1.protoinst
+1594
View File
File diff suppressed because it is too large Load Diff
c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_axi_smc_0.mem
+961
View File
@@ -0,0 +1,961 @@
NUM_SI 1
NUM_MI 22
NUM_CLKS 1
S00_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
S00_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
S00_AXI.CONFIG.NUM_READ_OUTSTANDING 8
S00_AXI.CONFIG.DATA_WIDTH 32
S00_AXI.CONFIG.DATAWIDTH 32
S00_AXI.CONFIG.PROTOCOL AXI3
S00_AXI.CONFIG.FREQ_HZ 100000000
S00_AXI.CONFIG.ID_WIDTH 12
S00_AXI.CONFIG.ADDR_WIDTH 32
S00_AXI.CONFIG.AWUSER_WIDTH 0
S00_AXI.CONFIG.ARUSER_WIDTH 0
S00_AXI.CONFIG.WUSER_WIDTH 0
S00_AXI.CONFIG.RUSER_WIDTH 0
S00_AXI.CONFIG.BUSER_WIDTH 0
S00_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
S00_AXI.CONFIG.HAS_BURST 1
S00_AXI.CONFIG.HAS_LOCK 1
S00_AXI.CONFIG.HAS_PROT 1
S00_AXI.CONFIG.HAS_CACHE 1
S00_AXI.CONFIG.HAS_QOS 1
S00_AXI.CONFIG.HAS_REGION 0
S00_AXI.CONFIG.HAS_WSTRB 1
S00_AXI.CONFIG.HAS_BRESP 1
S00_AXI.CONFIG.HAS_RRESP 1
S00_AXI.CONFIG.MAX_BURST_LENGTH 16
S00_AXI.CONFIG.PHASE 0.0
S00_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
S00_AXI.CONFIG.NUM_READ_THREADS 4
S00_AXI.CONFIG.NUM_WRITE_THREADS 4
S00_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
S00_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
S00_AXI.CONFIG.INSERT_VIP 0
M00_AXI.CONFIG.DATA_WIDTH 32
M00_AXI.CONFIG.DATAWIDTH 32
M00_AXI.CONFIG.PROTOCOL AXI4LITE
M00_AXI.CONFIG.FREQ_HZ 100000000
M00_AXI.CONFIG.ID_WIDTH 0
M00_AXI.CONFIG.ADDR_WIDTH 13
M00_AXI.CONFIG.AWUSER_WIDTH 0
M00_AXI.CONFIG.ARUSER_WIDTH 0
M00_AXI.CONFIG.WUSER_WIDTH 0
M00_AXI.CONFIG.RUSER_WIDTH 0
M00_AXI.CONFIG.BUSER_WIDTH 0
M00_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M00_AXI.CONFIG.HAS_BURST 0
M00_AXI.CONFIG.HAS_LOCK 0
M00_AXI.CONFIG.HAS_PROT 1
M00_AXI.CONFIG.HAS_CACHE 0
M00_AXI.CONFIG.HAS_QOS 0
M00_AXI.CONFIG.HAS_REGION 0
M00_AXI.CONFIG.HAS_WSTRB 1
M00_AXI.CONFIG.HAS_BRESP 1
M00_AXI.CONFIG.HAS_RRESP 1
M00_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M00_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M00_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M00_AXI.CONFIG.MAX_BURST_LENGTH 1
M00_AXI.CONFIG.PHASE 0.0
M00_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M00_AXI.CONFIG.NUM_READ_THREADS 1
M00_AXI.CONFIG.NUM_WRITE_THREADS 1
M00_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M00_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M00_AXI.CONFIG.INSERT_VIP 0
M01_AXI.CONFIG.DATA_WIDTH 32
M01_AXI.CONFIG.DATAWIDTH 32
M01_AXI.CONFIG.PROTOCOL AXI4LITE
M01_AXI.CONFIG.FREQ_HZ 100000000
M01_AXI.CONFIG.ID_WIDTH 0
M01_AXI.CONFIG.ADDR_WIDTH 9
M01_AXI.CONFIG.AWUSER_WIDTH 0
M01_AXI.CONFIG.ARUSER_WIDTH 0
M01_AXI.CONFIG.WUSER_WIDTH 0
M01_AXI.CONFIG.RUSER_WIDTH 0
M01_AXI.CONFIG.BUSER_WIDTH 0
M01_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M01_AXI.CONFIG.HAS_BURST 0
M01_AXI.CONFIG.HAS_LOCK 0
M01_AXI.CONFIG.HAS_PROT 0
M01_AXI.CONFIG.HAS_CACHE 0
M01_AXI.CONFIG.HAS_QOS 0
M01_AXI.CONFIG.HAS_REGION 0
M01_AXI.CONFIG.HAS_WSTRB 1
M01_AXI.CONFIG.HAS_BRESP 1
M01_AXI.CONFIG.HAS_RRESP 1
M01_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M01_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M01_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M01_AXI.CONFIG.MAX_BURST_LENGTH 1
M01_AXI.CONFIG.PHASE 0.0
M01_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M01_AXI.CONFIG.NUM_READ_THREADS 1
M01_AXI.CONFIG.NUM_WRITE_THREADS 1
M01_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M01_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M01_AXI.CONFIG.INSERT_VIP 0
M02_AXI.CONFIG.DATA_WIDTH 32
M02_AXI.CONFIG.DATAWIDTH 32
M02_AXI.CONFIG.PROTOCOL AXI4LITE
M02_AXI.CONFIG.FREQ_HZ 100000000
M02_AXI.CONFIG.ID_WIDTH 0
M02_AXI.CONFIG.ADDR_WIDTH 13
M02_AXI.CONFIG.AWUSER_WIDTH 0
M02_AXI.CONFIG.ARUSER_WIDTH 0
M02_AXI.CONFIG.WUSER_WIDTH 0
M02_AXI.CONFIG.RUSER_WIDTH 0
M02_AXI.CONFIG.BUSER_WIDTH 0
M02_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M02_AXI.CONFIG.HAS_BURST 0
M02_AXI.CONFIG.HAS_LOCK 0
M02_AXI.CONFIG.HAS_PROT 1
M02_AXI.CONFIG.HAS_CACHE 0
M02_AXI.CONFIG.HAS_QOS 0
M02_AXI.CONFIG.HAS_REGION 0
M02_AXI.CONFIG.HAS_WSTRB 1
M02_AXI.CONFIG.HAS_BRESP 1
M02_AXI.CONFIG.HAS_RRESP 1
M02_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M02_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M02_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M02_AXI.CONFIG.MAX_BURST_LENGTH 1
M02_AXI.CONFIG.PHASE 0.0
M02_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M02_AXI.CONFIG.NUM_READ_THREADS 1
M02_AXI.CONFIG.NUM_WRITE_THREADS 1
M02_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M02_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M02_AXI.CONFIG.INSERT_VIP 0
M03_AXI.CONFIG.DATA_WIDTH 32
M03_AXI.CONFIG.DATAWIDTH 32
M03_AXI.CONFIG.PROTOCOL AXI4LITE
M03_AXI.CONFIG.FREQ_HZ 100000000
M03_AXI.CONFIG.ID_WIDTH 0
M03_AXI.CONFIG.ADDR_WIDTH 13
M03_AXI.CONFIG.AWUSER_WIDTH 0
M03_AXI.CONFIG.ARUSER_WIDTH 0
M03_AXI.CONFIG.WUSER_WIDTH 0
M03_AXI.CONFIG.RUSER_WIDTH 0
M03_AXI.CONFIG.BUSER_WIDTH 0
M03_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M03_AXI.CONFIG.HAS_BURST 0
M03_AXI.CONFIG.HAS_LOCK 0
M03_AXI.CONFIG.HAS_PROT 1
M03_AXI.CONFIG.HAS_CACHE 0
M03_AXI.CONFIG.HAS_QOS 0
M03_AXI.CONFIG.HAS_REGION 0
M03_AXI.CONFIG.HAS_WSTRB 1
M03_AXI.CONFIG.HAS_BRESP 1
M03_AXI.CONFIG.HAS_RRESP 1
M03_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M03_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M03_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M03_AXI.CONFIG.MAX_BURST_LENGTH 1
M03_AXI.CONFIG.PHASE 0.0
M03_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M03_AXI.CONFIG.NUM_READ_THREADS 1
M03_AXI.CONFIG.NUM_WRITE_THREADS 1
M03_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M03_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M03_AXI.CONFIG.INSERT_VIP 0
M04_AXI.CONFIG.DATA_WIDTH 32
M04_AXI.CONFIG.DATAWIDTH 32
M04_AXI.CONFIG.PROTOCOL AXI4LITE
M04_AXI.CONFIG.FREQ_HZ 100000000
M04_AXI.CONFIG.ID_WIDTH 0
M04_AXI.CONFIG.ADDR_WIDTH 9
M04_AXI.CONFIG.AWUSER_WIDTH 0
M04_AXI.CONFIG.ARUSER_WIDTH 0
M04_AXI.CONFIG.WUSER_WIDTH 0
M04_AXI.CONFIG.RUSER_WIDTH 0
M04_AXI.CONFIG.BUSER_WIDTH 0
M04_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M04_AXI.CONFIG.HAS_BURST 0
M04_AXI.CONFIG.HAS_LOCK 0
M04_AXI.CONFIG.HAS_PROT 0
M04_AXI.CONFIG.HAS_CACHE 0
M04_AXI.CONFIG.HAS_QOS 0
M04_AXI.CONFIG.HAS_REGION 0
M04_AXI.CONFIG.HAS_WSTRB 1
M04_AXI.CONFIG.HAS_BRESP 1
M04_AXI.CONFIG.HAS_RRESP 1
M04_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M04_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M04_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M04_AXI.CONFIG.MAX_BURST_LENGTH 1
M04_AXI.CONFIG.PHASE 0.0
M04_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M04_AXI.CONFIG.NUM_READ_THREADS 1
M04_AXI.CONFIG.NUM_WRITE_THREADS 1
M04_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M04_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M04_AXI.CONFIG.INSERT_VIP 0
M05_AXI.CONFIG.DATA_WIDTH 32
M05_AXI.CONFIG.DATAWIDTH 32
M05_AXI.CONFIG.PROTOCOL AXI4LITE
M05_AXI.CONFIG.FREQ_HZ 100000000
M05_AXI.CONFIG.ID_WIDTH 0
M05_AXI.CONFIG.ADDR_WIDTH 13
M05_AXI.CONFIG.AWUSER_WIDTH 0
M05_AXI.CONFIG.ARUSER_WIDTH 0
M05_AXI.CONFIG.WUSER_WIDTH 0
M05_AXI.CONFIG.RUSER_WIDTH 0
M05_AXI.CONFIG.BUSER_WIDTH 0
M05_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M05_AXI.CONFIG.HAS_BURST 0
M05_AXI.CONFIG.HAS_LOCK 0
M05_AXI.CONFIG.HAS_PROT 1
M05_AXI.CONFIG.HAS_CACHE 0
M05_AXI.CONFIG.HAS_QOS 0
M05_AXI.CONFIG.HAS_REGION 0
M05_AXI.CONFIG.HAS_WSTRB 1
M05_AXI.CONFIG.HAS_BRESP 1
M05_AXI.CONFIG.HAS_RRESP 1
M05_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M05_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M05_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M05_AXI.CONFIG.MAX_BURST_LENGTH 1
M05_AXI.CONFIG.PHASE 0.0
M05_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M05_AXI.CONFIG.NUM_READ_THREADS 1
M05_AXI.CONFIG.NUM_WRITE_THREADS 1
M05_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M05_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M05_AXI.CONFIG.INSERT_VIP 0
M06_AXI.CONFIG.DATA_WIDTH 32
M06_AXI.CONFIG.DATAWIDTH 32
M06_AXI.CONFIG.PROTOCOL AXI4LITE
M06_AXI.CONFIG.FREQ_HZ 100000000
M06_AXI.CONFIG.ID_WIDTH 0
M06_AXI.CONFIG.ADDR_WIDTH 10
M06_AXI.CONFIG.AWUSER_WIDTH 0
M06_AXI.CONFIG.ARUSER_WIDTH 0
M06_AXI.CONFIG.WUSER_WIDTH 0
M06_AXI.CONFIG.RUSER_WIDTH 0
M06_AXI.CONFIG.BUSER_WIDTH 0
M06_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M06_AXI.CONFIG.HAS_BURST 0
M06_AXI.CONFIG.HAS_LOCK 0
M06_AXI.CONFIG.HAS_PROT 0
M06_AXI.CONFIG.HAS_CACHE 0
M06_AXI.CONFIG.HAS_QOS 0
M06_AXI.CONFIG.HAS_REGION 0
M06_AXI.CONFIG.HAS_WSTRB 0
M06_AXI.CONFIG.HAS_BRESP 1
M06_AXI.CONFIG.HAS_RRESP 1
M06_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M06_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M06_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M06_AXI.CONFIG.MAX_BURST_LENGTH 1
M06_AXI.CONFIG.PHASE 0.0
M06_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M06_AXI.CONFIG.NUM_READ_THREADS 1
M06_AXI.CONFIG.NUM_WRITE_THREADS 1
M06_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M06_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M06_AXI.CONFIG.INSERT_VIP 0
M07_AXI.CONFIG.DATA_WIDTH 32
M07_AXI.CONFIG.DATAWIDTH 32
M07_AXI.CONFIG.PROTOCOL AXI4LITE
M07_AXI.CONFIG.FREQ_HZ 100000000
M07_AXI.CONFIG.ID_WIDTH 0
M07_AXI.CONFIG.ADDR_WIDTH 10
M07_AXI.CONFIG.AWUSER_WIDTH 0
M07_AXI.CONFIG.ARUSER_WIDTH 0
M07_AXI.CONFIG.WUSER_WIDTH 0
M07_AXI.CONFIG.RUSER_WIDTH 0
M07_AXI.CONFIG.BUSER_WIDTH 0
M07_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M07_AXI.CONFIG.HAS_BURST 0
M07_AXI.CONFIG.HAS_LOCK 0
M07_AXI.CONFIG.HAS_PROT 0
M07_AXI.CONFIG.HAS_CACHE 0
M07_AXI.CONFIG.HAS_QOS 0
M07_AXI.CONFIG.HAS_REGION 0
M07_AXI.CONFIG.HAS_WSTRB 0
M07_AXI.CONFIG.HAS_BRESP 1
M07_AXI.CONFIG.HAS_RRESP 1
M07_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M07_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M07_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M07_AXI.CONFIG.MAX_BURST_LENGTH 1
M07_AXI.CONFIG.PHASE 0.0
M07_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M07_AXI.CONFIG.NUM_READ_THREADS 1
M07_AXI.CONFIG.NUM_WRITE_THREADS 1
M07_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M07_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M07_AXI.CONFIG.INSERT_VIP 0
M08_AXI.CONFIG.DATA_WIDTH 32
M08_AXI.CONFIG.DATAWIDTH 32
M08_AXI.CONFIG.PROTOCOL AXI4LITE
M08_AXI.CONFIG.FREQ_HZ 100000000
M08_AXI.CONFIG.ID_WIDTH 0
M08_AXI.CONFIG.ADDR_WIDTH 10
M08_AXI.CONFIG.AWUSER_WIDTH 0
M08_AXI.CONFIG.ARUSER_WIDTH 0
M08_AXI.CONFIG.WUSER_WIDTH 0
M08_AXI.CONFIG.RUSER_WIDTH 0
M08_AXI.CONFIG.BUSER_WIDTH 0
M08_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M08_AXI.CONFIG.HAS_BURST 0
M08_AXI.CONFIG.HAS_LOCK 0
M08_AXI.CONFIG.HAS_PROT 0
M08_AXI.CONFIG.HAS_CACHE 0
M08_AXI.CONFIG.HAS_QOS 0
M08_AXI.CONFIG.HAS_REGION 0
M08_AXI.CONFIG.HAS_WSTRB 0
M08_AXI.CONFIG.HAS_BRESP 1
M08_AXI.CONFIG.HAS_RRESP 1
M08_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M08_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M08_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M08_AXI.CONFIG.MAX_BURST_LENGTH 1
M08_AXI.CONFIG.PHASE 0.0
M08_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M08_AXI.CONFIG.NUM_READ_THREADS 1
M08_AXI.CONFIG.NUM_WRITE_THREADS 1
M08_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M08_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M08_AXI.CONFIG.INSERT_VIP 0
M09_AXI.CONFIG.DATA_WIDTH 32
M09_AXI.CONFIG.DATAWIDTH 32
M09_AXI.CONFIG.PROTOCOL AXI4LITE
M09_AXI.CONFIG.FREQ_HZ 100000000
M09_AXI.CONFIG.ID_WIDTH 0
M09_AXI.CONFIG.ADDR_WIDTH 13
M09_AXI.CONFIG.AWUSER_WIDTH 0
M09_AXI.CONFIG.ARUSER_WIDTH 0
M09_AXI.CONFIG.WUSER_WIDTH 0
M09_AXI.CONFIG.RUSER_WIDTH 0
M09_AXI.CONFIG.BUSER_WIDTH 0
M09_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M09_AXI.CONFIG.HAS_BURST 0
M09_AXI.CONFIG.HAS_LOCK 0
M09_AXI.CONFIG.HAS_PROT 1
M09_AXI.CONFIG.HAS_CACHE 0
M09_AXI.CONFIG.HAS_QOS 0
M09_AXI.CONFIG.HAS_REGION 0
M09_AXI.CONFIG.HAS_WSTRB 1
M09_AXI.CONFIG.HAS_BRESP 1
M09_AXI.CONFIG.HAS_RRESP 1
M09_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M09_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M09_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M09_AXI.CONFIG.MAX_BURST_LENGTH 1
M09_AXI.CONFIG.PHASE 0.0
M09_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M09_AXI.CONFIG.NUM_READ_THREADS 1
M09_AXI.CONFIG.NUM_WRITE_THREADS 1
M09_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M09_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M09_AXI.CONFIG.INSERT_VIP 0
M10_AXI.CONFIG.DATA_WIDTH 32
M10_AXI.CONFIG.DATAWIDTH 32
M10_AXI.CONFIG.PROTOCOL AXI4LITE
M10_AXI.CONFIG.FREQ_HZ 100000000
M10_AXI.CONFIG.ID_WIDTH 0
M10_AXI.CONFIG.ADDR_WIDTH 9
M10_AXI.CONFIG.AWUSER_WIDTH 0
M10_AXI.CONFIG.ARUSER_WIDTH 0
M10_AXI.CONFIG.WUSER_WIDTH 0
M10_AXI.CONFIG.RUSER_WIDTH 0
M10_AXI.CONFIG.BUSER_WIDTH 0
M10_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M10_AXI.CONFIG.HAS_BURST 0
M10_AXI.CONFIG.HAS_LOCK 0
M10_AXI.CONFIG.HAS_PROT 0
M10_AXI.CONFIG.HAS_CACHE 0
M10_AXI.CONFIG.HAS_QOS 0
M10_AXI.CONFIG.HAS_REGION 0
M10_AXI.CONFIG.HAS_WSTRB 1
M10_AXI.CONFIG.HAS_BRESP 1
M10_AXI.CONFIG.HAS_RRESP 1
M10_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M10_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M10_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M10_AXI.CONFIG.MAX_BURST_LENGTH 1
M10_AXI.CONFIG.PHASE 0.0
M10_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M10_AXI.CONFIG.NUM_READ_THREADS 1
M10_AXI.CONFIG.NUM_WRITE_THREADS 1
M10_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M10_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M10_AXI.CONFIG.INSERT_VIP 0
M11_AXI.CONFIG.DATA_WIDTH 32
M11_AXI.CONFIG.DATAWIDTH 32
M11_AXI.CONFIG.PROTOCOL AXI4LITE
M11_AXI.CONFIG.FREQ_HZ 100000000
M11_AXI.CONFIG.ID_WIDTH 0
M11_AXI.CONFIG.ADDR_WIDTH 9
M11_AXI.CONFIG.AWUSER_WIDTH 0
M11_AXI.CONFIG.ARUSER_WIDTH 0
M11_AXI.CONFIG.WUSER_WIDTH 0
M11_AXI.CONFIG.RUSER_WIDTH 0
M11_AXI.CONFIG.BUSER_WIDTH 0
M11_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M11_AXI.CONFIG.HAS_BURST 0
M11_AXI.CONFIG.HAS_LOCK 0
M11_AXI.CONFIG.HAS_PROT 0
M11_AXI.CONFIG.HAS_CACHE 0
M11_AXI.CONFIG.HAS_QOS 0
M11_AXI.CONFIG.HAS_REGION 0
M11_AXI.CONFIG.HAS_WSTRB 1
M11_AXI.CONFIG.HAS_BRESP 1
M11_AXI.CONFIG.HAS_RRESP 1
M11_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M11_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M11_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M11_AXI.CONFIG.MAX_BURST_LENGTH 1
M11_AXI.CONFIG.PHASE 0.0
M11_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M11_AXI.CONFIG.NUM_READ_THREADS 1
M11_AXI.CONFIG.NUM_WRITE_THREADS 1
M11_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M11_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M11_AXI.CONFIG.INSERT_VIP 0
M12_AXI.CONFIG.DATA_WIDTH 32
M12_AXI.CONFIG.DATAWIDTH 32
M12_AXI.CONFIG.PROTOCOL AXI4LITE
M12_AXI.CONFIG.FREQ_HZ 100000000
M12_AXI.CONFIG.ID_WIDTH 0
M12_AXI.CONFIG.ADDR_WIDTH 9
M12_AXI.CONFIG.AWUSER_WIDTH 0
M12_AXI.CONFIG.ARUSER_WIDTH 0
M12_AXI.CONFIG.WUSER_WIDTH 0
M12_AXI.CONFIG.RUSER_WIDTH 0
M12_AXI.CONFIG.BUSER_WIDTH 0
M12_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M12_AXI.CONFIG.HAS_BURST 0
M12_AXI.CONFIG.HAS_LOCK 0
M12_AXI.CONFIG.HAS_PROT 0
M12_AXI.CONFIG.HAS_CACHE 0
M12_AXI.CONFIG.HAS_QOS 0
M12_AXI.CONFIG.HAS_REGION 0
M12_AXI.CONFIG.HAS_WSTRB 1
M12_AXI.CONFIG.HAS_BRESP 1
M12_AXI.CONFIG.HAS_RRESP 1
M12_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M12_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M12_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M12_AXI.CONFIG.MAX_BURST_LENGTH 1
M12_AXI.CONFIG.PHASE 0.0
M12_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M12_AXI.CONFIG.NUM_READ_THREADS 1
M12_AXI.CONFIG.NUM_WRITE_THREADS 1
M12_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M12_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M12_AXI.CONFIG.INSERT_VIP 0
M13_AXI.CONFIG.DATA_WIDTH 32
M13_AXI.CONFIG.DATAWIDTH 32
M13_AXI.CONFIG.PROTOCOL AXI4LITE
M13_AXI.CONFIG.FREQ_HZ 100000000
M13_AXI.CONFIG.ID_WIDTH 0
M13_AXI.CONFIG.ADDR_WIDTH 10
M13_AXI.CONFIG.AWUSER_WIDTH 0
M13_AXI.CONFIG.ARUSER_WIDTH 0
M13_AXI.CONFIG.WUSER_WIDTH 0
M13_AXI.CONFIG.RUSER_WIDTH 0
M13_AXI.CONFIG.BUSER_WIDTH 0
M13_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M13_AXI.CONFIG.HAS_BURST 0
M13_AXI.CONFIG.HAS_LOCK 0
M13_AXI.CONFIG.HAS_PROT 0
M13_AXI.CONFIG.HAS_CACHE 0
M13_AXI.CONFIG.HAS_QOS 0
M13_AXI.CONFIG.HAS_REGION 0
M13_AXI.CONFIG.HAS_WSTRB 0
M13_AXI.CONFIG.HAS_BRESP 1
M13_AXI.CONFIG.HAS_RRESP 1
M13_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M13_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M13_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M13_AXI.CONFIG.MAX_BURST_LENGTH 1
M13_AXI.CONFIG.PHASE 0.0
M13_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M13_AXI.CONFIG.NUM_READ_THREADS 1
M13_AXI.CONFIG.NUM_WRITE_THREADS 1
M13_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M13_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M13_AXI.CONFIG.INSERT_VIP 0
M14_AXI.CONFIG.DATA_WIDTH 32
M14_AXI.CONFIG.DATAWIDTH 32
M14_AXI.CONFIG.PROTOCOL AXI4LITE
M14_AXI.CONFIG.FREQ_HZ 100000000
M14_AXI.CONFIG.ID_WIDTH 0
M14_AXI.CONFIG.ADDR_WIDTH 7
M14_AXI.CONFIG.AWUSER_WIDTH 0
M14_AXI.CONFIG.ARUSER_WIDTH 0
M14_AXI.CONFIG.WUSER_WIDTH 0
M14_AXI.CONFIG.RUSER_WIDTH 0
M14_AXI.CONFIG.BUSER_WIDTH 0
M14_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M14_AXI.CONFIG.HAS_BURST 0
M14_AXI.CONFIG.HAS_LOCK 0
M14_AXI.CONFIG.HAS_PROT 0
M14_AXI.CONFIG.HAS_CACHE 0
M14_AXI.CONFIG.HAS_QOS 0
M14_AXI.CONFIG.HAS_REGION 0
M14_AXI.CONFIG.HAS_WSTRB 1
M14_AXI.CONFIG.HAS_BRESP 1
M14_AXI.CONFIG.HAS_RRESP 1
M14_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M14_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M14_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M14_AXI.CONFIG.MAX_BURST_LENGTH 1
M14_AXI.CONFIG.PHASE 0.0
M14_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M14_AXI.CONFIG.NUM_READ_THREADS 1
M14_AXI.CONFIG.NUM_WRITE_THREADS 1
M14_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M14_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M14_AXI.CONFIG.INSERT_VIP 0
M15_AXI.CONFIG.DATA_WIDTH 32
M15_AXI.CONFIG.DATAWIDTH 32
M15_AXI.CONFIG.PROTOCOL AXI4LITE
M15_AXI.CONFIG.FREQ_HZ 100000000
M15_AXI.CONFIG.ID_WIDTH 0
M15_AXI.CONFIG.ADDR_WIDTH 7
M15_AXI.CONFIG.AWUSER_WIDTH 0
M15_AXI.CONFIG.ARUSER_WIDTH 0
M15_AXI.CONFIG.WUSER_WIDTH 0
M15_AXI.CONFIG.RUSER_WIDTH 0
M15_AXI.CONFIG.BUSER_WIDTH 0
M15_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M15_AXI.CONFIG.HAS_BURST 0
M15_AXI.CONFIG.HAS_LOCK 0
M15_AXI.CONFIG.HAS_PROT 0
M15_AXI.CONFIG.HAS_CACHE 0
M15_AXI.CONFIG.HAS_QOS 0
M15_AXI.CONFIG.HAS_REGION 0
M15_AXI.CONFIG.HAS_WSTRB 1
M15_AXI.CONFIG.HAS_BRESP 1
M15_AXI.CONFIG.HAS_RRESP 1
M15_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M15_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M15_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M15_AXI.CONFIG.MAX_BURST_LENGTH 1
M15_AXI.CONFIG.PHASE 0.0
M15_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M15_AXI.CONFIG.NUM_READ_THREADS 1
M15_AXI.CONFIG.NUM_WRITE_THREADS 1
M15_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M15_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M15_AXI.CONFIG.INSERT_VIP 0
M16_AXI.CONFIG.DATA_WIDTH 32
M16_AXI.CONFIG.DATAWIDTH 32
M16_AXI.CONFIG.PROTOCOL AXI4LITE
M16_AXI.CONFIG.FREQ_HZ 100000000
M16_AXI.CONFIG.ID_WIDTH 0
M16_AXI.CONFIG.ADDR_WIDTH 9
M16_AXI.CONFIG.AWUSER_WIDTH 0
M16_AXI.CONFIG.ARUSER_WIDTH 0
M16_AXI.CONFIG.WUSER_WIDTH 0
M16_AXI.CONFIG.RUSER_WIDTH 0
M16_AXI.CONFIG.BUSER_WIDTH 0
M16_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M16_AXI.CONFIG.HAS_BURST 0
M16_AXI.CONFIG.HAS_LOCK 0
M16_AXI.CONFIG.HAS_PROT 0
M16_AXI.CONFIG.HAS_CACHE 0
M16_AXI.CONFIG.HAS_QOS 0
M16_AXI.CONFIG.HAS_REGION 0
M16_AXI.CONFIG.HAS_WSTRB 1
M16_AXI.CONFIG.HAS_BRESP 1
M16_AXI.CONFIG.HAS_RRESP 1
M16_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M16_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M16_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M16_AXI.CONFIG.MAX_BURST_LENGTH 1
M16_AXI.CONFIG.PHASE 0.0
M16_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M16_AXI.CONFIG.NUM_READ_THREADS 1
M16_AXI.CONFIG.NUM_WRITE_THREADS 1
M16_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M16_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M16_AXI.CONFIG.INSERT_VIP 0
M17_AXI.CONFIG.DATA_WIDTH 32
M17_AXI.CONFIG.DATAWIDTH 32
M17_AXI.CONFIG.PROTOCOL AXI4LITE
M17_AXI.CONFIG.FREQ_HZ 100000000
M17_AXI.CONFIG.ID_WIDTH 0
M17_AXI.CONFIG.ADDR_WIDTH 13
M17_AXI.CONFIG.AWUSER_WIDTH 0
M17_AXI.CONFIG.ARUSER_WIDTH 0
M17_AXI.CONFIG.WUSER_WIDTH 0
M17_AXI.CONFIG.RUSER_WIDTH 0
M17_AXI.CONFIG.BUSER_WIDTH 0
M17_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M17_AXI.CONFIG.HAS_BURST 0
M17_AXI.CONFIG.HAS_LOCK 0
M17_AXI.CONFIG.HAS_PROT 1
M17_AXI.CONFIG.HAS_CACHE 0
M17_AXI.CONFIG.HAS_QOS 0
M17_AXI.CONFIG.HAS_REGION 0
M17_AXI.CONFIG.HAS_WSTRB 1
M17_AXI.CONFIG.HAS_BRESP 1
M17_AXI.CONFIG.HAS_RRESP 1
M17_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M17_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M17_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M17_AXI.CONFIG.MAX_BURST_LENGTH 1
M17_AXI.CONFIG.PHASE 0.0
M17_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M17_AXI.CONFIG.NUM_READ_THREADS 1
M17_AXI.CONFIG.NUM_WRITE_THREADS 1
M17_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M17_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M17_AXI.CONFIG.INSERT_VIP 0
M18_AXI.CONFIG.DATA_WIDTH 32
M18_AXI.CONFIG.DATAWIDTH 32
M18_AXI.CONFIG.PROTOCOL AXI4LITE
M18_AXI.CONFIG.FREQ_HZ 100000000
M18_AXI.CONFIG.ID_WIDTH 0
M18_AXI.CONFIG.ADDR_WIDTH 13
M18_AXI.CONFIG.AWUSER_WIDTH 0
M18_AXI.CONFIG.ARUSER_WIDTH 0
M18_AXI.CONFIG.WUSER_WIDTH 0
M18_AXI.CONFIG.RUSER_WIDTH 0
M18_AXI.CONFIG.BUSER_WIDTH 0
M18_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M18_AXI.CONFIG.HAS_BURST 0
M18_AXI.CONFIG.HAS_LOCK 0
M18_AXI.CONFIG.HAS_PROT 1
M18_AXI.CONFIG.HAS_CACHE 0
M18_AXI.CONFIG.HAS_QOS 0
M18_AXI.CONFIG.HAS_REGION 0
M18_AXI.CONFIG.HAS_WSTRB 1
M18_AXI.CONFIG.HAS_BRESP 1
M18_AXI.CONFIG.HAS_RRESP 1
M18_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M18_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M18_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M18_AXI.CONFIG.MAX_BURST_LENGTH 1
M18_AXI.CONFIG.PHASE 0.0
M18_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M18_AXI.CONFIG.NUM_READ_THREADS 1
M18_AXI.CONFIG.NUM_WRITE_THREADS 1
M18_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M18_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M18_AXI.CONFIG.INSERT_VIP 0
M19_AXI.CONFIG.DATA_WIDTH 32
M19_AXI.CONFIG.DATAWIDTH 32
M19_AXI.CONFIG.PROTOCOL AXI4LITE
M19_AXI.CONFIG.FREQ_HZ 100000000
M19_AXI.CONFIG.ID_WIDTH 0
M19_AXI.CONFIG.ADDR_WIDTH 9
M19_AXI.CONFIG.AWUSER_WIDTH 0
M19_AXI.CONFIG.ARUSER_WIDTH 0
M19_AXI.CONFIG.WUSER_WIDTH 0
M19_AXI.CONFIG.RUSER_WIDTH 0
M19_AXI.CONFIG.BUSER_WIDTH 0
M19_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M19_AXI.CONFIG.HAS_BURST 0
M19_AXI.CONFIG.HAS_LOCK 0
M19_AXI.CONFIG.HAS_PROT 0
M19_AXI.CONFIG.HAS_CACHE 0
M19_AXI.CONFIG.HAS_QOS 0
M19_AXI.CONFIG.HAS_REGION 0
M19_AXI.CONFIG.HAS_WSTRB 1
M19_AXI.CONFIG.HAS_BRESP 1
M19_AXI.CONFIG.HAS_RRESP 1
M19_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M19_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M19_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M19_AXI.CONFIG.MAX_BURST_LENGTH 1
M19_AXI.CONFIG.PHASE 0.0
M19_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M19_AXI.CONFIG.NUM_READ_THREADS 1
M19_AXI.CONFIG.NUM_WRITE_THREADS 1
M19_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M19_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M19_AXI.CONFIG.INSERT_VIP 0
M20_AXI.CONFIG.DATA_WIDTH 32
M20_AXI.CONFIG.DATAWIDTH 32
M20_AXI.CONFIG.PROTOCOL AXI4LITE
M20_AXI.CONFIG.FREQ_HZ 100000000
M20_AXI.CONFIG.ID_WIDTH 0
M20_AXI.CONFIG.ADDR_WIDTH 13
M20_AXI.CONFIG.AWUSER_WIDTH 0
M20_AXI.CONFIG.ARUSER_WIDTH 0
M20_AXI.CONFIG.WUSER_WIDTH 0
M20_AXI.CONFIG.RUSER_WIDTH 0
M20_AXI.CONFIG.BUSER_WIDTH 0
M20_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M20_AXI.CONFIG.HAS_BURST 0
M20_AXI.CONFIG.HAS_LOCK 0
M20_AXI.CONFIG.HAS_PROT 1
M20_AXI.CONFIG.HAS_CACHE 0
M20_AXI.CONFIG.HAS_QOS 0
M20_AXI.CONFIG.HAS_REGION 0
M20_AXI.CONFIG.HAS_WSTRB 1
M20_AXI.CONFIG.HAS_BRESP 1
M20_AXI.CONFIG.HAS_RRESP 1
M20_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M20_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M20_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M20_AXI.CONFIG.MAX_BURST_LENGTH 1
M20_AXI.CONFIG.PHASE 0.0
M20_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M20_AXI.CONFIG.NUM_READ_THREADS 1
M20_AXI.CONFIG.NUM_WRITE_THREADS 1
M20_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M20_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M20_AXI.CONFIG.INSERT_VIP 0
M21_AXI.CONFIG.DATA_WIDTH 32
M21_AXI.CONFIG.DATAWIDTH 32
M21_AXI.CONFIG.PROTOCOL AXI4LITE
M21_AXI.CONFIG.FREQ_HZ 100000000
M21_AXI.CONFIG.ID_WIDTH 0
M21_AXI.CONFIG.ADDR_WIDTH 7
M21_AXI.CONFIG.AWUSER_WIDTH 0
M21_AXI.CONFIG.ARUSER_WIDTH 0
M21_AXI.CONFIG.WUSER_WIDTH 0
M21_AXI.CONFIG.RUSER_WIDTH 0
M21_AXI.CONFIG.BUSER_WIDTH 0
M21_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M21_AXI.CONFIG.HAS_BURST 0
M21_AXI.CONFIG.HAS_LOCK 0
M21_AXI.CONFIG.HAS_PROT 0
M21_AXI.CONFIG.HAS_CACHE 0
M21_AXI.CONFIG.HAS_QOS 0
M21_AXI.CONFIG.HAS_REGION 0
M21_AXI.CONFIG.HAS_WSTRB 1
M21_AXI.CONFIG.HAS_BRESP 1
M21_AXI.CONFIG.HAS_RRESP 1
M21_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M21_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M21_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M21_AXI.CONFIG.MAX_BURST_LENGTH 1
M21_AXI.CONFIG.PHASE 0.0
M21_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M21_AXI.CONFIG.NUM_READ_THREADS 1
M21_AXI.CONFIG.NUM_WRITE_THREADS 1
M21_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M21_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M21_AXI.CONFIG.INSERT_VIP 0
M00_AXI.IS_CASCADED 0
M01_AXI.IS_CASCADED 0
M02_AXI.IS_CASCADED 0
M03_AXI.IS_CASCADED 0
M04_AXI.IS_CASCADED 0
M05_AXI.IS_CASCADED 0
M06_AXI.IS_CASCADED 0
M07_AXI.IS_CASCADED 0
M08_AXI.IS_CASCADED 0
M09_AXI.IS_CASCADED 0
M10_AXI.IS_CASCADED 0
M11_AXI.IS_CASCADED 0
M12_AXI.IS_CASCADED 0
M13_AXI.IS_CASCADED 0
M14_AXI.IS_CASCADED 0
M15_AXI.IS_CASCADED 0
M16_AXI.IS_CASCADED 0
M17_AXI.IS_CASCADED 0
M18_AXI.IS_CASCADED 0
M19_AXI.IS_CASCADED 0
M20_AXI.IS_CASCADED 0
M21_AXI.IS_CASCADED 0
S00_AXI.IS_CASCADED 0
S00_AXI.NUM_SEG 22
S00_AXI.SEG000.BASE_ADDR 0x0000000040000000
S00_AXI.SEG000.SIZE 13
S00_AXI.SEG000.SUPPORTS_READ 1
S00_AXI.SEG000.SUPPORTS_WRITE 1
S00_AXI.SEG000.SECURE_READ 0
S00_AXI.SEG000.SECURE_WRITE 0
S00_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
S00_AXI.SEG000.PROTOCOL AXI4LITE
S00_AXI.SEG000.DATA_WIDTH 32
S00_AXI.SEG001.BASE_ADDR 0x0000000040400000
S00_AXI.SEG001.SIZE 16
S00_AXI.SEG001.SUPPORTS_READ 1
S00_AXI.SEG001.SUPPORTS_WRITE 1
S00_AXI.SEG001.SECURE_READ 0
S00_AXI.SEG001.SECURE_WRITE 0
S00_AXI.SEG001.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000111
S00_AXI.SEG001.PROTOCOL AXI4LITE
S00_AXI.SEG001.DATA_WIDTH 32
S00_AXI.SEG002.BASE_ADDR 0x0000000040410000
S00_AXI.SEG002.SIZE 16
S00_AXI.SEG002.SUPPORTS_READ 1
S00_AXI.SEG002.SUPPORTS_WRITE 1
S00_AXI.SEG002.SECURE_READ 0
S00_AXI.SEG002.SECURE_WRITE 0
S00_AXI.SEG002.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000110
S00_AXI.SEG002.PROTOCOL AXI4LITE
S00_AXI.SEG002.DATA_WIDTH 32
S00_AXI.SEG003.BASE_ADDR 0x0000000040420000
S00_AXI.SEG003.SIZE 16
S00_AXI.SEG003.SUPPORTS_READ 1
S00_AXI.SEG003.SUPPORTS_WRITE 1
S00_AXI.SEG003.SECURE_READ 0
S00_AXI.SEG003.SECURE_WRITE 0
S00_AXI.SEG003.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001000
S00_AXI.SEG003.PROTOCOL AXI4LITE
S00_AXI.SEG003.DATA_WIDTH 32
S00_AXI.SEG004.BASE_ADDR 0x0000000040430000
S00_AXI.SEG004.SIZE 16
S00_AXI.SEG004.SUPPORTS_READ 1
S00_AXI.SEG004.SUPPORTS_WRITE 1
S00_AXI.SEG004.SECURE_READ 0
S00_AXI.SEG004.SECURE_WRITE 0
S00_AXI.SEG004.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001101
S00_AXI.SEG004.PROTOCOL AXI4LITE
S00_AXI.SEG004.DATA_WIDTH 32
S00_AXI.SEG005.BASE_ADDR 0x0000000041200000
S00_AXI.SEG005.SIZE 16
S00_AXI.SEG005.SUPPORTS_READ 1
S00_AXI.SEG005.SUPPORTS_WRITE 1
S00_AXI.SEG005.SECURE_READ 0
S00_AXI.SEG005.SECURE_WRITE 0
S00_AXI.SEG005.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000001
S00_AXI.SEG005.PROTOCOL AXI4LITE
S00_AXI.SEG005.DATA_WIDTH 32
S00_AXI.SEG006.BASE_ADDR 0x0000000041210000
S00_AXI.SEG006.SIZE 16
S00_AXI.SEG006.SUPPORTS_READ 1
S00_AXI.SEG006.SUPPORTS_WRITE 1
S00_AXI.SEG006.SECURE_READ 0
S00_AXI.SEG006.SECURE_WRITE 0
S00_AXI.SEG006.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001010
S00_AXI.SEG006.PROTOCOL AXI4LITE
S00_AXI.SEG006.DATA_WIDTH 32
S00_AXI.SEG007.BASE_ADDR 0x0000000041220000
S00_AXI.SEG007.SIZE 16
S00_AXI.SEG007.SUPPORTS_READ 1
S00_AXI.SEG007.SUPPORTS_WRITE 1
S00_AXI.SEG007.SECURE_READ 0
S00_AXI.SEG007.SECURE_WRITE 0
S00_AXI.SEG007.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001011
S00_AXI.SEG007.PROTOCOL AXI4LITE
S00_AXI.SEG007.DATA_WIDTH 32
S00_AXI.SEG008.BASE_ADDR 0x0000000041230000
S00_AXI.SEG008.SIZE 16
S00_AXI.SEG008.SUPPORTS_READ 1
S00_AXI.SEG008.SUPPORTS_WRITE 1
S00_AXI.SEG008.SECURE_READ 0
S00_AXI.SEG008.SECURE_WRITE 0
S00_AXI.SEG008.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001100
S00_AXI.SEG008.PROTOCOL AXI4LITE
S00_AXI.SEG008.DATA_WIDTH 32
S00_AXI.SEG009.BASE_ADDR 0x0000000041240000
S00_AXI.SEG009.SIZE 16
S00_AXI.SEG009.SUPPORTS_READ 1
S00_AXI.SEG009.SUPPORTS_WRITE 1
S00_AXI.SEG009.SECURE_READ 0
S00_AXI.SEG009.SECURE_WRITE 0
S00_AXI.SEG009.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000010000
S00_AXI.SEG009.PROTOCOL AXI4LITE
S00_AXI.SEG009.DATA_WIDTH 32
S00_AXI.SEG010.BASE_ADDR 0x0000000041250000
S00_AXI.SEG010.SIZE 16
S00_AXI.SEG010.SUPPORTS_READ 1
S00_AXI.SEG010.SUPPORTS_WRITE 1
S00_AXI.SEG010.SECURE_READ 0
S00_AXI.SEG010.SECURE_WRITE 0
S00_AXI.SEG010.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000010011
S00_AXI.SEG010.PROTOCOL AXI4LITE
S00_AXI.SEG010.DATA_WIDTH 32
S00_AXI.SEG011.BASE_ADDR 0x0000000041260000
S00_AXI.SEG011.SIZE 16
S00_AXI.SEG011.SUPPORTS_READ 1
S00_AXI.SEG011.SUPPORTS_WRITE 1
S00_AXI.SEG011.SECURE_READ 0
S00_AXI.SEG011.SECURE_WRITE 0
S00_AXI.SEG011.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000100
S00_AXI.SEG011.PROTOCOL AXI4LITE
S00_AXI.SEG011.DATA_WIDTH 32
S00_AXI.SEG012.BASE_ADDR 0x0000000041E00000
S00_AXI.SEG012.SIZE 16
S00_AXI.SEG012.SUPPORTS_READ 1
S00_AXI.SEG012.SUPPORTS_WRITE 1
S00_AXI.SEG012.SECURE_READ 0
S00_AXI.SEG012.SECURE_WRITE 0
S00_AXI.SEG012.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001110
S00_AXI.SEG012.PROTOCOL AXI4LITE
S00_AXI.SEG012.DATA_WIDTH 32
S00_AXI.SEG013.BASE_ADDR 0x0000000041E10000
S00_AXI.SEG013.SIZE 16
S00_AXI.SEG013.SUPPORTS_READ 1
S00_AXI.SEG013.SUPPORTS_WRITE 1
S00_AXI.SEG013.SECURE_READ 0
S00_AXI.SEG013.SECURE_WRITE 0
S00_AXI.SEG013.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000010101
S00_AXI.SEG013.PROTOCOL AXI4LITE
S00_AXI.SEG013.DATA_WIDTH 32
S00_AXI.SEG014.BASE_ADDR 0x0000000041E20000
S00_AXI.SEG014.SIZE 16
S00_AXI.SEG014.SUPPORTS_READ 1
S00_AXI.SEG014.SUPPORTS_WRITE 1
S00_AXI.SEG014.SECURE_READ 0
S00_AXI.SEG014.SECURE_WRITE 0
S00_AXI.SEG014.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001111
S00_AXI.SEG014.PROTOCOL AXI4LITE
S00_AXI.SEG014.DATA_WIDTH 32
S00_AXI.SEG015.BASE_ADDR 0x0000000042000000
S00_AXI.SEG015.SIZE 13
S00_AXI.SEG015.SUPPORTS_READ 1
S00_AXI.SEG015.SUPPORTS_WRITE 1
S00_AXI.SEG015.SECURE_READ 0
S00_AXI.SEG015.SECURE_WRITE 0
S00_AXI.SEG015.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000010
S00_AXI.SEG015.PROTOCOL AXI4LITE
S00_AXI.SEG015.DATA_WIDTH 32
S00_AXI.SEG016.BASE_ADDR 0x0000000044000000
S00_AXI.SEG016.SIZE 13
S00_AXI.SEG016.SUPPORTS_READ 1
S00_AXI.SEG016.SUPPORTS_WRITE 1
S00_AXI.SEG016.SECURE_READ 0
S00_AXI.SEG016.SECURE_WRITE 0
S00_AXI.SEG016.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000011
S00_AXI.SEG016.PROTOCOL AXI4LITE
S00_AXI.SEG016.DATA_WIDTH 32
S00_AXI.SEG017.BASE_ADDR 0x0000000046000000
S00_AXI.SEG017.SIZE 13
S00_AXI.SEG017.SUPPORTS_READ 1
S00_AXI.SEG017.SUPPORTS_WRITE 1
S00_AXI.SEG017.SECURE_READ 0
S00_AXI.SEG017.SECURE_WRITE 0
S00_AXI.SEG017.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000101
S00_AXI.SEG017.PROTOCOL AXI4LITE
S00_AXI.SEG017.DATA_WIDTH 32
S00_AXI.SEG018.BASE_ADDR 0x0000000048000000
S00_AXI.SEG018.SIZE 13
S00_AXI.SEG018.SUPPORTS_READ 1
S00_AXI.SEG018.SUPPORTS_WRITE 1
S00_AXI.SEG018.SECURE_READ 0
S00_AXI.SEG018.SECURE_WRITE 0
S00_AXI.SEG018.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001001
S00_AXI.SEG018.PROTOCOL AXI4LITE
S00_AXI.SEG018.DATA_WIDTH 32
S00_AXI.SEG019.BASE_ADDR 0x000000004A000000
S00_AXI.SEG019.SIZE 13
S00_AXI.SEG019.SUPPORTS_READ 1
S00_AXI.SEG019.SUPPORTS_WRITE 1
S00_AXI.SEG019.SECURE_READ 0
S00_AXI.SEG019.SECURE_WRITE 0
S00_AXI.SEG019.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000010001
S00_AXI.SEG019.PROTOCOL AXI4LITE
S00_AXI.SEG019.DATA_WIDTH 32
S00_AXI.SEG020.BASE_ADDR 0x000000004C000000
S00_AXI.SEG020.SIZE 13
S00_AXI.SEG020.SUPPORTS_READ 1
S00_AXI.SEG020.SUPPORTS_WRITE 1
S00_AXI.SEG020.SECURE_READ 0
S00_AXI.SEG020.SECURE_WRITE 0
S00_AXI.SEG020.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000010010
S00_AXI.SEG020.PROTOCOL AXI4LITE
S00_AXI.SEG020.DATA_WIDTH 32
S00_AXI.SEG021.BASE_ADDR 0x000000004E000000
S00_AXI.SEG021.SIZE 13
S00_AXI.SEG021.SUPPORTS_READ 1
S00_AXI.SEG021.SUPPORTS_WRITE 1
S00_AXI.SEG021.SECURE_READ 0
S00_AXI.SEG021.SECURE_WRITE 0
S00_AXI.SEG021.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000010100
S00_AXI.SEG021.PROTOCOL AXI4LITE
S00_AXI.SEG021.DATA_WIDTH 32
c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_smartconnect_0_0.mem
+208
View File
@@ -0,0 +1,208 @@
NUM_SI 4
NUM_MI 1
NUM_CLKS 1
S00_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
S00_AXI.CONFIG.NUM_READ_OUTSTANDING 16
S00_AXI.CONFIG.DATA_WIDTH 32
S00_AXI.CONFIG.DATAWIDTH 32
S00_AXI.CONFIG.PROTOCOL AXI4
S00_AXI.CONFIG.FREQ_HZ 100000000
S00_AXI.CONFIG.ID_WIDTH 0
S00_AXI.CONFIG.ADDR_WIDTH 32
S00_AXI.CONFIG.AWUSER_WIDTH 0
S00_AXI.CONFIG.ARUSER_WIDTH 0
S00_AXI.CONFIG.WUSER_WIDTH 0
S00_AXI.CONFIG.RUSER_WIDTH 0
S00_AXI.CONFIG.BUSER_WIDTH 0
S00_AXI.CONFIG.READ_WRITE_MODE READ_ONLY
S00_AXI.CONFIG.HAS_BURST 0
S00_AXI.CONFIG.HAS_LOCK 0
S00_AXI.CONFIG.HAS_PROT 1
S00_AXI.CONFIG.HAS_CACHE 1
S00_AXI.CONFIG.HAS_QOS 0
S00_AXI.CONFIG.HAS_REGION 0
S00_AXI.CONFIG.HAS_WSTRB 0
S00_AXI.CONFIG.HAS_BRESP 0
S00_AXI.CONFIG.HAS_RRESP 1
S00_AXI.CONFIG.NUM_WRITE_OUTSTANDING 2
S00_AXI.CONFIG.MAX_BURST_LENGTH 128
S00_AXI.CONFIG.PHASE 0.0
S00_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
S00_AXI.CONFIG.NUM_READ_THREADS 1
S00_AXI.CONFIG.NUM_WRITE_THREADS 1
S00_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
S00_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
S00_AXI.CONFIG.INSERT_VIP 0
S01_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
S01_AXI.CONFIG.NUM_WRITE_OUTSTANDING 16
S01_AXI.CONFIG.DATA_WIDTH 32
S01_AXI.CONFIG.DATAWIDTH 32
S01_AXI.CONFIG.PROTOCOL AXI4
S01_AXI.CONFIG.FREQ_HZ 100000000
S01_AXI.CONFIG.ID_WIDTH 0
S01_AXI.CONFIG.ADDR_WIDTH 32
S01_AXI.CONFIG.AWUSER_WIDTH 0
S01_AXI.CONFIG.ARUSER_WIDTH 0
S01_AXI.CONFIG.WUSER_WIDTH 0
S01_AXI.CONFIG.RUSER_WIDTH 0
S01_AXI.CONFIG.BUSER_WIDTH 0
S01_AXI.CONFIG.READ_WRITE_MODE WRITE_ONLY
S01_AXI.CONFIG.HAS_BURST 0
S01_AXI.CONFIG.HAS_LOCK 0
S01_AXI.CONFIG.HAS_PROT 1
S01_AXI.CONFIG.HAS_CACHE 1
S01_AXI.CONFIG.HAS_QOS 0
S01_AXI.CONFIG.HAS_REGION 0
S01_AXI.CONFIG.HAS_WSTRB 1
S01_AXI.CONFIG.HAS_BRESP 1
S01_AXI.CONFIG.HAS_RRESP 0
S01_AXI.CONFIG.NUM_READ_OUTSTANDING 2
S01_AXI.CONFIG.MAX_BURST_LENGTH 128
S01_AXI.CONFIG.PHASE 0.0
S01_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
S01_AXI.CONFIG.NUM_READ_THREADS 1
S01_AXI.CONFIG.NUM_WRITE_THREADS 1
S01_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
S01_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
S01_AXI.CONFIG.INSERT_VIP 0
S02_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
S02_AXI.CONFIG.NUM_WRITE_OUTSTANDING 16
S02_AXI.CONFIG.DATA_WIDTH 32
S02_AXI.CONFIG.DATAWIDTH 32
S02_AXI.CONFIG.PROTOCOL AXI4
S02_AXI.CONFIG.FREQ_HZ 100000000
S02_AXI.CONFIG.ID_WIDTH 0
S02_AXI.CONFIG.ADDR_WIDTH 32
S02_AXI.CONFIG.AWUSER_WIDTH 0
S02_AXI.CONFIG.ARUSER_WIDTH 0
S02_AXI.CONFIG.WUSER_WIDTH 0
S02_AXI.CONFIG.RUSER_WIDTH 0
S02_AXI.CONFIG.BUSER_WIDTH 0
S02_AXI.CONFIG.READ_WRITE_MODE WRITE_ONLY
S02_AXI.CONFIG.HAS_BURST 0
S02_AXI.CONFIG.HAS_LOCK 0
S02_AXI.CONFIG.HAS_PROT 1
S02_AXI.CONFIG.HAS_CACHE 1
S02_AXI.CONFIG.HAS_QOS 0
S02_AXI.CONFIG.HAS_REGION 0
S02_AXI.CONFIG.HAS_WSTRB 1
S02_AXI.CONFIG.HAS_BRESP 1
S02_AXI.CONFIG.HAS_RRESP 0
S02_AXI.CONFIG.NUM_READ_OUTSTANDING 2
S02_AXI.CONFIG.MAX_BURST_LENGTH 128
S02_AXI.CONFIG.PHASE 0.0
S02_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
S02_AXI.CONFIG.NUM_READ_THREADS 1
S02_AXI.CONFIG.NUM_WRITE_THREADS 1
S02_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
S02_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
S02_AXI.CONFIG.INSERT_VIP 0
S03_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
S03_AXI.CONFIG.NUM_WRITE_OUTSTANDING 16
S03_AXI.CONFIG.DATA_WIDTH 32
S03_AXI.CONFIG.DATAWIDTH 32
S03_AXI.CONFIG.PROTOCOL AXI4
S03_AXI.CONFIG.FREQ_HZ 100000000
S03_AXI.CONFIG.ID_WIDTH 0
S03_AXI.CONFIG.ADDR_WIDTH 32
S03_AXI.CONFIG.AWUSER_WIDTH 0
S03_AXI.CONFIG.ARUSER_WIDTH 0
S03_AXI.CONFIG.WUSER_WIDTH 0
S03_AXI.CONFIG.RUSER_WIDTH 0
S03_AXI.CONFIG.BUSER_WIDTH 0
S03_AXI.CONFIG.READ_WRITE_MODE WRITE_ONLY
S03_AXI.CONFIG.HAS_BURST 0
S03_AXI.CONFIG.HAS_LOCK 0
S03_AXI.CONFIG.HAS_PROT 1
S03_AXI.CONFIG.HAS_CACHE 1
S03_AXI.CONFIG.HAS_QOS 0
S03_AXI.CONFIG.HAS_REGION 0
S03_AXI.CONFIG.HAS_WSTRB 1
S03_AXI.CONFIG.HAS_BRESP 1
S03_AXI.CONFIG.HAS_RRESP 0
S03_AXI.CONFIG.NUM_READ_OUTSTANDING 2
S03_AXI.CONFIG.MAX_BURST_LENGTH 128
S03_AXI.CONFIG.PHASE 0.0
S03_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
S03_AXI.CONFIG.NUM_READ_THREADS 1
S03_AXI.CONFIG.NUM_WRITE_THREADS 1
S03_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
S03_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
S03_AXI.CONFIG.INSERT_VIP 0
M00_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M00_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M00_AXI.CONFIG.DATA_WIDTH 32
M00_AXI.CONFIG.DATAWIDTH 32
M00_AXI.CONFIG.PROTOCOL AXI3
M00_AXI.CONFIG.FREQ_HZ 100000000
M00_AXI.CONFIG.ID_WIDTH 6
M00_AXI.CONFIG.ADDR_WIDTH 32
M00_AXI.CONFIG.AWUSER_WIDTH 0
M00_AXI.CONFIG.ARUSER_WIDTH 0
M00_AXI.CONFIG.WUSER_WIDTH 0
M00_AXI.CONFIG.RUSER_WIDTH 0
M00_AXI.CONFIG.BUSER_WIDTH 0
M00_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M00_AXI.CONFIG.HAS_BURST 1
M00_AXI.CONFIG.HAS_LOCK 1
M00_AXI.CONFIG.HAS_PROT 1
M00_AXI.CONFIG.HAS_CACHE 1
M00_AXI.CONFIG.HAS_QOS 1
M00_AXI.CONFIG.HAS_REGION 0
M00_AXI.CONFIG.HAS_WSTRB 1
M00_AXI.CONFIG.HAS_BRESP 1
M00_AXI.CONFIG.HAS_RRESP 1
M00_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M00_AXI.CONFIG.MAX_BURST_LENGTH 16
M00_AXI.CONFIG.PHASE 0.0
M00_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
M00_AXI.CONFIG.NUM_READ_THREADS 1
M00_AXI.CONFIG.NUM_WRITE_THREADS 1
M00_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M00_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M00_AXI.CONFIG.INSERT_VIP 0
M00_AXI.IS_CASCADED 0
S00_AXI.IS_CASCADED 0
S01_AXI.IS_CASCADED 0
S02_AXI.IS_CASCADED 0
S03_AXI.IS_CASCADED 0
S00_AXI.NUM_SEG 1
S00_AXI.SEG000.BASE_ADDR 0x0000000000000000
S00_AXI.SEG000.SIZE 29
S00_AXI.SEG000.SUPPORTS_READ 1
S00_AXI.SEG000.SUPPORTS_WRITE 1
S00_AXI.SEG000.SECURE_READ 0
S00_AXI.SEG000.SECURE_WRITE 0
S00_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
S00_AXI.SEG000.PROTOCOL AXI3
S00_AXI.SEG000.DATA_WIDTH 32
S01_AXI.NUM_SEG 1
S01_AXI.SEG000.BASE_ADDR 0x0000000000000000
S01_AXI.SEG000.SIZE 29
S01_AXI.SEG000.SUPPORTS_READ 1
S01_AXI.SEG000.SUPPORTS_WRITE 1
S01_AXI.SEG000.SECURE_READ 0
S01_AXI.SEG000.SECURE_WRITE 0
S01_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
S01_AXI.SEG000.PROTOCOL AXI3
S01_AXI.SEG000.DATA_WIDTH 32
S02_AXI.NUM_SEG 1
S02_AXI.SEG000.BASE_ADDR 0x0000000000000000
S02_AXI.SEG000.SIZE 29
S02_AXI.SEG000.SUPPORTS_READ 1
S02_AXI.SEG000.SUPPORTS_WRITE 1
S02_AXI.SEG000.SECURE_READ 0
S02_AXI.SEG000.SECURE_WRITE 0
S02_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
S02_AXI.SEG000.PROTOCOL AXI3
S02_AXI.SEG000.DATA_WIDTH 32
S03_AXI.NUM_SEG 1
S03_AXI.SEG000.BASE_ADDR 0x0000000000000000
S03_AXI.SEG000.SIZE 29
S03_AXI.SEG000.SUPPORTS_READ 1
S03_AXI.SEG000.SUPPORTS_WRITE 1
S03_AXI.SEG000.SECURE_READ 0
S03_AXI.SEG000.SECURE_WRITE 0
S03_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
S03_AXI.SEG000.PROTOCOL AXI3
S03_AXI.SEG000.DATA_WIDTH 32
c64_pro.sim/sim_1/behav/xsim/simulate.bat
+25
View File
@@ -0,0 +1,25 @@
@echo off
REM ****************************************************************************
REM Vivado (TM) v2023.1 (64-bit)
REM
REM Filename : simulate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for simulating the design by launching the simulator
REM
REM Generated by Vivado on Thu Sep 03 09:57:19 +0800 2026
REM SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
REM
REM IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
REM
REM usage: simulate.bat
REM
REM ****************************************************************************
REM simulate design
echo "xsim pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch pl_top_tb.tcl -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg -log simulate.log"
call xsim pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch pl_top_tb.tcl -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg -log simulate.log
if "%errorlevel%"=="0" goto SUCCESS
if "%errorlevel%"=="1" goto END
:END
exit 1
:SUCCESS
exit 0
c64_pro.sim/sim_1/behav/xsim/simulate.log
+79
View File
@@ -0,0 +1,79 @@
Time resolution is 1 ps
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
INFO: xsimkernel Simulation Memory Usage: 30840 KB (Peak: 30840 KB), Simulation CPU Usage: 211702 ms
c64_pro.sim/sim_1/behav/xsim/xelab.pb
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c64_pro.sim/sim_1/behav/xsim/xsim.dir/pl_top_tb_behav/Compile_Options.txt
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--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "axi_infrastructure_v1_1_0" -L "axi_vip_v1_1_14" -L "processing_system7_vip_v1_0_16" -L "axis_infrastructure_v1_1_0" -L "axis_data_fifo_v2_0_10" -L "fifo_generator_v13_2_8" -L "axi_lite_ipif_v3_0_4" -L "lib_cdc_v1_0_2" -L "interrupt_control_v3_1_4" -L "axi_gpio_v2_0_30" -L "dist_mem_gen_v8_0_13" -L "lib_pkg_v1_0_2" -L "lib_srl_fifo_v1_0_2" -L "lib_fifo_v1_0_17" -L "axi_quad_spi_v3_2_27" -L "axi_datamover_v5_1_30" -L "axi_sg_v4_1_16" -L "axi_dma_v7_1_29" -L "axi_bram_ctrl_v4_1_8" -L "xlconstant_v1_1_7" -L "proc_sys_reset_v5_0_13" -L "smartconnect_v1_0" -L "axi_register_slice_v2_1_28" -L "xlconcat_v2_1_4" -L "uvm" -L "xilinx_vip" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "pl_top_tb_behav" "xil_defaultlib.pl_top_tb" "xil_defaultlib.glbl" -log "elaborate.log"
c64_pro.sim/sim_1/behav/xsim/xsim.dir/pl_top_tb_behav/TempBreakPointFile.txt
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Breakpoint File Version 1.0
c64_pro.sim/sim_1/behav/xsim/xsim.dir/pl_top_tb_behav/obj/xsim_0.win64.obj
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