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"csi040_ctrl_tb" -snapshot "csi040_ctrl_tb_sim"
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Breakpoint File Version 1.0
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[General]
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ARRAY_DISPLAY_LIMIT=512
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RADIX=hex
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TIME_UNIT=ns
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TRACE_LIMIT=2147483647
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VHDL_ENTITY_SCOPE_FILTER=true
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VHDL_PACKAGE_SCOPE_FILTER=false
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VHDL_BLOCK_SCOPE_FILTER=true
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VHDL_PROCESS_SCOPE_FILTER=false
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VHDL_PROCEDURE_SCOPE_FILTER=false
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VERILOG_MODULE_SCOPE_FILTER=true
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VERILOG_PACKAGE_SCOPE_FILTER=false
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VERILOG_BLOCK_SCOPE_FILTER=false
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VERILOG_TASK_SCOPE_FILTER=false
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VERILOG_PROCESS_SCOPE_FILTER=false
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INPUT_OBJECT_FILTER=true
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OUTPUT_OBJECT_FILTER=true
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INOUT_OBJECT_FILTER=true
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INTERNAL_OBJECT_FILTER=true
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CONSTANT_OBJECT_FILTER=true
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VARIABLE_OBJECT_FILTER=true
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INPUT_PROTOINST_FILTER=true
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OUTPUT_PROTOINST_FILTER=true
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INOUT_PROTOINST_FILTER=true
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INTERNAL_PROTOINST_FILTER=true
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CONSTANT_PROTOINST_FILTER=true
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VARIABLE_PROTOINST_FILTER=true
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SCOPE_NAME_COLUMN_WIDTH=136
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SCOPE_DESIGN_UNIT_COLUMN_WIDTH=96
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SCOPE_BLOCK_TYPE_COLUMN_WIDTH=100
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OBJECT_NAME_COLUMN_WIDTH=162
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OBJECT_VALUE_COLUMN_WIDTH=75
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OBJECT_DATA_TYPE_COLUMN_WIDTH=73
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PROCESS_NAME_COLUMN_WIDTH=75
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PROCESS_TYPE_COLUMN_WIDTH=75
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FRAME_INDEX_COLUMN_WIDTH=75
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FRAME_NAME_COLUMN_WIDTH=75
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FRAME_FILE_NAME_COLUMN_WIDTH=75
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FRAME_LINE_NUM_COLUMN_WIDTH=75
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LOCAL_NAME_COLUMN_WIDTH=75
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LOCAL_VALUE_COLUMN_WIDTH=75
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LOCAL_DATA_TYPE_COLUMN_WIDTH=0
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PROTO_NAME_COLUMN_WIDTH=0
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PROTO_VALUE_COLUMN_WIDTH=0
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INPUT_LOCAL_FILTER=1
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OUTPUT_LOCAL_FILTER=1
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INOUT_LOCAL_FILTER=1
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INTERNAL_LOCAL_FILTER=1
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CONSTANT_LOCAL_FILTER=1
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VARIABLE_LOCAL_FILTER=1
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set_param project.enableReportConfiguration 0
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load_feature core
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current_fileset
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xsim {csi040_ctrl_tb_sim} -autoloadwcfg
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Running: xsim.dir/csi040_ctrl_tb_sim/xsimk.exe -simmode gui -wdb csi040_ctrl_tb_sim.wdb -simrunnum 0 -socket 60790
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Design successfully loaded
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Design Loading Memory Usage: 9520 KB (Peak: 9520 KB)
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Design Loading CPU Usage: 30 ms
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Simulation completed
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Simulation Memory Usage: 9916 KB (Peak: 9916 KB)
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Simulation CPU Usage: 108 ms
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