sync chunk 11/12

xsim.dir/csi040_ctrl_tb_sim/Compile_Options.txt

@@ -0,0 +1 @@
+"csi040_ctrl_tb" -snapshot "csi040_ctrl_tb_sim" 

xsim.dir/csi040_ctrl_tb_sim/TempBreakPointFile.txt

@@ -0,0 +1 @@
+Breakpoint File Version 1.0

xsim.dir/csi040_ctrl_tb_sim/xsimSettings.ini

@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=136
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=96
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=100
+OBJECT_NAME_COLUMN_WIDTH=162
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=73
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1

xsim.dir/csi040_ctrl_tb_sim/xsim_script.tcl

@@ -0,0 +1,4 @@
+set_param project.enableReportConfiguration 0
+load_feature core
+current_fileset
+xsim {csi040_ctrl_tb_sim} -autoloadwcfg

xsim.dir/csi040_ctrl_tb_sim/xsimkernel.log

@@ -0,0 +1,7 @@
+Running: xsim.dir/csi040_ctrl_tb_sim/xsimk.exe -simmode gui -wdb csi040_ctrl_tb_sim.wdb -simrunnum 0 -socket 60790
+Design successfully loaded
+Design Loading Memory Usage: 9520 KB (Peak: 9520 KB)
+Design Loading CPU Usage: 30 ms
+Simulation completed
+Simulation Memory Usage: 9916 KB (Peak: 9916 KB)
+Simulation CPU Usage: 108 ms

xsim.dir/csi040_ctrl_tb_sim_cn_comments/Compile_Options.txt

@@ -0,0 +1 @@
+"csi040_ctrl_tb" -debug "typical" -snapshot "csi040_ctrl_tb_sim_cn_comments" 

xsim.dir/csi040_ctrl_tb_sim_cn_comments/xsimSettings.ini

@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=0
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=0
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=0
+OBJECT_NAME_COLUMN_WIDTH=0
+OBJECT_VALUE_COLUMN_WIDTH=0
+OBJECT_DATA_TYPE_COLUMN_WIDTH=0
+PROCESS_NAME_COLUMN_WIDTH=0
+PROCESS_TYPE_COLUMN_WIDTH=0
+FRAME_INDEX_COLUMN_WIDTH=0
+FRAME_NAME_COLUMN_WIDTH=0
+FRAME_FILE_NAME_COLUMN_WIDTH=0
+FRAME_LINE_NUM_COLUMN_WIDTH=0
+LOCAL_NAME_COLUMN_WIDTH=0
+LOCAL_VALUE_COLUMN_WIDTH=0
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1

xsim.dir/csi040_ctrl_tb_sim_cn_comments/xsim_script.tcl

@@ -0,0 +1 @@
+xsim {csi040_ctrl_tb_sim_cn_comments} -autoloadwcfg -runall

xsim.dir/csi040_ctrl_tb_sim_cn_comments/xsimkernel.log

@@ -0,0 +1,7 @@
+Running: xsim.dir/csi040_ctrl_tb_sim_cn_comments/xsimk.exe -runall -simmode gui -wdb csi040_ctrl_tb_sim_cn_comments.wdb -simrunnum 0 -socket 61897
+Design successfully loaded
+Design Loading Memory Usage: 10668 KB (Peak: 10668 KB)
+Design Loading CPU Usage: 31 ms
+Simulation completed
+Simulation Memory Usage: 11324 KB (Peak: 11324 KB)
+Simulation CPU Usage: 31 ms

xsim.dir/csi040_ctrl_tb_sim_comments/Compile_Options.txt

@@ -0,0 +1 @@
+"csi040_ctrl_tb" -debug "typical" -snapshot "csi040_ctrl_tb_sim_comments" 

xsim.dir/csi040_ctrl_tb_sim_comments/xsimSettings.ini

@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=0
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=0
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=0
+OBJECT_NAME_COLUMN_WIDTH=0
+OBJECT_VALUE_COLUMN_WIDTH=0
+OBJECT_DATA_TYPE_COLUMN_WIDTH=0
+PROCESS_NAME_COLUMN_WIDTH=0
+PROCESS_TYPE_COLUMN_WIDTH=0
+FRAME_INDEX_COLUMN_WIDTH=0
+FRAME_NAME_COLUMN_WIDTH=0
+FRAME_FILE_NAME_COLUMN_WIDTH=0
+FRAME_LINE_NUM_COLUMN_WIDTH=0
+LOCAL_NAME_COLUMN_WIDTH=0
+LOCAL_VALUE_COLUMN_WIDTH=0
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1

xsim.dir/csi040_ctrl_tb_sim_comments/xsim_script.tcl

@@ -0,0 +1 @@
+xsim {csi040_ctrl_tb_sim_comments} -autoloadwcfg -runall

xsim.dir/csi040_ctrl_tb_sim_comments/xsimkernel.log

@@ -0,0 +1,7 @@
+Running: xsim.dir/csi040_ctrl_tb_sim_comments/xsimk.exe -runall -simmode gui -wdb csi040_ctrl_tb_sim_comments.wdb -simrunnum 0 -socket 49208
+Design successfully loaded
+Design Loading Memory Usage: 10636 KB (Peak: 10636 KB)
+Design Loading CPU Usage: 15 ms
+Simulation completed
+Simulation Memory Usage: 11304 KB (Peak: 11304 KB)
+Simulation CPU Usage: 15 ms

xsim.dir/csi040_ctrl_tb_sim_dbg/Compile_Options.txt

@@ -0,0 +1 @@
+"csi040_ctrl_tb" -debug "typical" -snapshot "csi040_ctrl_tb_sim_dbg" 

xsim.dir/csi040_ctrl_tb_sim_dbg/TempBreakPointFile.txt

@@ -0,0 +1 @@
+Breakpoint File Version 1.0

xsim.dir/csi040_ctrl_tb_sim_dbg/xsimSettings.ini

@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=150
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=96
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=100
+OBJECT_NAME_COLUMN_WIDTH=162
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=73
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1

xsim.dir/csi040_ctrl_tb_sim_dbg/xsim_script.tcl

@@ -0,0 +1,4 @@
+set_param project.enableReportConfiguration 0
+load_feature core
+current_fileset
+xsim {csi040_ctrl_tb_sim_dbg} -autoloadwcfg

xsim.dir/csi040_ctrl_tb_sim_dbg/xsimkernel.log

@@ -0,0 +1,7 @@
+Running: xsim.dir/csi040_ctrl_tb_sim_dbg/xsimk.exe -simmode gui -wdb csi040_ctrl_tb_sim_dbg.wdb -simrunnum 0 -socket 56128
+Design successfully loaded
+Design Loading Memory Usage: 10692 KB (Peak: 10692 KB)
+Design Loading CPU Usage: 31 ms
+Simulation completed
+Simulation Memory Usage: 11648 KB (Peak: 11648 KB)
+Simulation CPU Usage: 108 ms

xsim.dir/work/work.rlx

@@ -0,0 +1,7 @@
+0.7
+2020.2
+May  7 2023
+15:24:31
+D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.srcs/sources_1/rtl/csi040/csi040_ctrl.v,1782134155,verilog,,D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.srcs/sources_1/rtl/csi040/csi040_ctrl_tb.v,,csi040_ctrl,,,,,,,,
+D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.srcs/sources_1/rtl/csi040/csi040_ctrl_tb.v,1782134400,verilog,,,,csi040_ctrl_tb,,,,,,,,
+D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.srcs/sources_1/rtl/csi040/csi040_spi_master.v,1782823105,verilog,,D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.srcs/sources_1/rtl/csi040/csi040_ctrl.v,,csi040_spi_master,,,,,,,,

xsim.dir/xil_defaultlib/xil_defaultlib.rlx

@@ -0,0 +1,7 @@
+0.7
+2020.2
+May  7 2023
+15:24:31
+D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.srcs/sources_1/rtl/csi040/csi040_ctrl.v,1782134155,verilog,,D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.srcs/sources_1/rtl/csi040/csi040_ctrl_tb.v,,csi040_ctrl,,,,,,,,
+D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.srcs/sources_1/rtl/csi040/csi040_ctrl_tb.v,1782134400,verilog,,,,csi040_ctrl_tb,,,,,,,,
+D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.srcs/sources_1/rtl/csi040/csi040_spi_master.v,1782133390,verilog,,D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.srcs/sources_1/rtl/csi040/csi040_ctrl.v,,csi040_spi_master,,,,,,,,