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chunk-sync
2026-09-11 16:18:36 +08:00
parent c315cef09e
commit c2c1bb2648
922 changed files with 102283 additions and 6793 deletions
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c64_pro.srcs/sources_1/rtl/pl_top_tb.v
+538 -96
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@@ -7,9 +7,9 @@ module pl_top_tb();
//*****************************************************************************
localparam T_CLK = 10 ; //ns
localparam RSH2116_QTY = 4 ;
localparam RSH2116_QTY = 2 ;//2
localparam EEG_ADS1299_QTY = 8 ;
localparam EEG_ADS1299_QTY = 4 ;
localparam EEG_ADS1299_SPI_QTY = 4 ;
//eeg ads1299
@@ -19,6 +19,8 @@ module pl_top_tb();
localparam EEG_BRAM_ADDR_EEG_ER = 13'h0040;
localparam EEG_BRAM_ADDR_EEG_CR = 13'h0044;
localparam EEG_BRAM_ADDR_EEG_SR = 13'h0048;
localparam BRAM_ADDR_CMD_D2 = 13'h004C;
localparam BRAM_ADDR_CMD_D1 = 13'h0050;
localparam EEG_BRAM_ADDR_EEG_TR = 13'h0100;
localparam EEG_BRAM_ADDR_EEG_RR = 13'h0200;
@@ -87,6 +89,18 @@ module pl_top_tb();
localparam BRAM_ADDR_CHIP_2_CNV_CMD_START = 13'h1080;
localparam BRAM_ADDR_CHIP_3_CNV_CMD_START = 13'h10C0;
localparam BRAM_ADDR_IMP_TEST_EN = 13'h000c;
localparam BRAM_ADDR_IMP_STIM_EM = 13'h0010;
localparam BRAM_ADDR_IMP_STIM_DATA0 = 13'h0014;
localparam BRAM_ADDR_IMP_STIM_DATA1 = 13'h0018;
localparam BRAM_ADDR_IMP_CMD_DATA2 = 13'h0028;
localparam BRAM_ADDR_IMP_CMD_DATA1 = 13'h002c;
localparam BRAM_ADDR_IMP_EEG_EMG_SEL = 13'h0030;
localparam BRAM_ADDR_IMP_EEG_SEND_PACKAGE_NUM = 13'h0034;
localparam BRAM_ADDR_IMP_EMG_SEND_PACKAGE_NUM = 13'h0038;
localparam BRAM_ADDR_DIFF_PKT_DATA_SEL = 13'h003C;
localparam COVER_Y = 1'b1;
localparam COVER_N = 1'b0;
@@ -191,6 +205,23 @@ module pl_top_tb();
reg bram_msg_en ;
reg bram_msg_rst ;
reg [ 4-1:0] bram_msg_we ;
reg [32-1:0] read_data ;
reg [13-1:0] bram_msg_emg_addr ;
reg bram_msg_emg_clk ;
reg [32-1:0] bram_msg_emg_din ;
wire [32-1:0] bram_msg_emg_dout ;
reg bram_msg_emg_en ;
reg bram_msg_emg_rst ;
reg [ 4-1:0] bram_msg_emg_we ;
reg [13-1:0] bram_imp_addr ;
reg bram_imp_clk ;
reg [32-1:0] bram_imp_din ;
wire [32-1:0] bram_imp_dout ;
reg bram_imp_en ;
reg bram_imp_rst ;
reg [ 4-1:0] bram_imp_we ;
wire stim_int ;
wire eeg_int ;
@@ -228,8 +259,8 @@ module pl_top_tb();
wire emg_ads1299_spi_cs ;
wire emg_ads1299_spi_sclk ;
wire emg_ads1299_spi_mosi ;
reg emg_ads1299_spi_miso ;
reg emg_ads1299_drdy_n ;
wire emg_ads1299_spi_miso ;
wire emg_ads1299_drdy_n ;
wire emg_ads1299_start ;
wire emg_ads1299_reset_n ;
wire emg_ads1299_pwdn_n ;
@@ -345,6 +376,22 @@ module pl_top_tb();
.bram_msg_rst ( bram_msg_rst ),
.bram_msg_we ( bram_msg_we ),
.bram_msg_emg_addr ( bram_msg_emg_addr ),
.bram_msg_emg_clk ( bram_msg_emg_clk ),
.bram_msg_emg_din ( bram_msg_emg_din ),
.bram_msg_emg_dout ( bram_msg_emg_dout ),
.bram_msg_emg_en ( bram_msg_emg_en ),
.bram_msg_emg_rst ( bram_msg_emg_rst ),
.bram_msg_emg_we ( bram_msg_emg_we ),
.bram_imp_addr ( bram_imp_addr ),
.bram_imp_clk ( bram_imp_clk ),
.bram_imp_din ( bram_imp_din ),
.bram_imp_dout ( bram_imp_dout ),
.bram_imp_en ( bram_imp_en ),
.bram_imp_rst ( bram_imp_rst ),
.bram_imp_we ( bram_imp_we ),
.stim_int ( stim_int ),
.eeg_int ( eeg_int ),
.emg_int ( emg_int ),
@@ -388,25 +435,6 @@ module pl_top_tb();
.emg_ads1299_reset_n ( emg_ads1299_reset_n ),
.emg_ads1299_pwdn_n ( emg_ads1299_pwdn_n ),
//------------------------------------------ device: MEMS
.accel_spi_cs ( accel_spi_cs ),
.accel_spi_sclk ( accel_spi_sclk ),
.accel_spi_mosi ( accel_spi_mosi ),
.accel_spi_miso ( accel_spi_miso ),
.accel_int0 ( accel_int0 ),
.accel_int1 ( accel_int1 ),
//------------------------------------------ ADG1414
.adg1414_spi_sync ( adg1414_spi_sync ),
.adg1414_spi_sclk ( adg1414_spi_sclk ),
.adg1414_spi_mosi ( adg1414_spi_mosi ),
.adg1414_spi_miso ( 1'b0 ),
//------------------------------------------ Trigger
.trigger_reset ( trigger_reset ),
.trigger_in ( trigger_in ),
.trigger_out ( trigger_out ),
//------------------------------------------ Debug
.debug_sig ( )
);
@@ -425,7 +453,7 @@ module pl_top_tb();
generate
for(i=0; i<EEG_ADS1299_QTY; i=i+1) begin : ADS1299_EEG
ads1299_mod u_ads1299_mod
ads1299_mod u0_ads1299_mod
(
.cs ( emg_ads1299_cs_w[i] ),
.sclk ( emg_ads1299_sclk_w[i] ),
@@ -437,6 +465,204 @@ module pl_top_tb();
end
endgenerate
ads1299_mod u1_ads1299_mod
(
.cs ( emg_ads1299_spi_cs ),
.sclk ( emg_ads1299_spi_sclk ),
.mosi ( emg_ads1299_spi_mosi ),
.miso ( emg_ads1299_spi_miso ),
.drdy ( emg_ads1299_drdy_n ),
.start ( emg_ads1299_start )
);
initial begin
Initial();
#100 rst_n = 0;
#100 rst_n = 1;
#100
///*
//SDATAC
@ ( posedge clk );
write_bram_imp(BRAM_ADDR_IMP_EEG_EMG_SEL, 2'h0);
write_bram_imp(BRAM_ADDR_IMP_EEG_SEND_PACKAGE_NUM, 16'h0);
write_bram_imp(BRAM_ADDR_IMP_EMG_SEND_PACKAGE_NUM, 16'h0);
write_bram_imp(BRAM_ADDR_DIFF_PKT_DATA_SEL,1'h0);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h00, 32'h00000011);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h04, 32'h00000011);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h08, 32'h00000011);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h0C, 32'h00000011);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h00, 32'h00000011);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h04, 32'h00000011);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h08, 32'h00000011);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h0C, 32'h00000011);
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_CR, {16'd0, 4'b0100, 4'b0100, 4'b0100, 4'b0100});
write_bram_emg(EEG_BRAM_ADDR_EEG_CR, {12'd0, 5'b00100, 5'b00100, 5'b00100, 5'b00100});//{16'd0, 4'b0100, 4'b0100, 4'b0100, 4'b0100});
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_ER, 32'hF);
write_bram_emg(EEG_BRAM_ADDR_EEG_ER, 32'hF);
#4_000
@ ( posedge clk );
write_bram_imp(BRAM_ADDR_IMP_EEG_EMG_SEL, 2'h3);
write_bram_imp(BRAM_ADDR_IMP_EEG_SEND_PACKAGE_NUM, 16'd568);//67个包，1个通道：568。320个包：62819。10个 包：16'd2059（对应10个包）
write_bram_imp(BRAM_ADDR_IMP_EMG_SEND_PACKAGE_NUM, 16'd568); //67个包，1个通道：568。320个包：9059。10个包：16'd379
write_bram_imp(BRAM_ADDR_DIFF_PKT_DATA_SEL, 1'h0); // 1'h1
write_bram_eeg(EEG_BRAM_ADDR_EEG_CR, {16'd0, 4'b0101, 4'b0101, 4'b0101, 4'b0101});
write_bram_emg(EEG_BRAM_ADDR_EEG_CR, {12'd0, 5'b00101, 5'b00101, 5'b00101, 5'b00101});//{16'd0, 4'b0101, 4'b0101, 4'b0101, 4'b0101})
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_ER, 32'hF);
write_bram_emg(EEG_BRAM_ADDR_EEG_ER, 32'hF);
#4_000
//READ ID
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h00, 32'h00010020);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h04, 32'h00020020);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h08, 32'h00030020);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h0C, 32'h00040020);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h00, 32'h00010020);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h04, 32'h00020020);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h08, 32'h00030020);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h0C, 32'h00040020);
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_CR, {16'd0, 4'b1100, 4'b1100, 4'b1100, 4'b1100});
write_bram_emg(EEG_BRAM_ADDR_EEG_CR, {12'd0, 5'b10000, 5'b10000, 5'b10000, 5'b10000});//{16'd0, 4'b1100, 4'b1100, 4'b1100, 4'b1100})
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_ER, 32'hF);
write_bram_emg(EEG_BRAM_ADDR_EEG_ER, 32'hF);
#10_000
read_bram_eeg(EEG_BRAM_ADDR_EEG_RR+4'h0, read_data);
read_bram_emg(EEG_BRAM_ADDR_EEG_RR+4'h0, read_data);
#100
// $stop;
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h00, 32'h00010020);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h04, 32'h00020020);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h08, 32'h00030020);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h0C, 32'h00040020);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h00, 32'h00010020);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h04, 32'h00020020);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h08, 32'h00030020);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h0C, 32'h00040020);
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_CR, {16'd0, 4'b1101, 4'b1101, 4'b1101, 4'b1101});
write_bram_emg(EEG_BRAM_ADDR_EEG_CR, {12'd0, 5'b10001, 5'b10001, 5'b10001, 5'b10001});//{16'd0, 4'b1101, 4'b1101, 4'b1101, 4'b1101})
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_ER, 32'hF);
write_bram_emg(EEG_BRAM_ADDR_EEG_ER, 32'hF);
#10_000
//
#7_000
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h00, 32'h00000010);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h04, 32'h00000010);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h08, 32'h00000010);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h0C, 32'h00000010);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h00, 32'h00000010);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h04, 32'h00000010);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h08, 32'h00000010);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h0C, 32'h00000010);
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_CR, {16'd0, 4'b0100, 4'b0100, 4'b0100, 4'b0100});
write_bram_emg(EEG_BRAM_ADDR_EEG_CR, {12'd0, 5'b00100, 5'b00100, 5'b00100, 5'b00100});//{16'd0, 4'b0100, 4'b0100, 4'b0100, 4'b0100})
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_ER, 32'hF);
write_bram_emg(EEG_BRAM_ADDR_EEG_ER, 32'hF);
#3_000
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h00, 32'h00000010);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h04, 32'h00000010);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h08, 32'h00000010);
write_bram_eeg(EEG_BRAM_ADDR_EEG_TR + 8'h0C, 32'h00000010);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h00, 32'h00000010);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h04, 32'h00000010);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h08, 32'h00000010);
write_bram_emg(EEG_BRAM_ADDR_EEG_TR + 8'h0C, 32'h00000010);
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_CR, {16'd0, 4'b0101, 4'b0101, 4'b0101, 4'b0101});
write_bram_emg(EEG_BRAM_ADDR_EEG_CR, {12'd0, 5'b00101, 5'b00101, 5'b00101, 5'b00101});//{16'd0, 4'b0101, 4'b0101, 4'b0101, 4'b0101})
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_ER, 32'hF);
write_bram_emg(EEG_BRAM_ADDR_EEG_ER, 32'hF);
#3_000
@ ( posedge clk );
write_bram_eeg(EEG_BRAM_ADDR_EEG_CR, {1'b1, 15'd10, 16'd0});
write_bram_emg(EEG_BRAM_ADDR_EEG_CR, {1'b1, 15'd10, 16'd0});
#1_000
@ ( posedge clk );
write_bram_eeg(BRAM_ADDR_CMD_D2, 32'h5aa52786);
write_bram_eeg(BRAM_ADDR_CMD_D1, 32'h6bb57c74);
write_bram_emg(BRAM_ADDR_CMD_D2, 32'h5aa52786);
write_bram_emg(BRAM_ADDR_CMD_D1, 32'h6bb57c74);
#32_000
@ ( posedge clk );
write_bram_eeg(BRAM_ADDR_CMD_D2, 32'h0);
write_bram_eeg(BRAM_ADDR_CMD_D1, 32'h0);
write_bram_emg(BRAM_ADDR_CMD_D2, 32'h0);
write_bram_emg(BRAM_ADDR_CMD_D1, 32'h0);
#32_000
@ ( posedge clk );
write_bram_eeg(BRAM_ADDR_CMD_D2, 32'h6bb67dd1);
write_bram_eeg(BRAM_ADDR_CMD_D1, 32'ha67963c4);
write_bram_emg(BRAM_ADDR_CMD_D2, 32'h6bb67dd1);
write_bram_emg(BRAM_ADDR_CMD_D1, 32'ha67963c4);
#32_000
@ ( posedge clk );
write_bram_eeg(BRAM_ADDR_CMD_D2, 32'h0);
write_bram_eeg(BRAM_ADDR_CMD_D1, 32'h0);
write_bram_emg(BRAM_ADDR_CMD_D2, 32'h0);
write_bram_emg(BRAM_ADDR_CMD_D1, 32'h0);
// #40_000
// @ ( posedge clk );
// $stop;
end
task Initial1;
begin
//clk <= 1'b0 ;
//rst_n <= 1'b0 ;
//bram_eeg_addr <= 0 ;
bram_eeg_clk <= 1'b0 ;
//bram_eeg_din <= 0 ;
//bram_eeg_en <= 1'b0 ;
//bram_eeg_rst <= 1'b0 ;
//bram_eeg_we <= 0 ;
//trigger_tdata <= 0 ;
//trigger_tvalid <= 1'b0 ;
// axis_record_tready <= 1'b1;
end
endtask
//*****************************************************************************
// Task
//*****************************************************************************
@@ -475,6 +701,19 @@ module pl_top_tb();
bram_msg_en <= 0 ;
bram_msg_rst <= 0 ;
bram_msg_we <= 0 ;
bram_msg_emg_addr <= 0 ;
bram_msg_emg_din <= 0 ;
bram_msg_emg_en <= 0 ;
bram_msg_emg_rst <= 0 ;
bram_msg_emg_we <= 0 ;
bram_imp_addr <= 0 ;
bram_imp_din <= 0 ;
bram_imp_en <= 0 ;
bram_imp_rst <= 0 ;
bram_imp_we <= 0 ;
accel_spi_miso <= 1'b0 ;
@@ -646,6 +885,96 @@ module pl_top_tb();
end
endtask
task write_bram_emg_msg;
input [12:0] addr;
input [31:0] data;
begin
@ ( posedge clk );
bram_msg_emg_addr <= addr;
bram_msg_emg_din <= data;
bram_msg_emg_en <= 1'b1;
bram_msg_emg_we <= 4'hF;
@ ( posedge clk );
bram_msg_emg_en <= 1'b0;
bram_msg_emg_we <= 4'h0;
end
endtask
task write_bram_byte_emg_msg;
input [12:0] addr;
input [ 7:0] data;
reg [31:0] data_w;
reg [ 3:0] we_w;
begin
we_w[0] <= (addr[1:0]==2'b00)? 1'b1:1'b0;
we_w[1] <= (addr[1:0]==2'b01)? 1'b1:1'b0;
we_w[2] <= (addr[1:0]==2'b10)? 1'b1:1'b0;
we_w[3] <= (addr[1:0]==2'b11)? 1'b1:1'b0;
data_w[ 7: 0] <= (addr[1:0]==2'b00)? data:8'h00;
data_w[15: 8] <= (addr[1:0]==2'b01)? data:8'h00;
data_w[23:16] <= (addr[1:0]==2'b10)? data:8'h00;
data_w[31:24] <= (addr[1:0]==2'b11)? data:8'h00;
@ ( posedge clk );
bram_msg_emg_addr <= addr;
bram_msg_emg_din <= data_w;
bram_msg_emg_en <= 1'b1;
bram_msg_emg_we <= we_w;
@ ( posedge clk );
bram_msg_emg_en <= 1'b0;
bram_msg_emg_we <= 4'h0;
end
endtask
task read_bram_emg_msg;
input [12:0] addr;
output [31:0] data;
begin
@ ( posedge clk );
bram_msg_emg_addr <= addr;
bram_msg_emg_en <= 1'b1;
bram_msg_emg_we <= 4'h0;
@ ( posedge clk );
bram_msg_emg_en <= 1'b0;
@ ( posedge clk );
data <= bram_msg_emg_dout;
end
endtask
task write_bram_imp;
input [12:0] addr;
input [31:0] data;
begin
@ ( posedge clk );
bram_imp_addr <= addr;
bram_imp_din <= data;
bram_imp_en <= 1'b1;
bram_imp_we <= 4'hF;
@ ( posedge clk );
bram_imp_en <= 1'b0;
bram_imp_we <= 4'h0;
end
endtask
task read_bram_imp;
input [12:0] addr;
output [31:0] data;
begin
@ ( posedge clk );
bram_imp_addr <= addr;
bram_imp_en <= 1'b1;
bram_imp_we <= 4'h0;
@ ( posedge clk );
bram_imp_en <= 1'b0;
@ ( posedge clk );
data <= bram_imp_dout;
end
endtask
task write_fifo;
input [32-1:0] tdata;
input tlast;
@@ -754,9 +1083,9 @@ module pl_top_tb();
write_bram_msg(BRAM_ADDR_MSG_TEST_RW, 32'h1 );
read_bram_msg(BRAM_ADDR_MSG_TEST_RW, temp32 );
write_bram_msg(BRAM_ADDR_MSG_SEL_EEG24, 32'b00 );
write_bram_msg(BRAM_ADDR_MSG_ROUNDS_QTY, 32'd10 );
write_bram_msg(BRAM_ADDR_MSG_PRE_MSG_LTH, 32'd77 );
write_bram_msg(BRAM_ADDR_MSG_SEL_EEG24, 32'h3 );
write_bram_msg(BRAM_ADDR_MSG_ROUNDS_QTY, 32'd67 );//32'd320,32'd10
write_bram_msg(BRAM_ADDR_MSG_PRE_MSG_LTH, 32'd85 );
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h00, 8'h5A); //16'hA55A
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h01, 8'hA5);
@@ -785,14 +1114,14 @@ module pl_top_tb();
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h18, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h19, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1A, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1B, 8'hFF); //upload channel
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1C, 8'hFF);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1D, 8'hFF);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1E, 8'hFF);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1F, 8'hFF);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h20, 8'hFF);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h21, 8'hFF);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h22, 8'hFF);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1B, 8'h01); //8'hFF//upload channel
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1C, 8'h00); //8'hFF
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1D, 8'h00); //8'hFF
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1E, 8'h00); //8'hFF
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1F, 8'h00); //8'hFF
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h20, 8'h00); //8'hFF
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h21, 8'h00); //8'hFF
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h22, 8'h00); //8'hFF
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h23, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h24, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h25, 8'h00);
@@ -817,24 +1146,32 @@ module pl_top_tb();
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h38, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h39, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3A, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3B, 8'h00); //OriRate
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3C, 8'h7D);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3D, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3E, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3F, 8'h00); //SampleRate
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h40, 8'h7D);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h41, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h42, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h43, 8'h01); //SampleLen
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h44, 8'h02);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h45, 8'h03);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h46, 8'h04);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h47, 8'h18); //resolution
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h48, 8'h00); //filter flag
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h49, 8'h10); //DataLen
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4A, 8'h20);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4B, 8'h30);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4C, 8'h40);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3B, 8'h00);//range
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3C, 8'h00);//range
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3D, 8'h00);//range
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3E, 8'h00);//range
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3F, 8'hFF);//0x457 cmd new add
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h40, 8'h00);//0x457 cmd new add
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h41, 8'h00);//0x457 cmd new add
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h42, 8'h00);//0x457 cmd new add
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h43, 8'h00); //OriRate
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h44, 8'h7D);//8'h7D
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h45, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h46, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h47, 8'h00); //SampleRate
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h48, 8'h7D);//8'h7D
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h49, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4a, 8'h00);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4b, 8'h40); //SampleLen 8'h0a
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4c, 8'h01); //SampleLen 8'h00
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4d, 8'h00); //SampleLen
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4e, 8'h00); //SampleLen
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4f, 8'h18); //resolution
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h50, 8'h00); //filter flag
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h51, 8'h10); //DataLen 8'h10
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h52, 8'h20);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h53, 8'h30);
write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h54, 8'h40);
write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd00, 8'd58); //PL_ch-0 -> PC_ch-59
write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd01, 8'd59);
@@ -901,15 +1238,120 @@ module pl_top_tb();
write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd62, 8'd29);
write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd63, 8'd27); //PL_ch-63 -> PC_ch-28
write_bram_msg(BRAM_ADDR_MSG_UPLOAD_CH_START+8'h0, 32'hFFFFFFFF);
write_bram_msg(BRAM_ADDR_MSG_UPLOAD_CH_START+8'h4, 32'hFFFFFFFF);
write_bram_msg(BRAM_ADDR_MSG_UPLOAD_CH_START+8'h0, 32'h1);//eeg上传通道选择 32'hFFFFFFFF
write_bram_msg(BRAM_ADDR_MSG_UPLOAD_CH_START+8'h4, 32'h0);//eeg上传通道选择 32'hFFFFFFFF
//record:(ads1299)
// #1_000
// @ ( posedge clk );
// write_bram_eeg(EEG_BRAM_ADDR_EEG_CR, {1'b1, 15'd10, 16'd0});
//record config
read_bram_emg_msg(BRAM_ADDR_MSG_TEST_RO, temp32 );
write_bram_emg_msg(BRAM_ADDR_MSG_TEST_RW, 32'h1 );
read_bram_emg_msg(BRAM_ADDR_MSG_TEST_RW, temp32 );
//stim:(rhs2116)
write_bram_emg_msg(BRAM_ADDR_MSG_SEL_EEG24, 32'h3 );//32'b00
write_bram_emg_msg(BRAM_ADDR_MSG_ROUNDS_QTY, 32'd67 );//32'd320,32'd10，上传多少个数据包确定，比如8k上传160个数据包，1k上传20个数据包
write_bram_emg_msg(BRAM_ADDR_MSG_PRE_MSG_LTH, 32'd85 );//pkg_eeg:81,pkg_eeg:77
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h00, 8'h5A); //16'hA55A
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h01, 8'hA5);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h02, 8'h01); //device -> PC
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h03, 8'h39); //device type
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h04, 8'h01); //device ID: 32'04030201
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h05, 8'h02);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h06, 8'h03);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h07, 8'h04);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h08, 8'h10); //message length
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h09, 8'h11);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h0A, 8'h12);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h0B, 8'h13);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h0C, 8'h56); //cmd: 16'h0456
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h0D, 8'h04);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h0E, 8'h00); //run time(ms)
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h0F, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h10, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h11, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h12, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h13, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h14, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h15, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h16, 8'h00); //result
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h17, 8'h00); //package id
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h18, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h19, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1A, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1B, 8'h00);//8'hFF //upload channel
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1C, 8'h00);//8'hFF
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1D, 8'h00);//8'hFF
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1E, 8'h00);//8'hFF
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1F, 8'h00);//8'hFF
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h20, 8'h00);//8'hFF
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h21, 8'h00);//8'hFF
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h22, 8'h01);//8'hFF
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h23, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h24, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h25, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h26, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h27, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h28, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h29, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h2A, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h2B, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h2C, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h2D, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h2E, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h2F, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h30, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h31, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h32, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h33, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h34, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h35, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h36, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h37, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h38, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h39, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3A, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3B, 8'h00);//range
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3C, 8'h00);//range
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3D, 8'h00);//range
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3E, 8'h00);//range
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3F, 8'hFF);//0x457 cmd new add
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h40, 8'h00);//0x457 cmd new add
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h41, 8'h00);//0x457 cmd new add
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h42, 8'h00);//0x457 cmd new add
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h43, 8'h00); //OriRate
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h44, 8'h7D);//8'h7D
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h45, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h46, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h47, 8'h00); //SampleRate
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h48, 8'h7D);//8'h7D
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h49, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4A, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4B, 8'h40); //SampleLen 8'h0a
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4C, 8'h01);//8'h00
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4D, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4E, 8'h00);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4F, 8'h18); //resolution
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h50, 8'h00); //filter flag
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h51, 8'h10); //DataLen
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h52, 8'h20);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h53, 8'h30);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h54, 8'h40);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd00, 8'd00); //PL_ch-0 -> PC_ch-59
write_bram_byte_emg_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd01, 8'd01);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd02, 8'd02);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd03, 8'd03);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd04, 8'd04);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd05, 8'd05);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd06, 8'd06);
write_bram_byte_emg_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd07, 8'd07);
write_bram_emg_msg(BRAM_ADDR_MSG_UPLOAD_CH_START+8'h0, 32'h1);//emg上传通道选择 32'hFF
write_bram_emg_msg(BRAM_ADDR_MSG_UPLOAD_CH_START+8'h4, 32'h0);//emg上传通道选择 32'h0
#1_000
//Config DDS
write_bram_2116(BRAM_ADDR_DDS_PHASE_INC_START + 8'h00, 32'h000029F1);
@@ -983,43 +1425,43 @@ module pl_top_tb();
write_fifo(code_read (CHIP_1, 8'hFB), 1'b0);
write_fifo(code_read (CHIP_1, 8'hFC), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_0), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_1), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_2), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_3), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_4), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_5), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_6), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_7), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_8), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_9), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_A), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_B), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_C), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_D), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_E), 1'b0);
write_fifo(code_cnv (CHIP_2, CHANNEL_F), 1'b0);
write_fifo(code_read (CHIP_2, 8'hFB), 1'b0);
write_fifo(code_read (CHIP_2, 8'hFC), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_0), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_1), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_2), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_3), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_4), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_5), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_6), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_7), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_8), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_9), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_A), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_B), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_C), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_D), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_E), 1'b0);
// write_fifo(code_cnv (CHIP_2, CHANNEL_F), 1'b0);
// write_fifo(code_read (CHIP_2, 8'hFB), 1'b0);
// write_fifo(code_read (CHIP_2, 8'hFC), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_0), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_1), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_2), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_3), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_4), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_5), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_6), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_7), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_8), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_9), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_A), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_B), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_C), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_D), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_E), 1'b0);
write_fifo(code_cnv (CHIP_3, CHANNEL_F), 1'b0);
write_fifo(code_read (CHIP_3, 8'hFB), 1'b0);
write_fifo(code_read (CHIP_3, 8'hFC), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_0), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_1), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_2), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_3), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_4), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_5), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_6), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_7), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_8), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_9), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_A), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_B), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_C), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_D), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_E), 1'b0);
// write_fifo(code_cnv (CHIP_3, CHANNEL_F), 1'b0);
// write_fifo(code_read (CHIP_3, 8'hFB), 1'b0);
// write_fifo(code_read (CHIP_3, 8'hFC), 1'b0);
write_fifo(code_end (0, 0), 1'b1);