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sync chunk 11/12

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chunk-sync
2026-09-11 16:18:36 +08:00
parent c315cef09e
commit c2c1bb2648
922 changed files with 102283 additions and 6793 deletions
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c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v
+20 -20
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@@ -4,9 +4,9 @@ module eeg_top#
(
parameter CLK_PERIOD = 10 ,
parameter CHIPSET_QTY = 8 ,
parameter CHIPSET_QTY = 4 ,//8
parameter CHIPSET_CH_QTY = 8 ,
parameter SPIS_QTY = 4 ,
parameter SPIS_QTY = 2 ,//4
parameter SPI_SLAVE_QTY = 2 ,
parameter SPI_CLK_DIV = 3 ,
@@ -37,7 +37,7 @@ module eeg_top#
output [ SPIS_QTY-1:0] mosi ,
input [ SPIS_QTY-1:0] miso ,
input [ SPIS_QTY-1:0] drdy ,
output start ,
output [ SPIS_QTY-1:0] start ,
output [ 4-1:0] debug_sig
);
@@ -100,30 +100,30 @@ module eeg_top#
//*****************************************************************************
eeg_config#
(
.SPIS_QTY ( 4 ),
.SPIS_QTY ( 2 ),//4
.SPI_DATA_WIDTH ( 8 )
)
u_eeg_config
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk ( clk ),
.rst_n ( rst_n ),
.bram_addr ( bram_addr ),
.bram_clk ( bram_clk ),
.bram_din ( bram_din ),
.bram_dout ( bram_dout ),
.bram_en ( bram_en ),
.bram_rst ( bram_rst ),
.bram_we ( bram_we ),
.bram_addr ( bram_addr ),
.bram_clk ( bram_clk ),
.bram_din ( bram_din ),
.bram_dout ( bram_dout ),
.bram_en ( bram_en ),
.bram_rst ( bram_rst ),
.bram_we ( bram_we ),
//eeg
.eeg_er ( eeg_er ),
.eeg_cr ( eeg_cr ),
.eeg_sr ( eeg_sr ),
.eeg_tr_array ( eeg_tr_array ),
.eeg_rr_array ( eeg_rr_array ),
.eeg_er ( eeg_er ),
.eeg_cr ( eeg_cr ),
.eeg_sr ( eeg_sr ),
.eeg_tr_array ( eeg_tr_array ),
.eeg_rr_array ( eeg_rr_array ),
.eeg_sr_r_evt ( eeg_sr_r_evt )
.eeg_sr_r_evt ( eeg_sr_r_evt )
);
generate
@@ -240,7 +240,7 @@ module eeg_top#
//*****************************************************************************
assign record_enable = eeg_cr[31];
assign start = cnv_start[0];
assign start = {cnv_start[0],cnv_start[0]};
generate
for(i=0;i<SPIS_QTY;i=i+1) begin : mapping