sync chunk 11/12

c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v

@@ -119,6 +119,7 @@ module ads1299_if#
 			r_cnt <= r_cnt + 1'b1;
 	end
 
+
 	always @ ( posedge clk or negedge rst_n ) begin
 		if ( !rst_n )
 			slv_cnt <= 0;

c64_pro.srcs/sources_1/rtl/eeg/ads1299_if1.v

@@ -0,0 +1,194 @@
+`timescale 1 ns / 1 ps
+
+module ads1299_if1#
+	(
+		parameter 		SPI_CLK_DIV			=     3	,
+		parameter 		SPI_DATA_WIDTH		=     8	,
+		parameter 		SPI_SLAVE_QTY		=     2	,
+		parameter 		SPI_CNV_BYTES		=     3
+	)
+	(
+		input					clk					,
+		input					rst_n				,
+
+		input					upload_enable		,
+		input					upload_round		,
+
+		//------------------------------------------ spi direct communication
+		input		[ 8-1:0]	t_cs_n		        ,
+		input		[ 8-1:0]	t_tdata		        ,
+		input					t_tlast		        ,
+		output					t_tready		    ,
+		input					t_tvalid		    ,
+		
+		output		[ 8-1:0]	r_tdata             ,
+		output					r_tlast             ,
+		output					r_tvalid            ,
+		
+		//------------------------------------------ record stream rx
+		output	reg	[32-1:0]	cnv_res_tdata		,
+		output	reg				cnv_res_tlast		,
+		input					cnv_res_tready		,
+		output	reg				cnv_res_tvalid		,
+	
+		//------------------------------------------ device spi
+		output		[SPI_SLAVE_QTY-1:0]		cs		,
+		output					sclk				,
+		output					mosi				,
+		input					miso
+	);
+	
+	//*****************************************************************************
+	// localparam definition
+	//*****************************************************************************
+	localparam 	IDLE					= 4'h0		;
+	localparam 	UPLOAD_ST				= 4'h1		;
+	
+	//*****************************************************************************
+	// Internal register and wire declarations
+	//*****************************************************************************
+    wire    [ 8-1:0]	    r_tdata_w               ;
+    wire				    r_tlast_w               ;
+    wire				    r_tvalid_w              ;
+    
+    wire    [ 8-1:0]	    res_tdata             	;
+    wire				    res_tlast             	;
+    wire				    res_tvalid            	;
+	
+	reg     [ 8-1:0]		slv_cnt					;
+	reg     [ 8-1:0]		r_cnt				    ;
+	reg     [ 4-1:0]		byte_cnt				;
+	reg     [32-1:0]		word				    ;
+	reg             		res_tvalid_b			;
+	reg             		res_tlast_b				;
+	
+	reg    [ 8-1:0]	   		ch						;
+	
+	//*****************************************************************************
+	// Instantiation
+	//*****************************************************************************
+    ads1299_spi1# 
+        (
+            .CLK_PERIOD			( 10				),
+            .CLK_DIV			( SPI_CLK_DIV		),
+            .DATA_WIDTH			( SPI_DATA_WIDTH	),
+            .NO_OF_SLAVES		( SPI_SLAVE_QTY	    )
+        )
+    u_ads1299_spi1
+        (
+            .clk				( clk 				),
+            .rst_n				( rst_n 			),
+            
+            .t_cs_n				( t_cs_n 			),
+            .t_tdata			( t_tdata 		    ),
+            .t_tlast			( t_tlast 		    ),
+            .t_tready			( t_tready		    ),
+            .t_tvalid			( t_tvalid		    ),
+
+            .r_tdata			( r_tdata_w  		),
+            .r_tlast			( r_tlast_w		    ),
+            .r_tvalid			( r_tvalid_w		),
+            
+            .cs					( cs				),
+            .sclk				( sclk   		    ),
+            .mosi				( mosi   		    ),
+            .miso				( miso   		    )
+        );
+	
+	//*****************************************************************************
+	// Procedural blocks
+	//*****************************************************************************
+	always @ ( posedge clk or negedge rst_n ) begin
+		if ( !rst_n ) begin
+			res_tvalid_b <= 1'b0;
+			res_tlast_b <= 1'b0;
+		end else begin
+			res_tvalid_b <= res_tvalid;
+			res_tlast_b <= res_tlast;
+		end
+	end
+
+	always @ ( posedge clk or negedge rst_n ) begin
+		if ( !rst_n )
+			r_cnt <= 0;
+		else if ( upload_round )
+			r_cnt <= 0;
+		else if ( res_tvalid && res_tlast )
+			r_cnt <= 0;
+		else if ( res_tvalid )
+			r_cnt <= r_cnt + 1'b1;
+	end
+
+
+	always @ ( posedge clk or negedge rst_n ) begin
+		if ( !rst_n )
+			slv_cnt <= 0;
+		else if ( upload_round )
+			slv_cnt <= 0;
+		else if ( res_tvalid && res_tlast )
+			slv_cnt <= slv_cnt + 1'b1;
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if ( !rst_n )
+			byte_cnt <= 0;
+		else if ( upload_round || r_cnt<SPI_CNV_BYTES )
+			byte_cnt <= 0;
+		else if ( res_tvalid ) begin
+			if ( byte_cnt == SPI_CNV_BYTES )
+                byte_cnt <= 1;
+            else
+                byte_cnt <= byte_cnt + 1'b1;
+		end
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if ( !rst_n )
+			word <= 0;
+        else if ( res_tvalid )
+            word <= {8'd0, word[15:0], res_tdata};
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if ( !rst_n ) begin
+			cnv_res_tdata <= 0;
+            cnv_res_tvalid <= 1'b0;
+		end else if ( res_tvalid_b && byte_cnt == SPI_CNV_BYTES ) begin
+			cnv_res_tdata <= {ch, word[23:0]};
+            cnv_res_tvalid <= 1'b1;
+		end else if ( cnv_res_tready )  begin
+            cnv_res_tvalid <= 1'b0;
+		end
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if ( !rst_n ) begin
+            cnv_res_tlast <= 1'b0;
+		end else if ( res_tvalid_b && res_tlast_b && slv_cnt == SPI_SLAVE_QTY ) begin
+            cnv_res_tlast <= res_tlast_b;
+		end else if ( cnv_res_tready )  begin
+            cnv_res_tlast <= 1'b0;
+		end
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if ( !rst_n )
+			ch <= 0;
+		else if ( upload_round )
+			ch <= 0;
+        else if ( res_tvalid_b && byte_cnt == SPI_CNV_BYTES )
+            ch <= ch + 1'b1;
+	end
+	
+	//*****************************************************************************
+	// Wire assignment
+	//*****************************************************************************
+	assign r_tdata  = (~upload_enable)? r_tdata_w :0;
+	assign r_tlast  = (~upload_enable)? r_tlast_w :0;
+	assign r_tvalid = (~upload_enable)? r_tvalid_w:0;
+
+	assign res_tdata  = (upload_enable)? r_tdata_w :0;
+	assign res_tlast  = (upload_enable)? r_tlast_w :0;
+	assign res_tvalid = (upload_enable)? r_tvalid_w:0;
+	
+endmodule

c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi1.v

@@ -0,0 +1,272 @@
+`timescale 1 ns / 1 ps
+
+module ads1299_spi1#
+	(
+		parameter	CLK_PERIOD			= 10		,
+		parameter	CLK_DIV				= 3			,	// max: 255
+		parameter	DATA_WIDTH			= 8			,	// max: 255
+        parameter	NO_OF_SLAVES		= 1
+	)
+	(
+		input							clk			,
+		input							rst_n		,
+		
+        input		[           8-1:0]	t_cs_n 		,
+        input		[  DATA_WIDTH-1:0]	t_tdata 	,
+        input							t_tlast 	,
+        output	reg						t_tready	,
+        input							t_tvalid	,
+
+        output	reg	[  DATA_WIDTH-1:0]	r_tdata  	,
+        output	reg						r_tlast		,
+        output	reg						r_tvalid	,
+        
+		output		[NO_OF_SLAVES-1:0]	cs			,
+		output							sclk		,
+		output							mosi		,
+		input							miso
+	);
+	
+	//*****************************************************************************
+	// localparam definition
+	//*****************************************************************************
+	localparam 	CNT_POS			= CLK_DIV-1			;
+	localparam 	CNT_NEG			= CLK_DIV*2-1		;
+
+	localparam 	T_SCCS			= 2000/CLK_PERIOD	;
+	localparam 	T_SCH			=  600/CLK_PERIOD	;
+	
+	localparam 	IDLE			= 4'd0;
+	localparam 	TRANS_ST		= 4'd1;
+	localparam 	SCCS_ST			= 4'd2;
+	localparam 	CSH_ST			= 4'd3;
+	
+	
+	//*****************************************************************************
+	// Internal register and wire declarations
+	//*****************************************************************************
+	reg [ 4-1:0]			cstate			;
+	reg [ 4-1:0]			nstate			;
+
+	reg [DATA_WIDTH-1:0]	tx_data			;
+	reg [DATA_WIDTH-1:0]	rx_data			;
+	reg 					clk_en			;
+	reg [ 9-1:0]			cnt				;
+	reg 					sck_pos			;
+	reg 					sck_neg			;
+	reg [ 8-1:0]			trans_cnt		;
+	
+	reg [ 8-1:0]			slv_n			;
+	reg [NO_OF_SLAVES-1:0]	cs_r			;
+	reg 					sclk_r			;
+	
+	reg [NO_OF_SLAVES-1:0]	cs_release		;
+
+	reg	[ 8-1:0]			t_sccs_cnt		;
+	reg	[ 8-1:0]			t_sch_cnt		;
+
+	reg						read_flag		;
+
+	//*****************************************************************************
+	always@( posedge clk or negedge rst_n ) begin
+		if( !rst_n )	cstate <= IDLE;
+		else        	cstate <= nstate;
+	end
+	
+	always@( * ) begin
+		case ( cstate )
+			IDLE:
+				if ( t_tvalid )
+					nstate 	<= TRANS_ST;
+				else
+					nstate 	<= IDLE;
+			TRANS_ST:
+				if( (trans_cnt == 0) && sck_neg )begin
+				    if(cs_release==1'b1)begin
+					    if(slv_n==8'h01)begin
+						    nstate 	<= IDLE ;
+						end else begin
+						    nstate 	<= SCCS_ST ;
+						end
+					end else begin
+					    nstate 	<= IDLE ;
+				    end
+					//nstate 	<= (cs_release[slv_n])? SCCS_ST : IDLE;
+				end else begin
+					nstate 	<= TRANS_ST;
+				end
+			SCCS_ST:
+				if ( t_sccs_cnt == T_SCCS - 1 )
+					nstate 	<= CSH_ST;
+				else
+					nstate 	<= SCCS_ST;
+			CSH_ST:
+				if ( t_sch_cnt == T_SCH - 1 )
+					nstate 	<= IDLE;
+				else
+					nstate 	<= CSH_ST;
+			default:
+				nstate 	<= IDLE;
+		endcase	
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if ( !rst_n )
+			t_tready <= 1'b0;
+		else if ( nstate == IDLE )
+			t_tready <= 1'b1;
+		else if ( cstate == IDLE && nstate == IDLE )
+			t_tready <= 1'b1;
+		else
+			t_tready <= 1'b0;
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if ( !rst_n ) begin
+			slv_n <= 0;
+		end else if ( cstate == IDLE || nstate == IDLE ) begin
+			slv_n <= t_cs_n;
+		end
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n )
+			cs_release <= 1'b0;
+		else if ( t_tvalid && t_tready && t_tlast )
+			cs_release[slv_n] <= 1'b1;
+		else if ( t_tvalid && t_tready )
+			cs_release[slv_n] <= 1'b0;
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n )
+			cs_r <= {NO_OF_SLAVES{1'b1}};
+		else if ( cstate == TRANS_ST )
+			cs_r[slv_n] <= 1'b0;
+		else if ( nstate == CSH_ST )
+			cs_r[slv_n] <= cs_release[slv_n];
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if ( !rst_n ) begin
+			tx_data <= 0;
+		end else if ( t_tready && t_tvalid ) begin
+			tx_data <= t_tdata;
+		end
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n )
+			clk_en <= 0;
+		else if ( ((cstate == IDLE) && (nstate == TRANS_ST)) || ((cstate == TRANS_ST) && (nstate != SCCS_ST)) )
+			clk_en <= 1'b1;
+		else if ( nstate == SCCS_ST || nstate == IDLE )
+			clk_en <= 1'b0;
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n )
+			cnt <= 0;
+		else if ( !clk_en )
+			cnt <= 0;
+		else if ( cnt == CLK_DIV*2-1 )
+			cnt <= 0;
+		else
+			cnt <= cnt + 1;
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n )
+			sck_pos <= 0;
+		else if ( clk_en && (cnt == CNT_POS) )
+			sck_pos <= 1;
+		else
+			sck_pos <= 0;
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n )
+			sck_neg <= 0;
+		else if ( clk_en && (cnt == CNT_NEG) )
+			sck_neg <= 1;
+		else
+			sck_neg <= 0;
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n )
+			sclk_r <= 0;
+		else if ( sck_pos && nstate == TRANS_ST )
+			sclk_r <= 1'b1;
+		else if ( sck_neg )
+			sclk_r <= 1'b0;
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n )
+			trans_cnt <= DATA_WIDTH;
+		else if ( cstate == IDLE )
+			trans_cnt <= DATA_WIDTH;
+		else if ( sck_pos && (trans_cnt != 0) )
+			trans_cnt <= trans_cnt - 1'b1;
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n )
+			rx_data <= 0;
+		else if ( sck_neg )
+			rx_data[trans_cnt] <= miso;
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n )
+			read_flag <= 1'b0;
+		else if ( cstate == TRANS_ST && nstate != TRANS_ST )
+			read_flag <= 1'b1;
+		else
+			read_flag <= 1'b0;
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n ) begin
+			r_tvalid <= 1'b0;
+			r_tdata <= 0;
+			r_tlast <= 1'b0;
+		end else if ( read_flag ) begin
+			r_tvalid <= 1'b1;
+			r_tdata <= rx_data;
+			r_tlast <= cs_release[slv_n];
+		end else begin
+			r_tvalid <= 1'b0;
+			r_tlast <= 1'b0;
+		end
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n ) begin
+			t_sccs_cnt <= 0;
+		end else if ( cstate != SCCS_ST ) begin
+			t_sccs_cnt <= 0;
+		end else begin
+			t_sccs_cnt <= t_sccs_cnt + 1'b1;
+		end
+	end
+	
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n ) begin
+			t_sch_cnt <= 0;
+		end else if ( cstate != CSH_ST ) begin
+			t_sch_cnt <= 0;
+		end else begin
+			t_sch_cnt <= t_sch_cnt + 1'b1;
+		end
+	end
+	
+	//*****************************************************************************
+	// Wire assignment
+	//*****************************************************************************
+	assign cs	= cs_r;
+	assign sclk = sclk_r;
+	assign mosi = (trans_cnt==DATA_WIDTH)? 1'b0:tx_data[trans_cnt];
+	
+endmodule

c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v

@@ -2,29 +2,30 @@
 
 module eeg_config#
 	(
-		parameter	SPIS_QTY			= 4			    	,
+		parameter	SPIS_QTY			= 4			    	 ,
 		parameter	SPI_DATA_WIDTH		= 8
 	)
 	(
-		input							clk					,
-		input							rst_n				,
+		input							clk					 ,
+		input							rst_n				 ,
 		
-		input		[13-1:0]			bram_addr			,
-		input							bram_clk			,
-		input		[32-1:0]			bram_din			,
-		output	reg	[32-1:0]			bram_dout			,
-		input							bram_en				,
-		input							bram_rst			,
-		input		[ 4-1:0]			bram_we				,
+		input		[13-1:0]			bram_addr			 ,
+		input							bram_clk			 ,
+		input		[32-1:0]			bram_din			 ,
+		output	reg	[32-1:0]			bram_dout			 ,
+		input							bram_en				 ,
+		input							bram_rst			 ,
+		input		[ 4-1:0]			bram_we				 ,
 		
 		//------------------------------------------ eeg
-		output		[32-1:0]			eeg_er				,
-		output		[32-1:0]			eeg_cr				,
-		input		[32-1:0]			eeg_sr				,
-		output		[32*SPIS_QTY-1:0]	eeg_tr_array		,
-		input		[32*SPIS_QTY-1:0]	eeg_rr_array		,
+		output		[32-1:0]			eeg_er				 ,
+		output		[32-1:0]			eeg_cr				 ,
+		input		[32-1:0]			eeg_sr				 ,
+		output		[32*SPIS_QTY-1:0]	eeg_tr_array		 ,
+		input		[32*SPIS_QTY-1:0]	eeg_rr_array		 ,
+
+		output	reg						eeg_sr_r_evt         
 
-		output	reg						eeg_sr_r_evt
 	);
 	
 	//*****************************************************************************
@@ -36,6 +37,7 @@ module eeg_config#
 	localparam 	BRAM_ADDR_EEG_ER				= 13'h0040;
 	localparam 	BRAM_ADDR_EEG_CR				= 13'h0044;
 	localparam 	BRAM_ADDR_EEG_SR				= 13'h0048;
+	
 	localparam 	BRAM_ADDR_EEG_TR				= 13'h0100;
 	localparam 	BRAM_ADDR_EEG_RR				= 13'h0200;
 	

c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v

@@ -4,9 +4,9 @@ module eeg_top#
 	(
 		parameter		CLK_PERIOD			= 10			,
 
-		parameter		CHIPSET_QTY			= 8				,
+		parameter		CHIPSET_QTY			= 4				,//8
 		parameter		CHIPSET_CH_QTY		= 8				,
-		parameter		SPIS_QTY			= 4				,
+		parameter		SPIS_QTY			= 2				,//4
 		parameter		SPI_SLAVE_QTY		= 2				,
 
 		parameter 		SPI_CLK_DIV			= 3				,
@@ -37,7 +37,7 @@ module eeg_top#
 		output	[   SPIS_QTY-1:0]		mosi				,
 		input	[   SPIS_QTY-1:0]		miso				,
 		input	[   SPIS_QTY-1:0]		drdy				,
-		output							start				,
+		output	[   SPIS_QTY-1:0]		start				,
 
 		output	[ 4-1:0]				debug_sig
 	);
@@ -100,30 +100,30 @@ module eeg_top#
 	//*****************************************************************************
 	eeg_config# 
 		(
-			.SPIS_QTY			( 4						),
+			.SPIS_QTY			( 2						),//4
 			.SPI_DATA_WIDTH		( 8						)
 		)
 	u_eeg_config
 		(
-			.clk				( clk					),
-			.rst_n				( rst_n					),
+			.clk				 ( clk					     ),
+			.rst_n				 ( rst_n					 ),
 			
-			.bram_addr			( bram_addr				),
-			.bram_clk			( bram_clk				),
-			.bram_din			( bram_din				),
-			.bram_dout			( bram_dout				),
-			.bram_en			( bram_en				),
-			.bram_rst			( bram_rst				),
-			.bram_we			( bram_we				),
+			.bram_addr			 ( bram_addr				 ),
+			.bram_clk			 ( bram_clk				     ),
+			.bram_din			 ( bram_din				     ),
+			.bram_dout			 ( bram_dout				 ),
+			.bram_en			 ( bram_en				     ),
+			.bram_rst			 ( bram_rst				     ),
+			.bram_we			 ( bram_we				     ),
 			
 			//eeg
-			.eeg_er				( eeg_er				),
-			.eeg_cr				( eeg_cr				),
-			.eeg_sr				( eeg_sr				),
-			.eeg_tr_array		( eeg_tr_array			),
-			.eeg_rr_array		( eeg_rr_array			),
+			.eeg_er				 ( eeg_er				     ),
+			.eeg_cr				 ( eeg_cr				     ),
+			.eeg_sr				 ( eeg_sr				     ),
+			.eeg_tr_array		 ( eeg_tr_array			     ),
+			.eeg_rr_array		 ( eeg_rr_array			     ),
 
-			.eeg_sr_r_evt		( eeg_sr_r_evt			)
+			.eeg_sr_r_evt		 ( eeg_sr_r_evt			     )
 		);
 		
 	generate
@@ -240,7 +240,7 @@ module eeg_top#
 	//*****************************************************************************
 	assign record_enable = eeg_cr[31];
 
-	assign start = cnv_start[0];
+	assign start = {cnv_start[0],cnv_start[0]};
 
 	generate
 		for(i=0;i<SPIS_QTY;i=i+1) begin : mapping

c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v

@@ -0,0 +1,272 @@
+`timescale 1 ns / 1 ps
+
+module eeg_top1#
+	(
+		parameter		CLK_PERIOD			= 10			,
+
+		parameter		CHIPSET_QTY			= 4				,//8
+		parameter		CHIPSET_CH_QTY		= 8				,
+		parameter		SPIS_QTY			= 2				,//4
+		parameter		SPI_SLAVE_QTY		= 2				,
+
+		parameter 		SPI_CLK_DIV			= 3				,
+		parameter 		SPI_DATA_WIDTH		= 8			    ,
+		parameter		SPI_TRANS_PERIOD	= 2000				//Unit: ns
+	)
+	(
+		input							clk					,
+		input							rst_n				,
+		
+		input	[13-1:0]				bram_addr			,
+		input							bram_clk			,
+		input	[32-1:0]				bram_din			,
+		output	[32-1:0]				bram_dout			,
+		input							bram_en				,
+		input							bram_rst			,
+		input	[ 4-1:0]				bram_we				,
+		
+		output							interrupt			,
+		
+		output	[32-1:0]				axis_record_tdata	,
+		output							axis_record_tlast	,
+		input							axis_record_tready	,
+		output							axis_record_tvalid	,
+	
+		output	[CHIPSET_QTY-1:0]		cs					,
+		output	[   SPIS_QTY-1:0]		sclk				,
+		output	[   SPIS_QTY-1:0]		mosi				,
+		input	[   SPIS_QTY-1:0]		miso				,
+		input	[   SPIS_QTY-1:0]		drdy				,
+		output	[   SPIS_QTY-1:0]		start				,
+
+		output	[ 4-1:0]				debug_sig
+	);
+	
+	//*****************************************************************************
+	// localparam definition
+	//*****************************************************************************
+	
+	
+	//*****************************************************************************
+	// Internal register and wire declarations
+	//*****************************************************************************
+	wire	[32-1:0]				eeg_er							;
+	wire	[32-1:0]				eeg_cr							;
+	wire	[32-1:0]				eeg_sr							;
+	wire	[32*SPIS_QTY-1:0]		eeg_tr_array					;
+	wire	[32*SPIS_QTY-1:0]		eeg_rr_array					;
+	wire							eeg_sr_r_evt					;
+
+	wire	[SPI_SLAVE_QTY-1:0]		cs_w[SPIS_QTY-1:0]				;
+
+	wire							send_enable[SPIS_QTY-1:0]		;
+	wire	[ 8-1:0]				send_cs_n[SPIS_QTY-1:0]			;
+	wire	[ 8-1:0]				send_length[SPIS_QTY-1:0]		;
+	wire	[32-1:0]				send_data_array[SPIS_QTY-1:0]	;
+	wire	[32-1:0]				recv_data_array[SPIS_QTY-1:0]	;
+	wire							recv_data_en_array[SPIS_QTY-1:0];
+
+	wire	[ 8-1:0]				t_cs_n[SPIS_QTY-1:0]			;
+	wire	[ 8-1:0]				t_tdata[SPIS_QTY-1:0]			;
+	wire							t_tlast[SPIS_QTY-1:0]			;
+	wire							t_tready[SPIS_QTY-1:0]			;
+	wire							t_tvalid[SPIS_QTY-1:0]			;
+
+	wire	[ 8-1:0]				r_tdata[SPIS_QTY-1:0]			;
+	wire							r_tlast[SPIS_QTY-1:0]			;
+	wire							r_tvalid[SPIS_QTY-1:0]			;
+
+	wire							cnv_start[SPIS_QTY-1:0]			;
+	wire							cnv_drdy[SPIS_QTY-1:0]			;
+	wire							upload_round[SPIS_QTY-1:0]		;
+					
+	//------------------------------------------ record stream rx
+	wire	[32-1:0]				cnv_res_tdata[SPIS_QTY-1:0]		;
+	wire							cnv_res_tlast[SPIS_QTY-1:0]		;
+	wire							cnv_res_tready[SPIS_QTY-1:0]	;
+	wire							cnv_res_tvalid[SPIS_QTY-1:0]	;
+
+	wire	[32*SPIS_QTY-1:0]		cnv_res_tdata_array				;
+	wire	[   SPIS_QTY-1:0]		cnv_res_tlast_array				;
+	wire	[   SPIS_QTY-1:0]		cnv_res_tready_array			;
+	wire	[   SPIS_QTY-1:0]		cnv_res_tvalid_array			;
+
+	wire							record_enable					;
+
+	genvar	i;
+	
+	//*****************************************************************************
+	// Instantiation
+	//*****************************************************************************
+	eeg_config# 
+		(
+			.SPIS_QTY			( 2						),//4
+			.SPI_DATA_WIDTH		( 8						)
+		)
+	u_eeg_config
+		(
+			.clk				 ( clk					     ),
+			.rst_n				 ( rst_n					 ),
+			
+			.bram_addr			 ( bram_addr				 ),
+			.bram_clk			 ( bram_clk				     ),
+			.bram_din			 ( bram_din				     ),
+			.bram_dout			 ( bram_dout				 ),
+			.bram_en			 ( bram_en				     ),
+			.bram_rst			 ( bram_rst				     ),
+			.bram_we			 ( bram_we				     ),
+			
+			//eeg
+			.eeg_er				 ( eeg_er				     ),
+			.eeg_cr				 ( eeg_cr				     ),
+			.eeg_sr				 ( eeg_sr				     ),
+			.eeg_tr_array		 ( eeg_tr_array			     ),
+			.eeg_rr_array		 ( eeg_rr_array			     ),
+
+			.eeg_sr_r_evt		 ( eeg_sr_r_evt			     )
+		);
+		
+	generate
+		for(i=0;i<SPIS_QTY;i=i+1) begin : transmit_arrange
+			ads1299_arrange# 
+				(
+					.CLK_PERIOD				( 10					),
+					.SPI_DATA_WIDTH			( 8						),
+					.SPI_TRANS_PERIOD		( SPI_TRANS_PERIOD		)
+				)
+			u_ads1299_arrange
+				(
+					.clk					( clk					),
+					.rst_n					( rst_n					),
+					
+					.send_cs_n				( send_cs_n[i]			),
+					.send_enable			( send_enable[i]		),
+					.send_length			( send_length[i]		),
+					.send_data_array		( send_data_array[i]	),
+					.recv_data_en			( recv_data_en_array[i]	),
+					.recv_data_array		( recv_data_array[i]	),
+
+					.t_cs_n					( t_cs_n[i]				),
+					.t_tdata				( t_tdata[i] 			),
+					.t_tlast				( t_tlast[i] 			),
+					.t_tready				( t_tready[i]			),
+					.t_tvalid				( t_tvalid[i]			),
+
+					.r_tdata				( r_tdata[i]  			),
+					.r_tlast				( r_tlast[i] 			),
+					.r_tvalid				( r_tvalid[i]			),
+					
+					.rdatac_enable			( record_enable			),
+					.cnv_start				( cnv_start[i]			),
+					.cnv_drdy				( cnv_drdy[0]			),
+					.upload_round			( upload_round[i]		)
+				);
+		end
+	endgenerate
+
+	generate
+		for(i=0;i<SPIS_QTY;i=i+1) begin : trans_if
+			ads1299_if1# 
+				(
+					.SPI_CLK_DIV			( SPI_CLK_DIV			),
+					.SPI_DATA_WIDTH			( SPI_DATA_WIDTH		),
+					.SPI_SLAVE_QTY			( SPI_SLAVE_QTY			)
+				)
+			u_ads1299_if1
+				(
+					.clk					( clk					),
+					.rst_n					( rst_n					),
+					
+					.upload_enable			( record_enable			),
+					.upload_round			( upload_round[i]		),
+
+					//------------------------------------------ spi direct communication
+					.t_cs_n					( t_cs_n[i] 			),
+					.t_tdata				( t_tdata[i] 			),
+					.t_tlast				( t_tlast[i] 			),
+					.t_tready				( t_tready[i]			),
+					.t_tvalid				( t_tvalid[i]			),
+
+					.r_tdata				( r_tdata[i]  			),
+					.r_tlast				( r_tlast[i] 			),
+					.r_tvalid				( r_tvalid[i]			),
+					
+					//------------------------------------------ record stream rx
+					.cnv_res_tdata			( cnv_res_tdata[i]		),
+					.cnv_res_tlast			( cnv_res_tlast[i]		),
+					.cnv_res_tready			( cnv_res_tready[i]		),
+					.cnv_res_tvalid			( cnv_res_tvalid[i]		),
+					
+					//------------------------------------------ device spi
+					.cs						( cs_w[i]				),
+					.sclk					( sclk[i]				),
+					.mosi					( mosi[i]				),
+					.miso					( miso[i]				)
+				);
+		end
+	endgenerate
+		
+	eeg_upload# 
+		(
+			.CLK_PERIOD				( CLK_PERIOD			),
+			.CHIPSET_QTY			( SPIS_QTY				),
+			.CH_OF_CHIPSET			( CHIPSET_CH_QTY*SPI_SLAVE_QTY	)
+		)
+	u_eeg_upload
+		(
+			.clk					( clk					),
+			.rst_n					( rst_n					),
+
+			.trans_round			( upload_round[0]		),
+			
+			.cnv_res_tdata_array	( cnv_res_tdata_array	),
+			.cnv_res_tlast_array	( cnv_res_tlast_array	),
+			.cnv_res_tready_array	( cnv_res_tready_array	),
+			.cnv_res_tvalid_array	( cnv_res_tvalid_array	),
+			
+			.axi_str_rxd_tdata		( axis_record_tdata		),
+			.axi_str_rxd_tlast		( axis_record_tlast		),
+			.axi_str_rxd_tready		( axis_record_tready	),
+			.axi_str_rxd_tvalid		( axis_record_tvalid	)
+		);
+	
+	//*****************************************************************************
+	// Procedural blocks
+	//*****************************************************************************
+	
+	
+	//*****************************************************************************
+	// Wire assignment
+	//*****************************************************************************
+	assign record_enable = eeg_cr[31];
+
+	assign start = {cnv_start[0],cnv_start[0]};
+
+	generate
+		for(i=0;i<SPIS_QTY;i=i+1) begin : mapping
+			assign send_enable[i] 	= eeg_er[i];
+
+			assign send_cs_n[i] 	= {6'd0, eeg_cr[5*i+1:5*i+0]};//[4*i+1:4*i+0]
+			assign send_length[i] 	= {5'd0, eeg_cr[5*i+4:5*i+2]};//[4*i+3:4*i+2]
+
+			assign send_data_array[i] = eeg_tr_array[32*i+31:32*i];
+			assign eeg_rr_array[32*i+31:32*i] = recv_data_array[i];
+
+			assign cs[SPI_SLAVE_QTY*(i+1)-1 : SPI_SLAVE_QTY*i] = cs_w[i];
+			assign cnv_drdy[i] = drdy[i];
+			
+			assign cnv_res_tdata_array[32*i+31 : 32*i] 	= cnv_res_tdata[i];
+			assign cnv_res_tlast_array[i]				= cnv_res_tlast[i];
+			assign cnv_res_tvalid_array[i]				= cnv_res_tvalid[i];
+			assign cnv_res_tready[i] = cnv_res_tready_array[i];
+		end
+	endgenerate
+
+	assign interrupt = 1'b0;
+
+	assign debug_sig[0] = record_enable;
+	assign debug_sig[1] = 1'b0;
+	assign debug_sig[2] = 1'b0;
+	assign debug_sig[3] = 1'b0;
+	
+endmodule