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`timescale 1 ns / 1 ps
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//------------------------------------------------------------------------------
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// csi040_ctrl 的自检查 testbench。
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//
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// 这个 testbench 驱动 BRAM 风格控制口，监视 DUT 产生的 SPI 总线，
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// 并检查每个期望的 32 bit 单字节 SPI 帧：
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// [opcode][addr high][addr low][data]
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//
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// ASIC SO 只做了最小模型，用于 direct read 测试：
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// 在读帧的 payload byte 阶段返回 read_response。
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//------------------------------------------------------------------------------
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module csi040_ctrl_tb;
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localparam CLK_PERIOD = 10;
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// DUT 寄存器总线和 ASIC 侧引脚。
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reg clk;
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reg rst_n;
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reg [12:0] bram_addr;
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reg [31:0] bram_din;
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wire [31:0] bram_dout;
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reg bram_en;
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reg [3:0] bram_we;
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wire busy;
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wire spi_done;
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wire error_busy;
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wire asic_rst_n;
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wire asic_trig;
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wire asic_csn;
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wire asic_sck;
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wire asic_si;
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reg asic_so;
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// SPI monitor 状态。CSN 为低时，shift_in 捕获 SI bit。
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integer bit_cnt;
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integer frame_bits;
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reg [31:0] shift_in;
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reg [31:0] frame_in;
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reg [7:0] read_response;
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// 使用较小分频和常见 0x02/0x03 opcode，让仿真更短，
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// 波形里的 SPI 帧也更好读。
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csi040_ctrl#
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(
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.SPI_CLK_DIV ( 2 ),
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.SPI_OPCODE_WRITE ( 8'h02 ),
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.SPI_OPCODE_READ ( 8'h03 )
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)
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dut
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.bram_addr ( bram_addr ),
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.bram_clk ( clk ),
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.bram_din ( bram_din ),
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.bram_dout ( bram_dout ),
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.bram_en ( bram_en ),
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.bram_rst ( 1'b0 ),
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.bram_we ( bram_we ),
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.busy ( busy ),
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.spi_done ( spi_done ),
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.error_busy ( error_busy ),
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.asic_rst_n ( asic_rst_n ),
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.asic_trig ( asic_trig ),
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.asic_csn ( asic_csn ),
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.asic_sck ( asic_sck ),
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.asic_si ( asic_si ),
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.asic_so ( asic_so )
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);
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// 100 MHz 时钟。
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initial begin
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clk = 1'b0;
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forever #(CLK_PERIOD/2) clk = ~clk;
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end
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// 主定向测试序列。每个 write_bram 要么启动命令，要么更新 shadow 寄存器；
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// 每个 check_next_frame 等待 CSN 拉高，并比较 monitor 捕获到的 SPI bit。
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initial begin
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rst_n = 1'b0;
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bram_addr = 0;
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bram_din = 0;
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bram_en = 1'b0;
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bram_we = 4'h0;
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asic_so = 1'b0;
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read_response = 8'h28;
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#(CLK_PERIOD*8);
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rst_n = 1'b1;
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// CONTROL 写：ASIC register 0x0002 <= 0x10。
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write_bram(13'h0020, 32'h00000010);
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check_next_frame(32'h02000210);
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// CH_ENABLE 写会把 16 bit 拆到 ASIC register 0x0007/0x0008。
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write_bram(13'h0024, 32'h0000A55A);
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check_next_frame(32'h0200075A);
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check_next_frame(32'h020008A5);
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// 通道参数写。ch_index=3，CH_CUR_A offset=1，
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// ASIC 地址 = 0x0010 + 3*0x10 + 1 = 0x0041。
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write_bram(13'h0040, 32'h00000003);
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write_bram(13'h0048, 32'h0000007F);
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check_next_frame(32'h0200417F);
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// DCS 解锁序列：向 key register 0x0009 连续写 3 个魔术字节。
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write_bram(13'h002C, 32'h00000001);
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check_next_frame(32'h02000955);
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check_next_frame(32'h020009B3);
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check_next_frame(32'h0200090A);
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// Direct 方式从 Part ID register 0x011D 读 1 字节。
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// 下面的 ASIC 模型返回 0x28，随后通过 BRAM 读 SPI_RDATA 检查。
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write_bram(13'h0008, 32'h0000011D);
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write_bram(13'h0010, 32'h00000100);
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check_next_frame(32'h03011D00);
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read_bram(13'h0014);
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if (bram_dout[7:0] !== 8'h28) begin
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$display("ERROR read data expected 28 got %h", bram_dout[7:0]);
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$stop;
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end
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#(CLK_PERIOD*20);
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$finish;
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end
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// CSN 拉低时，开始捕获一帧新的 SPI。
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always @(negedge asic_csn) begin
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bit_cnt <= 0;
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shift_in <= 0;
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end
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// CSN 拉高时，锁存刚捕获完的一帧。
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always @(posedge asic_csn) begin
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frame_in <= shift_in;
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frame_bits <= bit_cnt;
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end
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// SPI monitor：CSN 有效期间，在 SCK 上升沿采样 MOSI/SI。
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always @(posedge asic_sck) begin
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if (!asic_csn) begin
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shift_in <= {shift_in[30:0], asic_si};
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bit_cnt <= bit_cnt + 1;
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end
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end
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// 最小 ASIC 读模型。对当前 32 bit 测试帧来说，bit 24..31 是返回数据字节。
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// 在下降沿驱动 SO，保证 DUT 在之后的上升沿能采到。
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always @(negedge asic_sck) begin
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if (!asic_csn && (bit_cnt >= 24) && (bit_cnt < 32))
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asic_so <= read_response[31-bit_cnt];
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else
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asic_so <= 1'b0;
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end
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// 整字 BRAM 写 helper。先等待 DUT 空闲，避免定向测试误触发 busy-error。
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task write_bram;
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input [12:0] addr;
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input [31:0] data;
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begin
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wait(busy == 1'b0);
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@(negedge clk);
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bram_addr = addr;
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bram_din = data;
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bram_en = 1'b1;
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bram_we = 4'hF;
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@(posedge clk);
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@(negedge clk);
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bram_en = 1'b0;
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bram_we = 4'h0;
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end
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endtask
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// BRAM 读 helper。bram_en 为高且 bram_we 为 0 的时钟沿更新 bram_dout。
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task read_bram;
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input [12:0] addr;
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begin
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@(negedge clk);
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bram_addr = addr;
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bram_din = 0;
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bram_en = 1'b1;
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bram_we = 4'h0;
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@(posedge clk);
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@(negedge clk);
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bram_en = 1'b0;
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end
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endtask
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// 等待下一帧 SPI 完成，并和期望的 32 bit 单字节帧比较。
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task check_next_frame;
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input [31:0] expected;
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begin
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@(posedge asic_csn);
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#(CLK_PERIOD/2);
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if (frame_bits != 32) begin
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$display("ERROR frame expected 32 bits got %0d bits", frame_bits);
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$stop;
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end
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if (frame_in !== expected) begin
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$display("ERROR frame expected %h got %h", expected, frame_in);
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$stop;
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end
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end
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endtask
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endmodule
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