sync chunk 11/12

2026-09-11 16:18:36 +08:00
parent c315cef09e
commit c2c1bb2648
922 changed files with 102283 additions and 6793 deletions
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+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2023.1 (64-bit)
+REM
+REM Filename    : compile.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Thu Sep 03 09:56:46 +0800 2026
+REM SW Build 3865809 on Sun May  7 15:05:29 MDT 2023
+REM
+REM IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+REM compile Verilog/System Verilog design sources
+echo "xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
+call xvlog  --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj -log xvlog.log
+call type xvlog.log > compile.log
+REM compile VHDL design sources
+echo "xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
+call xvhdl  --incr --relax -prj pl_top_tb_vhdl.prj -log xvhdl.log
+call type xvhdl.log >> compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0