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@echo off
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REM ****************************************************************************
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REM Vivado (TM) v2023.1 (64-bit)
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REM
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REM Filename : compile.bat
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REM Simulator : Xilinx Vivado Simulator
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REM Description : Script for compiling the simulation design source files
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REM
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REM Generated by Vivado on Thu Sep 03 09:56:46 +0800 2026
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REM SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
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REM
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REM IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
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REM
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REM usage: compile.bat
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REM
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REM ****************************************************************************
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REM compile Verilog/System Verilog design sources
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echo "xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
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call xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj -log xvlog.log
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call type xvlog.log > compile.log
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REM compile VHDL design sources
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echo "xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
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call xvhdl --incr --relax -prj pl_top_tb_vhdl.prj -log xvhdl.log
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call type xvhdl.log >> compile.log
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if "%errorlevel%"=="1" goto END
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if "%errorlevel%"=="0" goto SUCCESS
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:END
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exit 1
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:SUCCESS
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exit 0
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@@ -0,0 +1,143 @@
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a
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INFO: [VRFC 10-311] analyzing module clk_map_imp_MO2W24
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INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_1AX6TQV
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INFO: [VRFC 10-311] analyzing module m00_nodes_imp_1X4T3QZ
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INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_BPMQL0
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INFO: [VRFC 10-311] analyzing module s00_nodes_imp_HMS2Z2
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INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_1D6QMRK
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INFO: [VRFC 10-311] analyzing module s01_nodes_imp_193AQ2G
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INFO: [VRFC 10-311] analyzing module switchboards_imp_NFUYHM
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_smartconnect_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_xlconcat_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/accel/accel_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module accel_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_arrange
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_spi
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module breath_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_wrapper
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_emg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pwm_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/run_time.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module run_time
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_intan
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_ql
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_sort
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/c64pro_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module c64pro_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_ch_map
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_monitor
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module acq_collect
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/stim_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module stim_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module spi_full_duplex_master_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb_stim
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module sine_gen_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trigger_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module channel_switch_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module adg1414_if_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module transmit_config_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" into library xil_defaultlib
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||||
INFO: [VRFC 10-311] analyzing module cnv_res_collect_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trans_timer_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v:18]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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||||
WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v:18]
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||||
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_cdc_sync_rst
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||||
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0
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||||
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1
|
||||
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1
|
||||
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_axis
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||||
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_base
|
||||
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_reg_bit
|
||||
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_rst
|
||||
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_memory_base
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||||
INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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||||
INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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||||
WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v:58]
|
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module glbl
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'glbl' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v:6]
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_cdc_sync_rst'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0\'
|
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0\'
|
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1\'
|
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1\'
|
||||
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_reg_bit'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_rst'
|
||||
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_memory_base'
|
||||
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_base'
|
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_axis'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
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@@ -0,0 +1,25 @@
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||||
@echo off
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||||
REM ****************************************************************************
|
||||
REM Vivado (TM) v2023.1 (64-bit)
|
||||
REM
|
||||
REM Filename : elaborate.bat
|
||||
REM Simulator : Xilinx Vivado Simulator
|
||||
REM Description : Script for elaborating the compiled design
|
||||
REM
|
||||
REM Generated by Vivado on Thu Sep 03 09:56:56 +0800 2026
|
||||
REM SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
|
||||
REM
|
||||
REM IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
|
||||
REM
|
||||
REM usage: elaborate.bat
|
||||
REM
|
||||
REM ****************************************************************************
|
||||
REM elaborate design
|
||||
echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log"
|
||||
call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
|
||||
if "%errorlevel%"=="0" goto SUCCESS
|
||||
if "%errorlevel%"=="1" goto END
|
||||
:END
|
||||
exit 1
|
||||
:SUCCESS
|
||||
exit 0
|
||||
@@ -0,0 +1,127 @@
|
||||
Vivado Simulator v2023.1
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2023.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
Pass Through NonSizing Optimizer
|
||||
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_sclk' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:422]
|
||||
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:423]
|
||||
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:424]
|
||||
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_drdy_n' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:425]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'eeg_ads1299_start' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:426]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_tr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_rr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:124]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cnv' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'sck' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:514]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:515]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'debug_sig' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:521]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 64 for port 'probe_in2' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:292]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:626]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:630]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:632]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:640]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:642]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:678]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:682]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:684]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:692]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:694]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'accel_data' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:696]
|
||||
WARNING: [VRFC 10-5021] port 'bram_cur_addr' is not connected on this instance [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:329]
|
||||
WARNING: [VRFC 10-3705] select index 4 into 'emg_ads1299_drdy_w' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1514]
|
||||
WARNING: [VRFC 10-3705] select index 4 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1520]
|
||||
WARNING: [VRFC 10-3705] select index 6 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1521]
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
|
||||
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
|
||||
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
|
||||
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
|
||||
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
|
||||
Compiling module xpm.xpm_fifo_reg_bit
|
||||
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=6...
|
||||
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
|
||||
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
|
||||
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
|
||||
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=3...
|
||||
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=32,USE_...
|
||||
Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
|
||||
Compiling module xil_defaultlib.axis_data_fifo_w32_d32
|
||||
Compiling module xil_defaultlib.eeg_config(SPIS_QTY=2)
|
||||
Compiling module xil_defaultlib.ads1299_arrange_default
|
||||
Compiling module xil_defaultlib.ads1299_spi(NO_OF_SLAVES=2)
|
||||
Compiling module xil_defaultlib.ads1299_if
|
||||
Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=2)
|
||||
Compiling module xil_defaultlib.eeg_top_default
|
||||
Compiling module xil_defaultlib.ads1299_spi_default
|
||||
Compiling module xil_defaultlib.ads1299_if(SPI_SLAVE_QTY=1)
|
||||
Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=1)
|
||||
Compiling module xil_defaultlib.eeg_top1(CHIPSET_QTY=1,SPIS_QTY=...
|
||||
Compiling module xil_defaultlib.cur_mon_config(CH_QTY=16)
|
||||
Compiling module xil_defaultlib.ad7689_dual_ctrl(CLK_PERIOD=500)
|
||||
Compiling module xil_defaultlib.ad7689_dual_if(CLK_PERIOD=500)
|
||||
Compiling module xil_defaultlib.acq_collect(CLK_PERIOD=500,SPI_Q...
|
||||
Compiling module xil_defaultlib.cur_ch_map(CLK_PERIOD=500,CH_QTY...
|
||||
Compiling module unisims_ver.GND
|
||||
Compiling module unisims_ver.FDRE_default
|
||||
Compiling module unisims_ver.CARRY4
|
||||
Compiling module unisims_ver.x_lut2_mux4
|
||||
Compiling module unisims_ver.LUT2
|
||||
Compiling module xil_defaultlib.c_add_s16_s32
|
||||
Compiling module xil_defaultlib.cur_monitor(CLK_PERIOD=500,CH_QT...
|
||||
Compiling module unisims_ver.LUT5
|
||||
Compiling module unisims_ver.LUT6
|
||||
Compiling module unisims_ver.LUT4
|
||||
Compiling module unisims_ver.x_lut1_mux2
|
||||
Compiling module unisims_ver.LUT1
|
||||
Compiling module unisims_ver.x_lut3_mux8
|
||||
Compiling module unisims_ver.LUT3
|
||||
Compiling module unisims_ver.MUXF8
|
||||
Compiling module unisims_ver.MUXF7
|
||||
Compiling module xil_defaultlib.vio_cur_flt_state
|
||||
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray
|
||||
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray__2
|
||||
Compiling module unisims_ver.FDSE_default
|
||||
Compiling module unisims_ver.SRL16E_default
|
||||
Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
|
||||
Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=36,READ_WI...
|
||||
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single
|
||||
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single_...
|
||||
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
|
||||
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
|
||||
Compiling module xil_defaultlib.fifo_generator_1
|
||||
Compiling module xil_defaultlib.cur_mon_top(CLK_PERIOD=500)
|
||||
Compiling module xil_defaultlib.accel_top
|
||||
Compiling module xil_defaultlib.run_time_default
|
||||
Compiling module xil_defaultlib.upload_config(PRE_MSG_LEN=128)
|
||||
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
|
||||
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
|
||||
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
|
||||
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
|
||||
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
|
||||
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
|
||||
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
|
||||
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=128,TDA...
|
||||
Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
|
||||
Compiling module xil_defaultlib.axis_data_fifo_w8_d128
|
||||
Compiling module xil_defaultlib.upload_sort_default
|
||||
Compiling module xil_defaultlib.upload_protocol_ql_default
|
||||
Compiling module xil_defaultlib.upload_protocol_intan
|
||||
Compiling module xil_defaultlib.upload_top
|
||||
Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_sync_stag...
|
||||
Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_bhv_ver_a...
|
||||
Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_CONV_VER(...
|
||||
Compiling module fifo_generator_v13_2_8.fifo_generator_vlog_beh(C_DATA_C...
|
||||
Compiling module xil_defaultlib.fifo_generator_0
|
||||
Compiling module xil_defaultlib.eeg_emg_upload
|
||||
Compiling module xil_defaultlib.stim_config
|
||||
Compiling module xil_defaultlib.pl_top
|
||||
Compiling module xil_defaultlib.rhs2116_mod
|
||||
Compiling module xil_defaultlib.ads1299_mod
|
||||
Compiling module xil_defaultlib.pl_top_tb
|
||||
Compiling module xil_defaultlib.glbl
|
||||
Built simulation snapshot pl_top_tb_behav
|
||||
@@ -0,0 +1,84 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
@@ -0,0 +1,256 @@
|
||||
001
|
||||
008
|
||||
008
|
||||
008
|
||||
000
|
||||
008
|
||||
000
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
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|
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|
||||
118
|
||||
918
|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
||||
DC8
|
||||
001
|
||||
001
|
||||
308
|
||||
318
|
||||
001
|
||||
DD8
|
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|
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|
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|
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|
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018
|
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001
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|
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|
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|
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|
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588
|
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598
|
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|
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|
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|
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|
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|
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|
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000
|
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|
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|
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|
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|
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|
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|
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000
|
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|
||||
328
|
||||
338
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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018
|
||||
001
|
||||
001
|
||||
001
|
||||
118
|
||||
918
|
||||
118
|
||||
818
|
||||
000
|
||||
001
|
||||
001
|
||||
001
|
||||
001
|
||||
000
|
||||
001
|
||||
5C8
|
||||
5D8
|
||||
001
|
||||
001
|
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|
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|
||||
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|
||||
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|
||||
001
|
||||
001
|
||||
@@ -0,0 +1,256 @@
|
||||
000000000000
|
||||
000000001000
|
||||
100100001000
|
||||
000000001000
|
||||
000000000000
|
||||
000000001000
|
||||
000000000000
|
||||
000000000001
|
||||
000000000001
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000000000001
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000000000001
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||||
000000000001
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||||
100100011000
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||||
000000001000
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000000000001
|
||||
000000001000
|
||||
000000001000
|
||||
000000001000
|
||||
000000000000
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000000000001
|
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000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000001000
|
||||
000000011000
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000100011000
|
||||
100100011000
|
||||
100100011000
|
||||
000000000001
|
||||
000000001000
|
||||
100000001000
|
||||
000000001000
|
||||
000000000001
|
||||
100000001000
|
||||
000000000000
|
||||
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|
||||
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|
||||
000000000001
|
||||
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|
||||
000000001000
|
||||
000000000001
|
||||
000000000001
|
||||
110111001000
|
||||
000000000001
|
||||
000000000001
|
||||
001100001000
|
||||
001100011000
|
||||
000000000001
|
||||
110111011000
|
||||
000000000001
|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
000000000001
|
||||
000000001000
|
||||
000000000001
|
||||
000000011000
|
||||
000000000001
|
||||
000000000001
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
000000000000
|
||||
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|
||||
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|
||||
000000000001
|
||||
000000000001
|
||||
010110001000
|
||||
010110011000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
000000011000
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000100011000
|
||||
100100011000
|
||||
000100011000
|
||||
100000011000
|
||||
000000000000
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000000
|
||||
000000000001
|
||||
010111001000
|
||||
010111011000
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
000000000001
|
||||
000000000001
|
||||
000000000001
|
||||
@@ -0,0 +1,11 @@
|
||||
set curr_wave [current_wave_config]
|
||||
if { [string length $curr_wave] == 0 } {
|
||||
if { [llength [get_objects]] > 0} {
|
||||
add_wave /
|
||||
set_property needs_save false [current_wave_config]
|
||||
} else {
|
||||
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
}
|
||||
}
|
||||
|
||||
run 1000ns
|
||||
Binary file not shown.
@@ -0,0 +1,32 @@
|
||||
# compile vhdl design source files
|
||||
vhdl xil_defaultlib \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/sim/design_a9_1_CHANN_EN_1.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/sim/design_a9_1_CHANN_EN_2.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/sim/design_a9_1_STIM_SPI_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/sim/design_a9_1_ZCHECK_SPI_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/sim/design_a9_1_axi_dma_2_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/sim/design_a9_1_axi_dma_1_1.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/sim/design_a9_1_axi_bram_ctrl_0_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/sim/design_a9_1_axi_bram_ctrl_1_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/sim/design_a9_1_axi_bram_ctrl_2_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/sim/design_a9_1_axi_bram_ctrl_3_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/sim/design_a9_1_axi_bram_ctrl_4_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/sim/design_a9_1_axi_dma_0_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/sim/design_a9_1_axi_dma_1_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/sim/design_a9_1_axi_gpio_0_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/sim/bd_6e35_psr_aclk_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/sim/design_a9_1_rst_ps7_0_50M_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/sim/bd_962a_psr_aclk_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/sim/design_a9_1_axi_gpio_1_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/sim/design_a9_1_CHANN_EN_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/sim/design_a9_1_CHANN_SEL_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/sim/design_a9_1_axi_quad_spi_0_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_1/sim/design_a9_1_axi_bram_ctrl_3_1.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_Z_IO_0/sim/design_a9_1_Z_IO_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_5_0/sim/design_a9_1_axi_bram_ctrl_5_0.vhd" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_6_0/sim/design_a9_1_axi_bram_ctrl_6_0.vhd" \
|
||||
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.vhdl" \
|
||||
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" \
|
||||
|
||||
# Do not sort compile order
|
||||
nosort
|
||||
@@ -0,0 +1,369 @@
|
||||
# compile verilog/system verilog design source files
|
||||
verilog xil_defaultlib --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" --include "../../../../c64_pro.ip_user_files/ipstatic/hdl" --include "C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/sim/design_a9_1_processing_system7_0_0.v" \
|
||||
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/sim/axis_data_fifo_w8_d128.v" \
|
||||
"../../../../c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v" \
|
||||
"../../../../LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_sim_netlist.v" \
|
||||
"../../../../LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_sim_netlist.v" \
|
||||
"../../../../LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32_sim_netlist.v" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_2_0/sim/design_a9_1_axis_data_fifo_2_0.v" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_1/sim/design_a9_1_axis_data_fifo_1_1.v" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_0/sim/bd_6e35_one_0.v" \
|
||||
|
||||
sv xil_defaultlib --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" --include "../../../../c64_pro.ip_user_files/ipstatic/hdl" --include "C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_2/sim/bd_6e35_arinsw_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_3/sim/bd_6e35_rinsw_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_4/sim/bd_6e35_awinsw_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_5/sim/bd_6e35_winsw_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_6/sim/bd_6e35_binsw_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_7/sim/bd_6e35_arni_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_8/sim/bd_6e35_rni_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_9/sim/bd_6e35_awni_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_10/sim/bd_6e35_wni_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_11/sim/bd_6e35_bni_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_12/sim/bd_6e35_arni_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_13/sim/bd_6e35_rni_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_14/sim/bd_6e35_awni_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_15/sim/bd_6e35_wni_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_16/sim/bd_6e35_bni_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_17/sim/bd_6e35_arni_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_18/sim/bd_6e35_rni_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_19/sim/bd_6e35_awni_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_20/sim/bd_6e35_wni_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_21/sim/bd_6e35_bni_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_22/sim/bd_6e35_arni_3.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_23/sim/bd_6e35_rni_3.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_24/sim/bd_6e35_awni_3.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_25/sim/bd_6e35_wni_3.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_26/sim/bd_6e35_bni_3.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_27/sim/bd_6e35_arni_4.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_28/sim/bd_6e35_rni_4.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_29/sim/bd_6e35_awni_4.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_30/sim/bd_6e35_wni_4.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_31/sim/bd_6e35_bni_4.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_32/sim/bd_6e35_arni_5.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_33/sim/bd_6e35_rni_5.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_34/sim/bd_6e35_awni_5.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_35/sim/bd_6e35_wni_5.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_36/sim/bd_6e35_bni_5.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_37/sim/bd_6e35_arni_6.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_38/sim/bd_6e35_rni_6.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_39/sim/bd_6e35_awni_6.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_40/sim/bd_6e35_wni_6.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_41/sim/bd_6e35_bni_6.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_42/sim/bd_6e35_arni_7.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_43/sim/bd_6e35_rni_7.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_44/sim/bd_6e35_awni_7.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_45/sim/bd_6e35_wni_7.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_46/sim/bd_6e35_bni_7.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_47/sim/bd_6e35_arinsw_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_48/sim/bd_6e35_rinsw_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_49/sim/bd_6e35_awinsw_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_50/sim/bd_6e35_winsw_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_51/sim/bd_6e35_binsw_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_52/sim/bd_6e35_arinsw_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_53/sim/bd_6e35_rinsw_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_54/sim/bd_6e35_awinsw_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_55/sim/bd_6e35_winsw_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_56/sim/bd_6e35_binsw_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_57/sim/bd_6e35_arinsw_3.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_58/sim/bd_6e35_rinsw_3.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_59/sim/bd_6e35_awinsw_3.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_60/sim/bd_6e35_winsw_3.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_61/sim/bd_6e35_binsw_3.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_62/sim/bd_6e35_arinsw_4.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_63/sim/bd_6e35_rinsw_4.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_64/sim/bd_6e35_awinsw_4.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_65/sim/bd_6e35_winsw_4.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_66/sim/bd_6e35_binsw_4.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_67/sim/bd_6e35_arinsw_5.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_68/sim/bd_6e35_rinsw_5.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_69/sim/bd_6e35_awinsw_5.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_70/sim/bd_6e35_winsw_5.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_71/sim/bd_6e35_binsw_5.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_72/sim/bd_6e35_arinsw_6.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_73/sim/bd_6e35_rinsw_6.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_74/sim/bd_6e35_awinsw_6.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_75/sim/bd_6e35_winsw_6.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_76/sim/bd_6e35_binsw_6.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_77/sim/bd_6e35_arinsw_7.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_78/sim/bd_6e35_rinsw_7.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_79/sim/bd_6e35_awinsw_7.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_80/sim/bd_6e35_winsw_7.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_81/sim/bd_6e35_binsw_7.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_82/sim/bd_6e35_arinsw_8.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_83/sim/bd_6e35_rinsw_8.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_84/sim/bd_6e35_awinsw_8.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_85/sim/bd_6e35_winsw_8.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_86/sim/bd_6e35_binsw_8.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_87/sim/bd_6e35_s00mmu_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_88/sim/bd_6e35_s00tr_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_89/sim/bd_6e35_s00sic_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_90/sim/bd_6e35_s00a2s_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_91/sim/bd_6e35_sarn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_92/sim/bd_6e35_srn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_93/sim/bd_6e35_sawn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_94/sim/bd_6e35_swn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_95/sim/bd_6e35_sbn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_96/sim/bd_6e35_m00s2a_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_97/sim/bd_6e35_m00arn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_98/sim/bd_6e35_m00rn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_99/sim/bd_6e35_m00awn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_100/sim/bd_6e35_m00wn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_101/sim/bd_6e35_m00bn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_102/sim/bd_6e35_m00e_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_103/sim/bd_6e35_m01s2a_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_104/sim/bd_6e35_m01arn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_105/sim/bd_6e35_m01rn_0.sv" \
|
||||
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|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_213/sim/bd_6e35_m16bn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_214/sim/bd_6e35_m16e_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_215/sim/bd_6e35_m17s2a_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_216/sim/bd_6e35_m17arn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_217/sim/bd_6e35_m17rn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_218/sim/bd_6e35_m17awn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_219/sim/bd_6e35_m17wn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_220/sim/bd_6e35_m17bn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_221/sim/bd_6e35_m17e_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_222/sim/bd_6e35_m18s2a_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_223/sim/bd_6e35_m18arn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_224/sim/bd_6e35_m18rn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_225/sim/bd_6e35_m18awn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_226/sim/bd_6e35_m18wn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_227/sim/bd_6e35_m18bn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_228/sim/bd_6e35_m18e_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_229/sim/bd_6e35_m19s2a_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_230/sim/bd_6e35_m19arn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_231/sim/bd_6e35_m19rn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_232/sim/bd_6e35_m19awn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_233/sim/bd_6e35_m19wn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_234/sim/bd_6e35_m19bn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_235/sim/bd_6e35_m19e_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_236/sim/bd_6e35_m20s2a_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_237/sim/bd_6e35_m20arn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_238/sim/bd_6e35_m20rn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_239/sim/bd_6e35_m20awn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_240/sim/bd_6e35_m20wn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_241/sim/bd_6e35_m20bn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_242/sim/bd_6e35_m20e_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_243/sim/bd_6e35_m21s2a_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_244/sim/bd_6e35_m21arn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_245/sim/bd_6e35_m21rn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_246/sim/bd_6e35_m21awn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_247/sim/bd_6e35_m21wn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_248/sim/bd_6e35_m21bn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_249/sim/bd_6e35_m21e_0.sv" \
|
||||
|
||||
verilog xil_defaultlib --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" --include "../../../../c64_pro.ip_user_files/ipstatic/hdl" --include "C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/sim/bd_6e35.v" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/sim/design_a9_1_axi_smc_0.v" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/sim/design_a9_1_axis_data_fifo_0_0.v" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/sim/design_a9_1_axis_data_fifo_1_0.v" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_0/sim/bd_962a_one_0.v" \
|
||||
|
||||
sv xil_defaultlib --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" --include "../../../../c64_pro.ip_user_files/ipstatic/hdl" --include "C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_2/sim/bd_962a_arsw_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_3/sim/bd_962a_rsw_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_4/sim/bd_962a_awsw_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_5/sim/bd_962a_wsw_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_6/sim/bd_962a_bsw_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_7/sim/bd_962a_s00mmu_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_8/sim/bd_962a_s00tr_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_9/sim/bd_962a_s00sic_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_10/sim/bd_962a_s00a2s_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_11/sim/bd_962a_sarn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_12/sim/bd_962a_srn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_13/sim/bd_962a_s01mmu_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_14/sim/bd_962a_s01tr_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_15/sim/bd_962a_s01sic_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_16/sim/bd_962a_s01a2s_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_17/sim/bd_962a_sawn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_18/sim/bd_962a_swn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_19/sim/bd_962a_sbn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_20/sim/bd_962a_s02mmu_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_21/sim/bd_962a_s02tr_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_22/sim/bd_962a_s02sic_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_23/sim/bd_962a_s02a2s_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_24/sim/bd_962a_sawn_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_25/sim/bd_962a_swn_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_26/sim/bd_962a_sbn_1.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_27/sim/bd_962a_s03mmu_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_28/sim/bd_962a_s03tr_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_29/sim/bd_962a_s03sic_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_30/sim/bd_962a_s03a2s_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_31/sim/bd_962a_sawn_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_32/sim/bd_962a_swn_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_33/sim/bd_962a_sbn_2.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_34/sim/bd_962a_m00s2a_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_35/sim/bd_962a_m00arn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_36/sim/bd_962a_m00rn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_37/sim/bd_962a_m00awn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_38/sim/bd_962a_m00wn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_39/sim/bd_962a_m00bn_0.sv" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_40/sim/bd_962a_m00e_0.sv" \
|
||||
|
||||
verilog xil_defaultlib --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" --include "../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" --include "../../../../c64_pro.ip_user_files/ipstatic/hdl" --include "C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" \
|
||||
"../../../../c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/accel/accel_top.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" \
|
||||
"../../../../c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/led_ctrl.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/pl_top.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/utils/run_time.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/upload/upload_config.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/upload/upload_top.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/c64pro_top.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/stim_config.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/pl_top_tb.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" \
|
||||
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" \
|
||||
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" \
|
||||
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" \
|
||||
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" \
|
||||
"../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" \
|
||||
|
||||
# compile glbl module
|
||||
verilog xil_defaultlib "glbl.v"
|
||||
|
||||
# Do not sort compile order
|
||||
nosort
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,961 @@
|
||||
NUM_SI 1
|
||||
NUM_MI 22
|
||||
NUM_CLKS 1
|
||||
S00_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
S00_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
S00_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
S00_AXI.CONFIG.DATA_WIDTH 32
|
||||
S00_AXI.CONFIG.DATAWIDTH 32
|
||||
S00_AXI.CONFIG.PROTOCOL AXI3
|
||||
S00_AXI.CONFIG.FREQ_HZ 100000000
|
||||
S00_AXI.CONFIG.ID_WIDTH 12
|
||||
S00_AXI.CONFIG.ADDR_WIDTH 32
|
||||
S00_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.WUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.RUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.BUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
S00_AXI.CONFIG.HAS_BURST 1
|
||||
S00_AXI.CONFIG.HAS_LOCK 1
|
||||
S00_AXI.CONFIG.HAS_PROT 1
|
||||
S00_AXI.CONFIG.HAS_CACHE 1
|
||||
S00_AXI.CONFIG.HAS_QOS 1
|
||||
S00_AXI.CONFIG.HAS_REGION 0
|
||||
S00_AXI.CONFIG.HAS_WSTRB 1
|
||||
S00_AXI.CONFIG.HAS_BRESP 1
|
||||
S00_AXI.CONFIG.HAS_RRESP 1
|
||||
S00_AXI.CONFIG.MAX_BURST_LENGTH 16
|
||||
S00_AXI.CONFIG.PHASE 0.0
|
||||
S00_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
S00_AXI.CONFIG.NUM_READ_THREADS 4
|
||||
S00_AXI.CONFIG.NUM_WRITE_THREADS 4
|
||||
S00_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
S00_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
S00_AXI.CONFIG.INSERT_VIP 0
|
||||
M00_AXI.CONFIG.DATA_WIDTH 32
|
||||
M00_AXI.CONFIG.DATAWIDTH 32
|
||||
M00_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M00_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M00_AXI.CONFIG.ID_WIDTH 0
|
||||
M00_AXI.CONFIG.ADDR_WIDTH 13
|
||||
M00_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M00_AXI.CONFIG.HAS_BURST 0
|
||||
M00_AXI.CONFIG.HAS_LOCK 0
|
||||
M00_AXI.CONFIG.HAS_PROT 1
|
||||
M00_AXI.CONFIG.HAS_CACHE 0
|
||||
M00_AXI.CONFIG.HAS_QOS 0
|
||||
M00_AXI.CONFIG.HAS_REGION 0
|
||||
M00_AXI.CONFIG.HAS_WSTRB 1
|
||||
M00_AXI.CONFIG.HAS_BRESP 1
|
||||
M00_AXI.CONFIG.HAS_RRESP 1
|
||||
M00_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M00_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M00_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M00_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M00_AXI.CONFIG.PHASE 0.0
|
||||
M00_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M00_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M00_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M00_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M00_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M00_AXI.CONFIG.INSERT_VIP 0
|
||||
M01_AXI.CONFIG.DATA_WIDTH 32
|
||||
M01_AXI.CONFIG.DATAWIDTH 32
|
||||
M01_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M01_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M01_AXI.CONFIG.ID_WIDTH 0
|
||||
M01_AXI.CONFIG.ADDR_WIDTH 9
|
||||
M01_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M01_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M01_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M01_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M01_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M01_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M01_AXI.CONFIG.HAS_BURST 0
|
||||
M01_AXI.CONFIG.HAS_LOCK 0
|
||||
M01_AXI.CONFIG.HAS_PROT 0
|
||||
M01_AXI.CONFIG.HAS_CACHE 0
|
||||
M01_AXI.CONFIG.HAS_QOS 0
|
||||
M01_AXI.CONFIG.HAS_REGION 0
|
||||
M01_AXI.CONFIG.HAS_WSTRB 1
|
||||
M01_AXI.CONFIG.HAS_BRESP 1
|
||||
M01_AXI.CONFIG.HAS_RRESP 1
|
||||
M01_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M01_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M01_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M01_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M01_AXI.CONFIG.PHASE 0.0
|
||||
M01_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M01_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M01_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M01_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M01_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M01_AXI.CONFIG.INSERT_VIP 0
|
||||
M02_AXI.CONFIG.DATA_WIDTH 32
|
||||
M02_AXI.CONFIG.DATAWIDTH 32
|
||||
M02_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M02_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M02_AXI.CONFIG.ID_WIDTH 0
|
||||
M02_AXI.CONFIG.ADDR_WIDTH 13
|
||||
M02_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M02_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M02_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M02_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M02_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M02_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M02_AXI.CONFIG.HAS_BURST 0
|
||||
M02_AXI.CONFIG.HAS_LOCK 0
|
||||
M02_AXI.CONFIG.HAS_PROT 1
|
||||
M02_AXI.CONFIG.HAS_CACHE 0
|
||||
M02_AXI.CONFIG.HAS_QOS 0
|
||||
M02_AXI.CONFIG.HAS_REGION 0
|
||||
M02_AXI.CONFIG.HAS_WSTRB 1
|
||||
M02_AXI.CONFIG.HAS_BRESP 1
|
||||
M02_AXI.CONFIG.HAS_RRESP 1
|
||||
M02_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M02_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M02_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M02_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M02_AXI.CONFIG.PHASE 0.0
|
||||
M02_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M02_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M02_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M02_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M02_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M02_AXI.CONFIG.INSERT_VIP 0
|
||||
M03_AXI.CONFIG.DATA_WIDTH 32
|
||||
M03_AXI.CONFIG.DATAWIDTH 32
|
||||
M03_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M03_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M03_AXI.CONFIG.ID_WIDTH 0
|
||||
M03_AXI.CONFIG.ADDR_WIDTH 13
|
||||
M03_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M03_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M03_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M03_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M03_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M03_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M03_AXI.CONFIG.HAS_BURST 0
|
||||
M03_AXI.CONFIG.HAS_LOCK 0
|
||||
M03_AXI.CONFIG.HAS_PROT 1
|
||||
M03_AXI.CONFIG.HAS_CACHE 0
|
||||
M03_AXI.CONFIG.HAS_QOS 0
|
||||
M03_AXI.CONFIG.HAS_REGION 0
|
||||
M03_AXI.CONFIG.HAS_WSTRB 1
|
||||
M03_AXI.CONFIG.HAS_BRESP 1
|
||||
M03_AXI.CONFIG.HAS_RRESP 1
|
||||
M03_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M03_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M03_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M03_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M03_AXI.CONFIG.PHASE 0.0
|
||||
M03_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M03_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M03_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M03_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M03_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M03_AXI.CONFIG.INSERT_VIP 0
|
||||
M04_AXI.CONFIG.DATA_WIDTH 32
|
||||
M04_AXI.CONFIG.DATAWIDTH 32
|
||||
M04_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M04_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M04_AXI.CONFIG.ID_WIDTH 0
|
||||
M04_AXI.CONFIG.ADDR_WIDTH 9
|
||||
M04_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M04_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M04_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M04_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M04_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M04_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M04_AXI.CONFIG.HAS_BURST 0
|
||||
M04_AXI.CONFIG.HAS_LOCK 0
|
||||
M04_AXI.CONFIG.HAS_PROT 0
|
||||
M04_AXI.CONFIG.HAS_CACHE 0
|
||||
M04_AXI.CONFIG.HAS_QOS 0
|
||||
M04_AXI.CONFIG.HAS_REGION 0
|
||||
M04_AXI.CONFIG.HAS_WSTRB 1
|
||||
M04_AXI.CONFIG.HAS_BRESP 1
|
||||
M04_AXI.CONFIG.HAS_RRESP 1
|
||||
M04_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M04_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M04_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M04_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M04_AXI.CONFIG.PHASE 0.0
|
||||
M04_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M04_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M04_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M04_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M04_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M04_AXI.CONFIG.INSERT_VIP 0
|
||||
M05_AXI.CONFIG.DATA_WIDTH 32
|
||||
M05_AXI.CONFIG.DATAWIDTH 32
|
||||
M05_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M05_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M05_AXI.CONFIG.ID_WIDTH 0
|
||||
M05_AXI.CONFIG.ADDR_WIDTH 13
|
||||
M05_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M05_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M05_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M05_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M05_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M05_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M05_AXI.CONFIG.HAS_BURST 0
|
||||
M05_AXI.CONFIG.HAS_LOCK 0
|
||||
M05_AXI.CONFIG.HAS_PROT 1
|
||||
M05_AXI.CONFIG.HAS_CACHE 0
|
||||
M05_AXI.CONFIG.HAS_QOS 0
|
||||
M05_AXI.CONFIG.HAS_REGION 0
|
||||
M05_AXI.CONFIG.HAS_WSTRB 1
|
||||
M05_AXI.CONFIG.HAS_BRESP 1
|
||||
M05_AXI.CONFIG.HAS_RRESP 1
|
||||
M05_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M05_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M05_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M05_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M05_AXI.CONFIG.PHASE 0.0
|
||||
M05_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M05_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M05_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M05_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M05_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M05_AXI.CONFIG.INSERT_VIP 0
|
||||
M06_AXI.CONFIG.DATA_WIDTH 32
|
||||
M06_AXI.CONFIG.DATAWIDTH 32
|
||||
M06_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M06_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M06_AXI.CONFIG.ID_WIDTH 0
|
||||
M06_AXI.CONFIG.ADDR_WIDTH 10
|
||||
M06_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M06_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M06_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M06_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M06_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M06_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M06_AXI.CONFIG.HAS_BURST 0
|
||||
M06_AXI.CONFIG.HAS_LOCK 0
|
||||
M06_AXI.CONFIG.HAS_PROT 0
|
||||
M06_AXI.CONFIG.HAS_CACHE 0
|
||||
M06_AXI.CONFIG.HAS_QOS 0
|
||||
M06_AXI.CONFIG.HAS_REGION 0
|
||||
M06_AXI.CONFIG.HAS_WSTRB 0
|
||||
M06_AXI.CONFIG.HAS_BRESP 1
|
||||
M06_AXI.CONFIG.HAS_RRESP 1
|
||||
M06_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M06_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M06_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M06_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M06_AXI.CONFIG.PHASE 0.0
|
||||
M06_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M06_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M06_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M06_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M06_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M06_AXI.CONFIG.INSERT_VIP 0
|
||||
M07_AXI.CONFIG.DATA_WIDTH 32
|
||||
M07_AXI.CONFIG.DATAWIDTH 32
|
||||
M07_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M07_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M07_AXI.CONFIG.ID_WIDTH 0
|
||||
M07_AXI.CONFIG.ADDR_WIDTH 10
|
||||
M07_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M07_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M07_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M07_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M07_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M07_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M07_AXI.CONFIG.HAS_BURST 0
|
||||
M07_AXI.CONFIG.HAS_LOCK 0
|
||||
M07_AXI.CONFIG.HAS_PROT 0
|
||||
M07_AXI.CONFIG.HAS_CACHE 0
|
||||
M07_AXI.CONFIG.HAS_QOS 0
|
||||
M07_AXI.CONFIG.HAS_REGION 0
|
||||
M07_AXI.CONFIG.HAS_WSTRB 0
|
||||
M07_AXI.CONFIG.HAS_BRESP 1
|
||||
M07_AXI.CONFIG.HAS_RRESP 1
|
||||
M07_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M07_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M07_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M07_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M07_AXI.CONFIG.PHASE 0.0
|
||||
M07_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M07_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M07_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M07_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M07_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M07_AXI.CONFIG.INSERT_VIP 0
|
||||
M08_AXI.CONFIG.DATA_WIDTH 32
|
||||
M08_AXI.CONFIG.DATAWIDTH 32
|
||||
M08_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M08_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M08_AXI.CONFIG.ID_WIDTH 0
|
||||
M08_AXI.CONFIG.ADDR_WIDTH 10
|
||||
M08_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M08_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M08_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M08_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M08_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M08_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M08_AXI.CONFIG.HAS_BURST 0
|
||||
M08_AXI.CONFIG.HAS_LOCK 0
|
||||
M08_AXI.CONFIG.HAS_PROT 0
|
||||
M08_AXI.CONFIG.HAS_CACHE 0
|
||||
M08_AXI.CONFIG.HAS_QOS 0
|
||||
M08_AXI.CONFIG.HAS_REGION 0
|
||||
M08_AXI.CONFIG.HAS_WSTRB 0
|
||||
M08_AXI.CONFIG.HAS_BRESP 1
|
||||
M08_AXI.CONFIG.HAS_RRESP 1
|
||||
M08_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M08_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M08_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M08_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M08_AXI.CONFIG.PHASE 0.0
|
||||
M08_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M08_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M08_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M08_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M08_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M08_AXI.CONFIG.INSERT_VIP 0
|
||||
M09_AXI.CONFIG.DATA_WIDTH 32
|
||||
M09_AXI.CONFIG.DATAWIDTH 32
|
||||
M09_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M09_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M09_AXI.CONFIG.ID_WIDTH 0
|
||||
M09_AXI.CONFIG.ADDR_WIDTH 13
|
||||
M09_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M09_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M09_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M09_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M09_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M09_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M09_AXI.CONFIG.HAS_BURST 0
|
||||
M09_AXI.CONFIG.HAS_LOCK 0
|
||||
M09_AXI.CONFIG.HAS_PROT 1
|
||||
M09_AXI.CONFIG.HAS_CACHE 0
|
||||
M09_AXI.CONFIG.HAS_QOS 0
|
||||
M09_AXI.CONFIG.HAS_REGION 0
|
||||
M09_AXI.CONFIG.HAS_WSTRB 1
|
||||
M09_AXI.CONFIG.HAS_BRESP 1
|
||||
M09_AXI.CONFIG.HAS_RRESP 1
|
||||
M09_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M09_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M09_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M09_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M09_AXI.CONFIG.PHASE 0.0
|
||||
M09_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M09_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M09_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M09_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M09_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M09_AXI.CONFIG.INSERT_VIP 0
|
||||
M10_AXI.CONFIG.DATA_WIDTH 32
|
||||
M10_AXI.CONFIG.DATAWIDTH 32
|
||||
M10_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M10_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M10_AXI.CONFIG.ID_WIDTH 0
|
||||
M10_AXI.CONFIG.ADDR_WIDTH 9
|
||||
M10_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M10_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M10_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M10_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M10_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M10_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M10_AXI.CONFIG.HAS_BURST 0
|
||||
M10_AXI.CONFIG.HAS_LOCK 0
|
||||
M10_AXI.CONFIG.HAS_PROT 0
|
||||
M10_AXI.CONFIG.HAS_CACHE 0
|
||||
M10_AXI.CONFIG.HAS_QOS 0
|
||||
M10_AXI.CONFIG.HAS_REGION 0
|
||||
M10_AXI.CONFIG.HAS_WSTRB 1
|
||||
M10_AXI.CONFIG.HAS_BRESP 1
|
||||
M10_AXI.CONFIG.HAS_RRESP 1
|
||||
M10_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M10_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M10_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M10_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M10_AXI.CONFIG.PHASE 0.0
|
||||
M10_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M10_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M10_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M10_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M10_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M10_AXI.CONFIG.INSERT_VIP 0
|
||||
M11_AXI.CONFIG.DATA_WIDTH 32
|
||||
M11_AXI.CONFIG.DATAWIDTH 32
|
||||
M11_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M11_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M11_AXI.CONFIG.ID_WIDTH 0
|
||||
M11_AXI.CONFIG.ADDR_WIDTH 9
|
||||
M11_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M11_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M11_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M11_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M11_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M11_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M11_AXI.CONFIG.HAS_BURST 0
|
||||
M11_AXI.CONFIG.HAS_LOCK 0
|
||||
M11_AXI.CONFIG.HAS_PROT 0
|
||||
M11_AXI.CONFIG.HAS_CACHE 0
|
||||
M11_AXI.CONFIG.HAS_QOS 0
|
||||
M11_AXI.CONFIG.HAS_REGION 0
|
||||
M11_AXI.CONFIG.HAS_WSTRB 1
|
||||
M11_AXI.CONFIG.HAS_BRESP 1
|
||||
M11_AXI.CONFIG.HAS_RRESP 1
|
||||
M11_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M11_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M11_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M11_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M11_AXI.CONFIG.PHASE 0.0
|
||||
M11_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M11_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M11_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M11_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M11_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M11_AXI.CONFIG.INSERT_VIP 0
|
||||
M12_AXI.CONFIG.DATA_WIDTH 32
|
||||
M12_AXI.CONFIG.DATAWIDTH 32
|
||||
M12_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M12_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M12_AXI.CONFIG.ID_WIDTH 0
|
||||
M12_AXI.CONFIG.ADDR_WIDTH 9
|
||||
M12_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M12_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M12_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M12_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M12_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M12_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M12_AXI.CONFIG.HAS_BURST 0
|
||||
M12_AXI.CONFIG.HAS_LOCK 0
|
||||
M12_AXI.CONFIG.HAS_PROT 0
|
||||
M12_AXI.CONFIG.HAS_CACHE 0
|
||||
M12_AXI.CONFIG.HAS_QOS 0
|
||||
M12_AXI.CONFIG.HAS_REGION 0
|
||||
M12_AXI.CONFIG.HAS_WSTRB 1
|
||||
M12_AXI.CONFIG.HAS_BRESP 1
|
||||
M12_AXI.CONFIG.HAS_RRESP 1
|
||||
M12_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M12_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M12_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M12_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M12_AXI.CONFIG.PHASE 0.0
|
||||
M12_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M12_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M12_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M12_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M12_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M12_AXI.CONFIG.INSERT_VIP 0
|
||||
M13_AXI.CONFIG.DATA_WIDTH 32
|
||||
M13_AXI.CONFIG.DATAWIDTH 32
|
||||
M13_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M13_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M13_AXI.CONFIG.ID_WIDTH 0
|
||||
M13_AXI.CONFIG.ADDR_WIDTH 10
|
||||
M13_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M13_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M13_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M13_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M13_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M13_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M13_AXI.CONFIG.HAS_BURST 0
|
||||
M13_AXI.CONFIG.HAS_LOCK 0
|
||||
M13_AXI.CONFIG.HAS_PROT 0
|
||||
M13_AXI.CONFIG.HAS_CACHE 0
|
||||
M13_AXI.CONFIG.HAS_QOS 0
|
||||
M13_AXI.CONFIG.HAS_REGION 0
|
||||
M13_AXI.CONFIG.HAS_WSTRB 0
|
||||
M13_AXI.CONFIG.HAS_BRESP 1
|
||||
M13_AXI.CONFIG.HAS_RRESP 1
|
||||
M13_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M13_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M13_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M13_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M13_AXI.CONFIG.PHASE 0.0
|
||||
M13_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M13_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M13_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M13_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M13_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M13_AXI.CONFIG.INSERT_VIP 0
|
||||
M14_AXI.CONFIG.DATA_WIDTH 32
|
||||
M14_AXI.CONFIG.DATAWIDTH 32
|
||||
M14_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M14_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M14_AXI.CONFIG.ID_WIDTH 0
|
||||
M14_AXI.CONFIG.ADDR_WIDTH 7
|
||||
M14_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M14_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M14_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M14_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M14_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M14_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M14_AXI.CONFIG.HAS_BURST 0
|
||||
M14_AXI.CONFIG.HAS_LOCK 0
|
||||
M14_AXI.CONFIG.HAS_PROT 0
|
||||
M14_AXI.CONFIG.HAS_CACHE 0
|
||||
M14_AXI.CONFIG.HAS_QOS 0
|
||||
M14_AXI.CONFIG.HAS_REGION 0
|
||||
M14_AXI.CONFIG.HAS_WSTRB 1
|
||||
M14_AXI.CONFIG.HAS_BRESP 1
|
||||
M14_AXI.CONFIG.HAS_RRESP 1
|
||||
M14_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M14_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M14_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M14_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M14_AXI.CONFIG.PHASE 0.0
|
||||
M14_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M14_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M14_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M14_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M14_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M14_AXI.CONFIG.INSERT_VIP 0
|
||||
M15_AXI.CONFIG.DATA_WIDTH 32
|
||||
M15_AXI.CONFIG.DATAWIDTH 32
|
||||
M15_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M15_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M15_AXI.CONFIG.ID_WIDTH 0
|
||||
M15_AXI.CONFIG.ADDR_WIDTH 7
|
||||
M15_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M15_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M15_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M15_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M15_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M15_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M15_AXI.CONFIG.HAS_BURST 0
|
||||
M15_AXI.CONFIG.HAS_LOCK 0
|
||||
M15_AXI.CONFIG.HAS_PROT 0
|
||||
M15_AXI.CONFIG.HAS_CACHE 0
|
||||
M15_AXI.CONFIG.HAS_QOS 0
|
||||
M15_AXI.CONFIG.HAS_REGION 0
|
||||
M15_AXI.CONFIG.HAS_WSTRB 1
|
||||
M15_AXI.CONFIG.HAS_BRESP 1
|
||||
M15_AXI.CONFIG.HAS_RRESP 1
|
||||
M15_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M15_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M15_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M15_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M15_AXI.CONFIG.PHASE 0.0
|
||||
M15_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M15_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M15_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M15_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M15_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M15_AXI.CONFIG.INSERT_VIP 0
|
||||
M16_AXI.CONFIG.DATA_WIDTH 32
|
||||
M16_AXI.CONFIG.DATAWIDTH 32
|
||||
M16_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M16_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M16_AXI.CONFIG.ID_WIDTH 0
|
||||
M16_AXI.CONFIG.ADDR_WIDTH 9
|
||||
M16_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M16_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M16_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M16_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M16_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M16_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M16_AXI.CONFIG.HAS_BURST 0
|
||||
M16_AXI.CONFIG.HAS_LOCK 0
|
||||
M16_AXI.CONFIG.HAS_PROT 0
|
||||
M16_AXI.CONFIG.HAS_CACHE 0
|
||||
M16_AXI.CONFIG.HAS_QOS 0
|
||||
M16_AXI.CONFIG.HAS_REGION 0
|
||||
M16_AXI.CONFIG.HAS_WSTRB 1
|
||||
M16_AXI.CONFIG.HAS_BRESP 1
|
||||
M16_AXI.CONFIG.HAS_RRESP 1
|
||||
M16_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M16_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M16_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M16_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M16_AXI.CONFIG.PHASE 0.0
|
||||
M16_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M16_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M16_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M16_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M16_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M16_AXI.CONFIG.INSERT_VIP 0
|
||||
M17_AXI.CONFIG.DATA_WIDTH 32
|
||||
M17_AXI.CONFIG.DATAWIDTH 32
|
||||
M17_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M17_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M17_AXI.CONFIG.ID_WIDTH 0
|
||||
M17_AXI.CONFIG.ADDR_WIDTH 13
|
||||
M17_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M17_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M17_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M17_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M17_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M17_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M17_AXI.CONFIG.HAS_BURST 0
|
||||
M17_AXI.CONFIG.HAS_LOCK 0
|
||||
M17_AXI.CONFIG.HAS_PROT 1
|
||||
M17_AXI.CONFIG.HAS_CACHE 0
|
||||
M17_AXI.CONFIG.HAS_QOS 0
|
||||
M17_AXI.CONFIG.HAS_REGION 0
|
||||
M17_AXI.CONFIG.HAS_WSTRB 1
|
||||
M17_AXI.CONFIG.HAS_BRESP 1
|
||||
M17_AXI.CONFIG.HAS_RRESP 1
|
||||
M17_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M17_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M17_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M17_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M17_AXI.CONFIG.PHASE 0.0
|
||||
M17_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M17_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M17_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M17_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M17_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M17_AXI.CONFIG.INSERT_VIP 0
|
||||
M18_AXI.CONFIG.DATA_WIDTH 32
|
||||
M18_AXI.CONFIG.DATAWIDTH 32
|
||||
M18_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M18_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M18_AXI.CONFIG.ID_WIDTH 0
|
||||
M18_AXI.CONFIG.ADDR_WIDTH 13
|
||||
M18_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M18_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M18_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M18_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M18_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M18_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M18_AXI.CONFIG.HAS_BURST 0
|
||||
M18_AXI.CONFIG.HAS_LOCK 0
|
||||
M18_AXI.CONFIG.HAS_PROT 1
|
||||
M18_AXI.CONFIG.HAS_CACHE 0
|
||||
M18_AXI.CONFIG.HAS_QOS 0
|
||||
M18_AXI.CONFIG.HAS_REGION 0
|
||||
M18_AXI.CONFIG.HAS_WSTRB 1
|
||||
M18_AXI.CONFIG.HAS_BRESP 1
|
||||
M18_AXI.CONFIG.HAS_RRESP 1
|
||||
M18_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M18_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M18_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M18_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M18_AXI.CONFIG.PHASE 0.0
|
||||
M18_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M18_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M18_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M18_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M18_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M18_AXI.CONFIG.INSERT_VIP 0
|
||||
M19_AXI.CONFIG.DATA_WIDTH 32
|
||||
M19_AXI.CONFIG.DATAWIDTH 32
|
||||
M19_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M19_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M19_AXI.CONFIG.ID_WIDTH 0
|
||||
M19_AXI.CONFIG.ADDR_WIDTH 9
|
||||
M19_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M19_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M19_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M19_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M19_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M19_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M19_AXI.CONFIG.HAS_BURST 0
|
||||
M19_AXI.CONFIG.HAS_LOCK 0
|
||||
M19_AXI.CONFIG.HAS_PROT 0
|
||||
M19_AXI.CONFIG.HAS_CACHE 0
|
||||
M19_AXI.CONFIG.HAS_QOS 0
|
||||
M19_AXI.CONFIG.HAS_REGION 0
|
||||
M19_AXI.CONFIG.HAS_WSTRB 1
|
||||
M19_AXI.CONFIG.HAS_BRESP 1
|
||||
M19_AXI.CONFIG.HAS_RRESP 1
|
||||
M19_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M19_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M19_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M19_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M19_AXI.CONFIG.PHASE 0.0
|
||||
M19_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M19_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M19_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M19_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M19_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M19_AXI.CONFIG.INSERT_VIP 0
|
||||
M20_AXI.CONFIG.DATA_WIDTH 32
|
||||
M20_AXI.CONFIG.DATAWIDTH 32
|
||||
M20_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M20_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M20_AXI.CONFIG.ID_WIDTH 0
|
||||
M20_AXI.CONFIG.ADDR_WIDTH 13
|
||||
M20_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M20_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M20_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M20_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M20_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M20_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M20_AXI.CONFIG.HAS_BURST 0
|
||||
M20_AXI.CONFIG.HAS_LOCK 0
|
||||
M20_AXI.CONFIG.HAS_PROT 1
|
||||
M20_AXI.CONFIG.HAS_CACHE 0
|
||||
M20_AXI.CONFIG.HAS_QOS 0
|
||||
M20_AXI.CONFIG.HAS_REGION 0
|
||||
M20_AXI.CONFIG.HAS_WSTRB 1
|
||||
M20_AXI.CONFIG.HAS_BRESP 1
|
||||
M20_AXI.CONFIG.HAS_RRESP 1
|
||||
M20_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M20_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M20_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M20_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M20_AXI.CONFIG.PHASE 0.0
|
||||
M20_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M20_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M20_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M20_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M20_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M20_AXI.CONFIG.INSERT_VIP 0
|
||||
M21_AXI.CONFIG.DATA_WIDTH 32
|
||||
M21_AXI.CONFIG.DATAWIDTH 32
|
||||
M21_AXI.CONFIG.PROTOCOL AXI4LITE
|
||||
M21_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M21_AXI.CONFIG.ID_WIDTH 0
|
||||
M21_AXI.CONFIG.ADDR_WIDTH 7
|
||||
M21_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M21_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M21_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M21_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M21_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M21_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M21_AXI.CONFIG.HAS_BURST 0
|
||||
M21_AXI.CONFIG.HAS_LOCK 0
|
||||
M21_AXI.CONFIG.HAS_PROT 0
|
||||
M21_AXI.CONFIG.HAS_CACHE 0
|
||||
M21_AXI.CONFIG.HAS_QOS 0
|
||||
M21_AXI.CONFIG.HAS_REGION 0
|
||||
M21_AXI.CONFIG.HAS_WSTRB 1
|
||||
M21_AXI.CONFIG.HAS_BRESP 1
|
||||
M21_AXI.CONFIG.HAS_RRESP 1
|
||||
M21_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M21_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M21_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M21_AXI.CONFIG.MAX_BURST_LENGTH 1
|
||||
M21_AXI.CONFIG.PHASE 0.0
|
||||
M21_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M21_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M21_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M21_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M21_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M21_AXI.CONFIG.INSERT_VIP 0
|
||||
M00_AXI.IS_CASCADED 0
|
||||
M01_AXI.IS_CASCADED 0
|
||||
M02_AXI.IS_CASCADED 0
|
||||
M03_AXI.IS_CASCADED 0
|
||||
M04_AXI.IS_CASCADED 0
|
||||
M05_AXI.IS_CASCADED 0
|
||||
M06_AXI.IS_CASCADED 0
|
||||
M07_AXI.IS_CASCADED 0
|
||||
M08_AXI.IS_CASCADED 0
|
||||
M09_AXI.IS_CASCADED 0
|
||||
M10_AXI.IS_CASCADED 0
|
||||
M11_AXI.IS_CASCADED 0
|
||||
M12_AXI.IS_CASCADED 0
|
||||
M13_AXI.IS_CASCADED 0
|
||||
M14_AXI.IS_CASCADED 0
|
||||
M15_AXI.IS_CASCADED 0
|
||||
M16_AXI.IS_CASCADED 0
|
||||
M17_AXI.IS_CASCADED 0
|
||||
M18_AXI.IS_CASCADED 0
|
||||
M19_AXI.IS_CASCADED 0
|
||||
M20_AXI.IS_CASCADED 0
|
||||
M21_AXI.IS_CASCADED 0
|
||||
S00_AXI.IS_CASCADED 0
|
||||
S00_AXI.NUM_SEG 22
|
||||
S00_AXI.SEG000.BASE_ADDR 0x0000000040000000
|
||||
S00_AXI.SEG000.SIZE 13
|
||||
S00_AXI.SEG000.SUPPORTS_READ 1
|
||||
S00_AXI.SEG000.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG000.SECURE_READ 0
|
||||
S00_AXI.SEG000.SECURE_WRITE 0
|
||||
S00_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
|
||||
S00_AXI.SEG000.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG000.DATA_WIDTH 32
|
||||
S00_AXI.SEG001.BASE_ADDR 0x0000000040400000
|
||||
S00_AXI.SEG001.SIZE 16
|
||||
S00_AXI.SEG001.SUPPORTS_READ 1
|
||||
S00_AXI.SEG001.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG001.SECURE_READ 0
|
||||
S00_AXI.SEG001.SECURE_WRITE 0
|
||||
S00_AXI.SEG001.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000111
|
||||
S00_AXI.SEG001.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG001.DATA_WIDTH 32
|
||||
S00_AXI.SEG002.BASE_ADDR 0x0000000040410000
|
||||
S00_AXI.SEG002.SIZE 16
|
||||
S00_AXI.SEG002.SUPPORTS_READ 1
|
||||
S00_AXI.SEG002.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG002.SECURE_READ 0
|
||||
S00_AXI.SEG002.SECURE_WRITE 0
|
||||
S00_AXI.SEG002.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000110
|
||||
S00_AXI.SEG002.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG002.DATA_WIDTH 32
|
||||
S00_AXI.SEG003.BASE_ADDR 0x0000000040420000
|
||||
S00_AXI.SEG003.SIZE 16
|
||||
S00_AXI.SEG003.SUPPORTS_READ 1
|
||||
S00_AXI.SEG003.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG003.SECURE_READ 0
|
||||
S00_AXI.SEG003.SECURE_WRITE 0
|
||||
S00_AXI.SEG003.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001000
|
||||
S00_AXI.SEG003.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG003.DATA_WIDTH 32
|
||||
S00_AXI.SEG004.BASE_ADDR 0x0000000040430000
|
||||
S00_AXI.SEG004.SIZE 16
|
||||
S00_AXI.SEG004.SUPPORTS_READ 1
|
||||
S00_AXI.SEG004.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG004.SECURE_READ 0
|
||||
S00_AXI.SEG004.SECURE_WRITE 0
|
||||
S00_AXI.SEG004.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001101
|
||||
S00_AXI.SEG004.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG004.DATA_WIDTH 32
|
||||
S00_AXI.SEG005.BASE_ADDR 0x0000000041200000
|
||||
S00_AXI.SEG005.SIZE 16
|
||||
S00_AXI.SEG005.SUPPORTS_READ 1
|
||||
S00_AXI.SEG005.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG005.SECURE_READ 0
|
||||
S00_AXI.SEG005.SECURE_WRITE 0
|
||||
S00_AXI.SEG005.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000001
|
||||
S00_AXI.SEG005.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG005.DATA_WIDTH 32
|
||||
S00_AXI.SEG006.BASE_ADDR 0x0000000041210000
|
||||
S00_AXI.SEG006.SIZE 16
|
||||
S00_AXI.SEG006.SUPPORTS_READ 1
|
||||
S00_AXI.SEG006.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG006.SECURE_READ 0
|
||||
S00_AXI.SEG006.SECURE_WRITE 0
|
||||
S00_AXI.SEG006.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001010
|
||||
S00_AXI.SEG006.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG006.DATA_WIDTH 32
|
||||
S00_AXI.SEG007.BASE_ADDR 0x0000000041220000
|
||||
S00_AXI.SEG007.SIZE 16
|
||||
S00_AXI.SEG007.SUPPORTS_READ 1
|
||||
S00_AXI.SEG007.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG007.SECURE_READ 0
|
||||
S00_AXI.SEG007.SECURE_WRITE 0
|
||||
S00_AXI.SEG007.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001011
|
||||
S00_AXI.SEG007.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG007.DATA_WIDTH 32
|
||||
S00_AXI.SEG008.BASE_ADDR 0x0000000041230000
|
||||
S00_AXI.SEG008.SIZE 16
|
||||
S00_AXI.SEG008.SUPPORTS_READ 1
|
||||
S00_AXI.SEG008.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG008.SECURE_READ 0
|
||||
S00_AXI.SEG008.SECURE_WRITE 0
|
||||
S00_AXI.SEG008.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001100
|
||||
S00_AXI.SEG008.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG008.DATA_WIDTH 32
|
||||
S00_AXI.SEG009.BASE_ADDR 0x0000000041240000
|
||||
S00_AXI.SEG009.SIZE 16
|
||||
S00_AXI.SEG009.SUPPORTS_READ 1
|
||||
S00_AXI.SEG009.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG009.SECURE_READ 0
|
||||
S00_AXI.SEG009.SECURE_WRITE 0
|
||||
S00_AXI.SEG009.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000010000
|
||||
S00_AXI.SEG009.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG009.DATA_WIDTH 32
|
||||
S00_AXI.SEG010.BASE_ADDR 0x0000000041250000
|
||||
S00_AXI.SEG010.SIZE 16
|
||||
S00_AXI.SEG010.SUPPORTS_READ 1
|
||||
S00_AXI.SEG010.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG010.SECURE_READ 0
|
||||
S00_AXI.SEG010.SECURE_WRITE 0
|
||||
S00_AXI.SEG010.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000010011
|
||||
S00_AXI.SEG010.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG010.DATA_WIDTH 32
|
||||
S00_AXI.SEG011.BASE_ADDR 0x0000000041260000
|
||||
S00_AXI.SEG011.SIZE 16
|
||||
S00_AXI.SEG011.SUPPORTS_READ 1
|
||||
S00_AXI.SEG011.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG011.SECURE_READ 0
|
||||
S00_AXI.SEG011.SECURE_WRITE 0
|
||||
S00_AXI.SEG011.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000100
|
||||
S00_AXI.SEG011.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG011.DATA_WIDTH 32
|
||||
S00_AXI.SEG012.BASE_ADDR 0x0000000041E00000
|
||||
S00_AXI.SEG012.SIZE 16
|
||||
S00_AXI.SEG012.SUPPORTS_READ 1
|
||||
S00_AXI.SEG012.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG012.SECURE_READ 0
|
||||
S00_AXI.SEG012.SECURE_WRITE 0
|
||||
S00_AXI.SEG012.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001110
|
||||
S00_AXI.SEG012.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG012.DATA_WIDTH 32
|
||||
S00_AXI.SEG013.BASE_ADDR 0x0000000041E10000
|
||||
S00_AXI.SEG013.SIZE 16
|
||||
S00_AXI.SEG013.SUPPORTS_READ 1
|
||||
S00_AXI.SEG013.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG013.SECURE_READ 0
|
||||
S00_AXI.SEG013.SECURE_WRITE 0
|
||||
S00_AXI.SEG013.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000010101
|
||||
S00_AXI.SEG013.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG013.DATA_WIDTH 32
|
||||
S00_AXI.SEG014.BASE_ADDR 0x0000000041E20000
|
||||
S00_AXI.SEG014.SIZE 16
|
||||
S00_AXI.SEG014.SUPPORTS_READ 1
|
||||
S00_AXI.SEG014.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG014.SECURE_READ 0
|
||||
S00_AXI.SEG014.SECURE_WRITE 0
|
||||
S00_AXI.SEG014.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001111
|
||||
S00_AXI.SEG014.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG014.DATA_WIDTH 32
|
||||
S00_AXI.SEG015.BASE_ADDR 0x0000000042000000
|
||||
S00_AXI.SEG015.SIZE 13
|
||||
S00_AXI.SEG015.SUPPORTS_READ 1
|
||||
S00_AXI.SEG015.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG015.SECURE_READ 0
|
||||
S00_AXI.SEG015.SECURE_WRITE 0
|
||||
S00_AXI.SEG015.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000010
|
||||
S00_AXI.SEG015.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG015.DATA_WIDTH 32
|
||||
S00_AXI.SEG016.BASE_ADDR 0x0000000044000000
|
||||
S00_AXI.SEG016.SIZE 13
|
||||
S00_AXI.SEG016.SUPPORTS_READ 1
|
||||
S00_AXI.SEG016.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG016.SECURE_READ 0
|
||||
S00_AXI.SEG016.SECURE_WRITE 0
|
||||
S00_AXI.SEG016.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000011
|
||||
S00_AXI.SEG016.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG016.DATA_WIDTH 32
|
||||
S00_AXI.SEG017.BASE_ADDR 0x0000000046000000
|
||||
S00_AXI.SEG017.SIZE 13
|
||||
S00_AXI.SEG017.SUPPORTS_READ 1
|
||||
S00_AXI.SEG017.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG017.SECURE_READ 0
|
||||
S00_AXI.SEG017.SECURE_WRITE 0
|
||||
S00_AXI.SEG017.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000101
|
||||
S00_AXI.SEG017.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG017.DATA_WIDTH 32
|
||||
S00_AXI.SEG018.BASE_ADDR 0x0000000048000000
|
||||
S00_AXI.SEG018.SIZE 13
|
||||
S00_AXI.SEG018.SUPPORTS_READ 1
|
||||
S00_AXI.SEG018.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG018.SECURE_READ 0
|
||||
S00_AXI.SEG018.SECURE_WRITE 0
|
||||
S00_AXI.SEG018.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000001001
|
||||
S00_AXI.SEG018.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG018.DATA_WIDTH 32
|
||||
S00_AXI.SEG019.BASE_ADDR 0x000000004A000000
|
||||
S00_AXI.SEG019.SIZE 13
|
||||
S00_AXI.SEG019.SUPPORTS_READ 1
|
||||
S00_AXI.SEG019.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG019.SECURE_READ 0
|
||||
S00_AXI.SEG019.SECURE_WRITE 0
|
||||
S00_AXI.SEG019.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000010001
|
||||
S00_AXI.SEG019.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG019.DATA_WIDTH 32
|
||||
S00_AXI.SEG020.BASE_ADDR 0x000000004C000000
|
||||
S00_AXI.SEG020.SIZE 13
|
||||
S00_AXI.SEG020.SUPPORTS_READ 1
|
||||
S00_AXI.SEG020.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG020.SECURE_READ 0
|
||||
S00_AXI.SEG020.SECURE_WRITE 0
|
||||
S00_AXI.SEG020.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000010010
|
||||
S00_AXI.SEG020.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG020.DATA_WIDTH 32
|
||||
S00_AXI.SEG021.BASE_ADDR 0x000000004E000000
|
||||
S00_AXI.SEG021.SIZE 13
|
||||
S00_AXI.SEG021.SUPPORTS_READ 1
|
||||
S00_AXI.SEG021.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG021.SECURE_READ 0
|
||||
S00_AXI.SEG021.SECURE_WRITE 0
|
||||
S00_AXI.SEG021.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000010100
|
||||
S00_AXI.SEG021.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG021.DATA_WIDTH 32
|
||||
@@ -0,0 +1,208 @@
|
||||
NUM_SI 4
|
||||
NUM_MI 1
|
||||
NUM_CLKS 1
|
||||
S00_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
S00_AXI.CONFIG.NUM_READ_OUTSTANDING 16
|
||||
S00_AXI.CONFIG.DATA_WIDTH 32
|
||||
S00_AXI.CONFIG.DATAWIDTH 32
|
||||
S00_AXI.CONFIG.PROTOCOL AXI4
|
||||
S00_AXI.CONFIG.FREQ_HZ 100000000
|
||||
S00_AXI.CONFIG.ID_WIDTH 0
|
||||
S00_AXI.CONFIG.ADDR_WIDTH 32
|
||||
S00_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.WUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.RUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.BUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.READ_WRITE_MODE READ_ONLY
|
||||
S00_AXI.CONFIG.HAS_BURST 0
|
||||
S00_AXI.CONFIG.HAS_LOCK 0
|
||||
S00_AXI.CONFIG.HAS_PROT 1
|
||||
S00_AXI.CONFIG.HAS_CACHE 1
|
||||
S00_AXI.CONFIG.HAS_QOS 0
|
||||
S00_AXI.CONFIG.HAS_REGION 0
|
||||
S00_AXI.CONFIG.HAS_WSTRB 0
|
||||
S00_AXI.CONFIG.HAS_BRESP 0
|
||||
S00_AXI.CONFIG.HAS_RRESP 1
|
||||
S00_AXI.CONFIG.NUM_WRITE_OUTSTANDING 2
|
||||
S00_AXI.CONFIG.MAX_BURST_LENGTH 128
|
||||
S00_AXI.CONFIG.PHASE 0.0
|
||||
S00_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
S00_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
S00_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
S00_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
S00_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
S00_AXI.CONFIG.INSERT_VIP 0
|
||||
S01_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
S01_AXI.CONFIG.NUM_WRITE_OUTSTANDING 16
|
||||
S01_AXI.CONFIG.DATA_WIDTH 32
|
||||
S01_AXI.CONFIG.DATAWIDTH 32
|
||||
S01_AXI.CONFIG.PROTOCOL AXI4
|
||||
S01_AXI.CONFIG.FREQ_HZ 100000000
|
||||
S01_AXI.CONFIG.ID_WIDTH 0
|
||||
S01_AXI.CONFIG.ADDR_WIDTH 32
|
||||
S01_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
S01_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
S01_AXI.CONFIG.WUSER_WIDTH 0
|
||||
S01_AXI.CONFIG.RUSER_WIDTH 0
|
||||
S01_AXI.CONFIG.BUSER_WIDTH 0
|
||||
S01_AXI.CONFIG.READ_WRITE_MODE WRITE_ONLY
|
||||
S01_AXI.CONFIG.HAS_BURST 0
|
||||
S01_AXI.CONFIG.HAS_LOCK 0
|
||||
S01_AXI.CONFIG.HAS_PROT 1
|
||||
S01_AXI.CONFIG.HAS_CACHE 1
|
||||
S01_AXI.CONFIG.HAS_QOS 0
|
||||
S01_AXI.CONFIG.HAS_REGION 0
|
||||
S01_AXI.CONFIG.HAS_WSTRB 1
|
||||
S01_AXI.CONFIG.HAS_BRESP 1
|
||||
S01_AXI.CONFIG.HAS_RRESP 0
|
||||
S01_AXI.CONFIG.NUM_READ_OUTSTANDING 2
|
||||
S01_AXI.CONFIG.MAX_BURST_LENGTH 128
|
||||
S01_AXI.CONFIG.PHASE 0.0
|
||||
S01_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
S01_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
S01_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
S01_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
S01_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
S01_AXI.CONFIG.INSERT_VIP 0
|
||||
S02_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
S02_AXI.CONFIG.NUM_WRITE_OUTSTANDING 16
|
||||
S02_AXI.CONFIG.DATA_WIDTH 32
|
||||
S02_AXI.CONFIG.DATAWIDTH 32
|
||||
S02_AXI.CONFIG.PROTOCOL AXI4
|
||||
S02_AXI.CONFIG.FREQ_HZ 100000000
|
||||
S02_AXI.CONFIG.ID_WIDTH 0
|
||||
S02_AXI.CONFIG.ADDR_WIDTH 32
|
||||
S02_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
S02_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
S02_AXI.CONFIG.WUSER_WIDTH 0
|
||||
S02_AXI.CONFIG.RUSER_WIDTH 0
|
||||
S02_AXI.CONFIG.BUSER_WIDTH 0
|
||||
S02_AXI.CONFIG.READ_WRITE_MODE WRITE_ONLY
|
||||
S02_AXI.CONFIG.HAS_BURST 0
|
||||
S02_AXI.CONFIG.HAS_LOCK 0
|
||||
S02_AXI.CONFIG.HAS_PROT 1
|
||||
S02_AXI.CONFIG.HAS_CACHE 1
|
||||
S02_AXI.CONFIG.HAS_QOS 0
|
||||
S02_AXI.CONFIG.HAS_REGION 0
|
||||
S02_AXI.CONFIG.HAS_WSTRB 1
|
||||
S02_AXI.CONFIG.HAS_BRESP 1
|
||||
S02_AXI.CONFIG.HAS_RRESP 0
|
||||
S02_AXI.CONFIG.NUM_READ_OUTSTANDING 2
|
||||
S02_AXI.CONFIG.MAX_BURST_LENGTH 128
|
||||
S02_AXI.CONFIG.PHASE 0.0
|
||||
S02_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
S02_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
S02_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
S02_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
S02_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
S02_AXI.CONFIG.INSERT_VIP 0
|
||||
S03_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
S03_AXI.CONFIG.NUM_WRITE_OUTSTANDING 16
|
||||
S03_AXI.CONFIG.DATA_WIDTH 32
|
||||
S03_AXI.CONFIG.DATAWIDTH 32
|
||||
S03_AXI.CONFIG.PROTOCOL AXI4
|
||||
S03_AXI.CONFIG.FREQ_HZ 100000000
|
||||
S03_AXI.CONFIG.ID_WIDTH 0
|
||||
S03_AXI.CONFIG.ADDR_WIDTH 32
|
||||
S03_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
S03_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
S03_AXI.CONFIG.WUSER_WIDTH 0
|
||||
S03_AXI.CONFIG.RUSER_WIDTH 0
|
||||
S03_AXI.CONFIG.BUSER_WIDTH 0
|
||||
S03_AXI.CONFIG.READ_WRITE_MODE WRITE_ONLY
|
||||
S03_AXI.CONFIG.HAS_BURST 0
|
||||
S03_AXI.CONFIG.HAS_LOCK 0
|
||||
S03_AXI.CONFIG.HAS_PROT 1
|
||||
S03_AXI.CONFIG.HAS_CACHE 1
|
||||
S03_AXI.CONFIG.HAS_QOS 0
|
||||
S03_AXI.CONFIG.HAS_REGION 0
|
||||
S03_AXI.CONFIG.HAS_WSTRB 1
|
||||
S03_AXI.CONFIG.HAS_BRESP 1
|
||||
S03_AXI.CONFIG.HAS_RRESP 0
|
||||
S03_AXI.CONFIG.NUM_READ_OUTSTANDING 2
|
||||
S03_AXI.CONFIG.MAX_BURST_LENGTH 128
|
||||
S03_AXI.CONFIG.PHASE 0.0
|
||||
S03_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
S03_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
S03_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
S03_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
S03_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
S03_AXI.CONFIG.INSERT_VIP 0
|
||||
M00_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M00_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M00_AXI.CONFIG.DATA_WIDTH 32
|
||||
M00_AXI.CONFIG.DATAWIDTH 32
|
||||
M00_AXI.CONFIG.PROTOCOL AXI3
|
||||
M00_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M00_AXI.CONFIG.ID_WIDTH 6
|
||||
M00_AXI.CONFIG.ADDR_WIDTH 32
|
||||
M00_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M00_AXI.CONFIG.HAS_BURST 1
|
||||
M00_AXI.CONFIG.HAS_LOCK 1
|
||||
M00_AXI.CONFIG.HAS_PROT 1
|
||||
M00_AXI.CONFIG.HAS_CACHE 1
|
||||
M00_AXI.CONFIG.HAS_QOS 1
|
||||
M00_AXI.CONFIG.HAS_REGION 0
|
||||
M00_AXI.CONFIG.HAS_WSTRB 1
|
||||
M00_AXI.CONFIG.HAS_BRESP 1
|
||||
M00_AXI.CONFIG.HAS_RRESP 1
|
||||
M00_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M00_AXI.CONFIG.MAX_BURST_LENGTH 16
|
||||
M00_AXI.CONFIG.PHASE 0.0
|
||||
M00_AXI.CONFIG.CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0
|
||||
M00_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M00_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M00_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M00_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M00_AXI.CONFIG.INSERT_VIP 0
|
||||
M00_AXI.IS_CASCADED 0
|
||||
S00_AXI.IS_CASCADED 0
|
||||
S01_AXI.IS_CASCADED 0
|
||||
S02_AXI.IS_CASCADED 0
|
||||
S03_AXI.IS_CASCADED 0
|
||||
S00_AXI.NUM_SEG 1
|
||||
S00_AXI.SEG000.BASE_ADDR 0x0000000000000000
|
||||
S00_AXI.SEG000.SIZE 29
|
||||
S00_AXI.SEG000.SUPPORTS_READ 1
|
||||
S00_AXI.SEG000.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG000.SECURE_READ 0
|
||||
S00_AXI.SEG000.SECURE_WRITE 0
|
||||
S00_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
|
||||
S00_AXI.SEG000.PROTOCOL AXI3
|
||||
S00_AXI.SEG000.DATA_WIDTH 32
|
||||
S01_AXI.NUM_SEG 1
|
||||
S01_AXI.SEG000.BASE_ADDR 0x0000000000000000
|
||||
S01_AXI.SEG000.SIZE 29
|
||||
S01_AXI.SEG000.SUPPORTS_READ 1
|
||||
S01_AXI.SEG000.SUPPORTS_WRITE 1
|
||||
S01_AXI.SEG000.SECURE_READ 0
|
||||
S01_AXI.SEG000.SECURE_WRITE 0
|
||||
S01_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
|
||||
S01_AXI.SEG000.PROTOCOL AXI3
|
||||
S01_AXI.SEG000.DATA_WIDTH 32
|
||||
S02_AXI.NUM_SEG 1
|
||||
S02_AXI.SEG000.BASE_ADDR 0x0000000000000000
|
||||
S02_AXI.SEG000.SIZE 29
|
||||
S02_AXI.SEG000.SUPPORTS_READ 1
|
||||
S02_AXI.SEG000.SUPPORTS_WRITE 1
|
||||
S02_AXI.SEG000.SECURE_READ 0
|
||||
S02_AXI.SEG000.SECURE_WRITE 0
|
||||
S02_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
|
||||
S02_AXI.SEG000.PROTOCOL AXI3
|
||||
S02_AXI.SEG000.DATA_WIDTH 32
|
||||
S03_AXI.NUM_SEG 1
|
||||
S03_AXI.SEG000.BASE_ADDR 0x0000000000000000
|
||||
S03_AXI.SEG000.SIZE 29
|
||||
S03_AXI.SEG000.SUPPORTS_READ 1
|
||||
S03_AXI.SEG000.SUPPORTS_WRITE 1
|
||||
S03_AXI.SEG000.SECURE_READ 0
|
||||
S03_AXI.SEG000.SECURE_WRITE 0
|
||||
S03_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
|
||||
S03_AXI.SEG000.PROTOCOL AXI3
|
||||
S03_AXI.SEG000.DATA_WIDTH 32
|
||||
@@ -0,0 +1,25 @@
|
||||
@echo off
|
||||
REM ****************************************************************************
|
||||
REM Vivado (TM) v2023.1 (64-bit)
|
||||
REM
|
||||
REM Filename : simulate.bat
|
||||
REM Simulator : Xilinx Vivado Simulator
|
||||
REM Description : Script for simulating the design by launching the simulator
|
||||
REM
|
||||
REM Generated by Vivado on Thu Sep 03 09:57:19 +0800 2026
|
||||
REM SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
|
||||
REM
|
||||
REM IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
|
||||
REM
|
||||
REM usage: simulate.bat
|
||||
REM
|
||||
REM ****************************************************************************
|
||||
REM simulate design
|
||||
echo "xsim pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch pl_top_tb.tcl -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg -log simulate.log"
|
||||
call xsim pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch pl_top_tb.tcl -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg -log simulate.log
|
||||
if "%errorlevel%"=="0" goto SUCCESS
|
||||
if "%errorlevel%"=="1" goto END
|
||||
:END
|
||||
exit 1
|
||||
:SUCCESS
|
||||
exit 0
|
||||
@@ -0,0 +1,79 @@
|
||||
Time resolution is 1 ps
|
||||
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
||||
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
||||
INFO: xsimkernel Simulation Memory Usage: 30840 KB (Peak: 30840 KB), Simulation CPU Usage: 211702 ms
|
||||
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|
||||
--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "axi_infrastructure_v1_1_0" -L "axi_vip_v1_1_14" -L "processing_system7_vip_v1_0_16" -L "axis_infrastructure_v1_1_0" -L "axis_data_fifo_v2_0_10" -L "fifo_generator_v13_2_8" -L "axi_lite_ipif_v3_0_4" -L "lib_cdc_v1_0_2" -L "interrupt_control_v3_1_4" -L "axi_gpio_v2_0_30" -L "dist_mem_gen_v8_0_13" -L "lib_pkg_v1_0_2" -L "lib_srl_fifo_v1_0_2" -L "lib_fifo_v1_0_17" -L "axi_quad_spi_v3_2_27" -L "axi_datamover_v5_1_30" -L "axi_sg_v4_1_16" -L "axi_dma_v7_1_29" -L "axi_bram_ctrl_v4_1_8" -L "xlconstant_v1_1_7" -L "proc_sys_reset_v5_0_13" -L "smartconnect_v1_0" -L "axi_register_slice_v2_1_28" -L "xlconcat_v2_1_4" -L "uvm" -L "xilinx_vip" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "pl_top_tb_behav" "xil_defaultlib.pl_top_tb" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
@@ -0,0 +1 @@
|
||||
Breakpoint File Version 1.0
|
||||
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|
||||
|
||||
{
|
||||
crc : 82732466229793304 ,
|
||||
ccp_crc : 0 ,
|
||||
cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl" ,
|
||||
buildDate : "May 7 2023" ,
|
||||
buildTime : "15:24:31" ,
|
||||
linkCmd : "C:\\Xilinx\\Vivado\\2023.1\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/pl_top_tb_behav/xsimk.exe\" \"xsim.dir/pl_top_tb_behav/obj/xsim_0.win64.obj\" \"xsim.dir/pl_top_tb_behav/obj/xsim_1.win64.obj\" \"xsim.dir/pl_top_tb_behav/obj/xsim_2.win64.obj\" \"xsim.dir/pl_top_tb_behav/obj/xsim_3.win64.obj\" \"xsim.dir/pl_top_tb_behav/obj/xsim_4.win64.obj\" \"xsim.dir/pl_top_tb_behav/obj/xsim_5.win64.obj\" \"xsim.dir/pl_top_tb_behav/obj/xsim_6.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2023.1\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" ,
|
||||
aggregate_nets :
|
||||
[
|
||||
]
|
||||
}
|
||||
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|
||||
[General]
|
||||
ARRAY_DISPLAY_LIMIT=1024
|
||||
RADIX=hex
|
||||
TIME_UNIT=ns
|
||||
TRACE_LIMIT=65536
|
||||
VHDL_ENTITY_SCOPE_FILTER=true
|
||||
VHDL_PACKAGE_SCOPE_FILTER=false
|
||||
VHDL_BLOCK_SCOPE_FILTER=true
|
||||
VHDL_PROCESS_SCOPE_FILTER=false
|
||||
VHDL_PROCEDURE_SCOPE_FILTER=false
|
||||
VERILOG_MODULE_SCOPE_FILTER=true
|
||||
VERILOG_PACKAGE_SCOPE_FILTER=false
|
||||
VERILOG_BLOCK_SCOPE_FILTER=false
|
||||
VERILOG_TASK_SCOPE_FILTER=false
|
||||
VERILOG_PROCESS_SCOPE_FILTER=false
|
||||
INPUT_OBJECT_FILTER=true
|
||||
OUTPUT_OBJECT_FILTER=true
|
||||
INOUT_OBJECT_FILTER=true
|
||||
INTERNAL_OBJECT_FILTER=true
|
||||
CONSTANT_OBJECT_FILTER=true
|
||||
VARIABLE_OBJECT_FILTER=true
|
||||
INPUT_PROTOINST_FILTER=true
|
||||
OUTPUT_PROTOINST_FILTER=true
|
||||
INOUT_PROTOINST_FILTER=true
|
||||
INTERNAL_PROTOINST_FILTER=true
|
||||
CONSTANT_PROTOINST_FILTER=true
|
||||
VARIABLE_PROTOINST_FILTER=true
|
||||
SCOPE_NAME_COLUMN_WIDTH=332
|
||||
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=153
|
||||
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=100
|
||||
OBJECT_NAME_COLUMN_WIDTH=177
|
||||
OBJECT_VALUE_COLUMN_WIDTH=49
|
||||
OBJECT_DATA_TYPE_COLUMN_WIDTH=73
|
||||
PROCESS_NAME_COLUMN_WIDTH=75
|
||||
PROCESS_TYPE_COLUMN_WIDTH=75
|
||||
FRAME_INDEX_COLUMN_WIDTH=75
|
||||
FRAME_NAME_COLUMN_WIDTH=75
|
||||
FRAME_FILE_NAME_COLUMN_WIDTH=75
|
||||
FRAME_LINE_NUM_COLUMN_WIDTH=213
|
||||
LOCAL_NAME_COLUMN_WIDTH=75
|
||||
LOCAL_VALUE_COLUMN_WIDTH=73
|
||||
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
|
||||
PROTO_NAME_COLUMN_WIDTH=0
|
||||
PROTO_VALUE_COLUMN_WIDTH=0
|
||||
INPUT_LOCAL_FILTER=1
|
||||
OUTPUT_LOCAL_FILTER=1
|
||||
INOUT_LOCAL_FILTER=1
|
||||
INTERNAL_LOCAL_FILTER=1
|
||||
CONSTANT_LOCAL_FILTER=1
|
||||
VARIABLE_LOCAL_FILTER=1
|
||||
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|
||||
Running: xsim.dir/pl_top_tb_behav/xsimk.exe -simmode gui -wdb pl_top_tb_behav.wdb -simrunnum 0 -socket 65142
|
||||
Design successfully loaded
|
||||
Design Loading Memory Usage: 18040 KB (Peak: 18040 KB)
|
||||
Design Loading CPU Usage: 61 ms
|
||||
Simulation completed
|
||||
Simulation Memory Usage: 30840 KB (Peak: 30840 KB)
|
||||
Simulation CPU Usage: 211702 ms
|
||||
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Reference in New Issue
Block a user