GEM/BSI-901-fpga-software
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chunk-sync
2026-09-11 16:18:36 +08:00
parent c315cef09e
commit c2c1bb2648
922 changed files with 102283 additions and 6793 deletions
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c64_pro.sim/sim_1/behav/modelsim/compile.bat
+2 -2
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@@ -6,7 +6,7 @@ REM Filename : compile.bat
REM Simulator : Siemens ModelSim Simulator
REM Description : Script for compiling the simulation design source files
REM
REM Generated by Vivado on Mon Jul 29 14:48:46 +0800 2024
REM Generated by Vivado on Mon Oct 20 14:37:06 +0800 2025
REM SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
REM
REM IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
@@ -14,7 +14,7 @@ REM
REM usage: compile.bat
REM
REM ****************************************************************************
set bin_path=C:\modeltech64_10.7\win64
set bin_path=D:\Program files\modelsim\win64
call %bin_path%/vsim -c -do "do {pl_top_tb_compile.do}" -l compile.log
if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS
c64_pro.sim/sim_1/behav/modelsim/pl_top_tb_compile.do
+1 -2
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@@ -1,7 +1,7 @@
######################################################################
#
# File name : pl_top_tb_compile.do
# Created on: Mon Jul 29 14:48:46 +0800 2024
# Created on: Mon Oct 20 14:37:05 +0800 2025
#
# Auto generated by Vivado for 'behavioral' simulation
#
@@ -117,7 +117,6 @@ vlog -incr -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" \
"../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" \
"../../../../c64_pro.srcs/sources_1/rtl/emg/emg_top.v" \
"../../../../c64_pro.srcs/sources_1/rtl/pl_top.v" \
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" \
"../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top.v" \