sync chunk 11/12
This commit is contained in:
chunk-sync
@@ -0,0 +1,5 @@
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||||
set_property SRC_FILE_INFO {cfile:d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc rfile:../../../LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc id:1 order:EARLY} [current_design]
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||||
set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_waiver -type CDC -id CDC-4 -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter {NAME =~ "*probe_in_reg_reg*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*data_int_sync1_reg*"}]] -user "vio" -description {The path has combinational circuit. But from hardware prospective the design works perfectly and the signals crossing happen after a very long time from the source has the value.} -tags "1050886" -scope -internal
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||||
set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design]
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||||
create_waiver -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*Hold_probe_in*" && IS_SEQUENTIAL } ]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter { NAME =~ "*PROBE_IN_INST/probe_in_reg*" && IS_SEQUENTIAL} ]] -user "vio" -description {The path has combinational circuit. But from hardware prospective the design works perfectly and the signals crossing happen after a very long time from the source has the value.} -tags "1050886" -scope -internal
|
||||
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="lixiangfu" Host="DESKTOP-VN054CM" Pid="34400" HostCore="20" HostMemory="0171579695104">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
@@ -0,0 +1,85 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_cur_flt_state_synth_1" LaunchPart="xc7z020clg400-2" LaunchTime="1782280322">
|
||||
<File Type="PA-TCL" Name="vio_cur_flt_state.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="vio_cur_flt_state_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="vio_cur_flt_state.vds"/>
|
||||
<File Type="RDS-UTIL" Name="vio_cur_flt_state_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_cur_flt_state_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="vio_cur_flt_state.dcp"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_cur_flt_state" RelGenDir="$PGENDIR/vio_cur_flt_state">
|
||||
<File Path="$PSRCDIR/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="vio_cur_flt_state"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_cur_flt_state" RelGenDir="$PGENDIR/vio_cur_flt_state">
|
||||
<File Path="$PSRCDIR/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="vio_cur_flt_state"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
@@ -0,0 +1,10 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
REM Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log vio_cur_flt_state.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_cur_flt_state.tcl
|
||||
@@ -0,0 +1,37 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/Vitis/2023.1/bin;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2023.1/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/Vitis/2023.1/bin;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2023.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log vio_cur_flt_state.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_cur_flt_state.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
@@ -0,0 +1,374 @@
|
||||
|
||||
*** Running vivado
|
||||
with args -log vio_cur_flt_state.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_cur_flt_state.tcl
|
||||
|
||||
|
||||
|
||||
****** Vivado v2023.1 (64-bit)
|
||||
**** SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
|
||||
**** IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
|
||||
**** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
|
||||
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
source vio_cur_flt_state.tcl -notrace
|
||||
create_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1468.434 ; gain = 161.480
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: vio_cur_flt_state
|
||||
Command: synth_design -top vio_cur_flt_state -part xc7z020clg400-2 -incremental_mode off -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
|
||||
INFO: [Device 21-403] Loading part xc7z020clg400-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 29808
|
||||
WARNING: [Synth 8-10515] begin/end is required for generate-for in this mode of Verilog [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/hdl/vio_v3_0_syn_rfs.v:1365]
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2327.035 ; gain = 409.660
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'vio_cur_flt_state' [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/synth/vio_cur_flt_state.v:49]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'vio_cur_flt_state' (0#1) [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/synth/vio_cur_flt_state.v:49]
|
||||
WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_cur_flt_state does not have driver. [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/synth/vio_cur_flt_state.v:73]
|
||||
WARNING: [Synth 8-7129] Port probe_in3[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in4[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in5[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in6[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in7[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in8[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in9[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in10[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in11[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in12[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in13[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in14[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in15[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in16[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in17[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in18[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in19[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in20[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in21[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in22[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in23[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in24[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in25[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in26[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in27[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in28[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in29[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in30[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in31[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in32[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in33[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in34[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in35[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in36[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in37[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in38[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in39[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in40[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in41[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in42[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in43[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in44[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in45[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in46[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in47[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in48[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in49[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in50[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in51[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in52[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in53[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in54[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in55[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in56[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in57[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in58[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in59[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in60[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in61[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in62[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in63[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in64[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in65[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in66[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in67[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in68[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in69[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in70[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in71[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in72[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in73[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in74[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in75[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in76[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in77[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in78[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in79[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in80[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in81[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in82[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in83[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in84[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in85[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in86[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in87[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in88[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in89[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in90[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in91[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in92[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in93[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in94[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in95[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in96[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in97[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in98[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in99[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in100[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in101[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in102[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2441.824 ; gain = 524.449
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2441.824 ; gain = 524.449
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2441.824 ; gain = 524.449
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2441.824 ; gain = 0.000
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_ooc.xdc]
|
||||
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_ooc.xdc]
|
||||
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]
|
||||
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/vio_cur_flt_state_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/vio_cur_flt_state_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2509.492 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 2514.125 ; gain = 4.633
|
||||
INFO: [Designutils 20-5008] Incremental synthesis strategy off
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z020clg400-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 6 Bit Adders := 1
|
||||
2 Input 1 Bit Adders := 1
|
||||
+---Registers :
|
||||
128 Bit Registers := 1
|
||||
97 Bit Registers := 5
|
||||
16 Bit Registers := 7
|
||||
7 Bit Registers := 1
|
||||
6 Bit Registers := 1
|
||||
5 Bit Registers := 1
|
||||
3 Bit Registers := 2
|
||||
1 Bit Registers := 13
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 2
|
||||
2 Input 1 Bit Muxes := 4
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 220 (col length:60)
|
||||
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+------+------+
|
||||
| |Cell |Count |
|
||||
+------+------+------+
|
||||
|1 |LUT1 | 3|
|
||||
|2 |LUT2 | 5|
|
||||
|3 |LUT3 | 215|
|
||||
|4 |LUT4 | 11|
|
||||
|5 |LUT5 | 22|
|
||||
|6 |LUT6 | 148|
|
||||
|7 |MUXF7 | 32|
|
||||
|8 |MUXF8 | 16|
|
||||
|9 |FDRE | 739|
|
||||
+------+------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 291 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:34 ; elapsed = 00:00:50 . Memory (MB): peak = 2514.125 ; gain = 524.449
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 2514.125 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 48 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2514.125 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Synth Design complete | Checksum: 479f714d
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
20 Infos, 140 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:59 ; elapsed = 00:01:03 . Memory (MB): peak = 2514.125 ; gain = 1001.438
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp' has been generated.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_cur_flt_state, cache-ID = 8d048e0917528583
|
||||
INFO: [Coretcl 2-1174] Renamed 5 cell refs.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file vio_cur_flt_state_utilization_synth.rpt -pb vio_cur_flt_state_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Jun 24 13:53:40 2026...
|
||||
@@ -0,0 +1,44 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/Vitis/2023.1/bin;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2023.1/bin
|
||||
else
|
||||
PATH=C:/Xilinx/Vitis/2023.1/bin;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2023.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log vio_cur_flt_state.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_cur_flt_state.tcl
|
||||
Binary file not shown.
@@ -0,0 +1,243 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
namespace eval ::optrace {
|
||||
variable script "D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.tcl"
|
||||
variable category "vivado_synth"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
OPTRACE "vio_cur_flt_state_synth_1" START { ROLLUP_AUTO }
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7z020clg400-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.cache/wt [current_project]
|
||||
set_property parent.project_path D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_FIFO XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_ip -quiet D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.srcs/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xci
|
||||
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_ooc.xdc]
|
||||
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
OPTRACE "Configure IP Cache" START { }
|
||||
|
||||
set cacheID [config_ip_cache -export -no_bom -dir D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1 -new_name vio_cur_flt_state -ip [get_ips vio_cur_flt_state]]
|
||||
|
||||
OPTRACE "Configure IP Cache" END { }
|
||||
if { $cacheID == "" } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top vio_cur_flt_state -part xc7z020clg400-2 -incremental_mode off -mode out_of_context
|
||||
OPTRACE "synth_design" END { }
|
||||
OPTRACE "Write IP Cache" START { }
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix vio_cur_flt_state_ vio_cur_flt_state.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_cur_flt_state_stub.v
|
||||
lappend ipCachedFiles vio_cur_flt_state_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_cur_flt_state_stub.vhdl
|
||||
lappend ipCachedFiles vio_cur_flt_state_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_cur_flt_state_sim_netlist.v
|
||||
lappend ipCachedFiles vio_cur_flt_state_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_cur_flt_state_sim_netlist.vhdl
|
||||
lappend ipCachedFiles vio_cur_flt_state_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
|
||||
config_ip_cache -add -dcp vio_cur_flt_state.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips vio_cur_flt_state]
|
||||
}
|
||||
OPTRACE "Write IP Cache" END { }
|
||||
}
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
rename_ref -prefix_all vio_cur_flt_state_
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef vio_cur_flt_state.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
create_report "vio_cur_flt_state_synth_1_synth_report_utilization_0" "report_utilization -file vio_cur_flt_state_utilization_synth.rpt -pb vio_cur_flt_state_utilization_synth.pb"
|
||||
OPTRACE "synth reports" END { }
|
||||
|
||||
if { [catch {
|
||||
file copy -force D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
if { [catch {
|
||||
file copy -force D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state_stub.v d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state_stub.vhdl d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state_sim_netlist.v d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state_sim_netlist.vhdl d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
close [open .end.used_ip_cache.rst w]
|
||||
}; # end if cacheID
|
||||
|
||||
if {[file isdir D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.ip_user_files/ip/vio_cur_flt_state]} {
|
||||
catch {
|
||||
file copy -force d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.v D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.ip_user_files/ip/vio_cur_flt_state
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.ip_user_files/ip/vio_cur_flt_state]} {
|
||||
catch {
|
||||
file copy -force d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.vhdl D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.ip_user_files/ip/vio_cur_flt_state
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "vio_cur_flt_state_synth_1" END { }
|
||||
@@ -0,0 +1,374 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.1 (64-bit)
|
||||
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
|
||||
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
|
||||
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
|
||||
# Start of session at: Wed Jun 24 13:52:09 2026
|
||||
# Process ID: 30740
|
||||
# Current directory: D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1
|
||||
# Command line: vivado.exe -log vio_cur_flt_state.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_cur_flt_state.tcl
|
||||
# Log file: D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.vds
|
||||
# Journal file: D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1\vivado.jou
|
||||
# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
|
||||
#-----------------------------------------------------------
|
||||
source vio_cur_flt_state.tcl -notrace
|
||||
create_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1468.434 ; gain = 161.480
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: vio_cur_flt_state
|
||||
Command: synth_design -top vio_cur_flt_state -part xc7z020clg400-2 -incremental_mode off -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
|
||||
INFO: [Device 21-403] Loading part xc7z020clg400-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 29808
|
||||
WARNING: [Synth 8-10515] begin/end is required for generate-for in this mode of Verilog [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/hdl/vio_v3_0_syn_rfs.v:1365]
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2327.035 ; gain = 409.660
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'vio_cur_flt_state' [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/synth/vio_cur_flt_state.v:49]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'vio_cur_flt_state' (0#1) [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/synth/vio_cur_flt_state.v:49]
|
||||
WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_cur_flt_state does not have driver. [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/synth/vio_cur_flt_state.v:73]
|
||||
WARNING: [Synth 8-7129] Port probe_in3[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in4[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in5[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in6[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in7[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in8[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in9[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in10[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in11[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in12[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in13[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in14[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in15[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in16[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in17[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in18[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in19[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in20[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in21[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in22[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in23[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in24[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in25[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in26[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in27[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in28[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in29[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in30[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in31[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in32[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in33[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in34[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in35[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in36[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in37[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in38[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in39[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in40[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in41[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in42[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in43[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in44[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in45[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in46[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in47[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in48[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in49[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in50[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in51[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in52[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in53[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in54[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in55[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in56[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in57[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in58[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in59[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in60[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in61[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in62[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in63[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in64[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in65[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in66[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in67[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in68[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in69[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in70[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in71[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in72[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in73[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in74[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in75[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in76[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in77[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in78[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in79[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in80[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in81[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in82[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in83[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in84[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in85[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in86[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in87[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in88[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in89[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in90[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in91[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in92[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in93[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in94[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in95[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in96[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in97[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in98[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in99[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in100[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in101[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port probe_in102[0] in module vio_v3_0_23_vio is either unconnected or has no load
|
||||
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2441.824 ; gain = 524.449
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2441.824 ; gain = 524.449
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2441.824 ; gain = 524.449
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2441.824 ; gain = 0.000
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_ooc.xdc]
|
||||
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_ooc.xdc]
|
||||
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]
|
||||
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/vio_cur_flt_state_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/vio_cur_flt_state_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2509.492 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 2514.125 ; gain = 4.633
|
||||
INFO: [Designutils 20-5008] Incremental synthesis strategy off
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z020clg400-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 6 Bit Adders := 1
|
||||
2 Input 1 Bit Adders := 1
|
||||
+---Registers :
|
||||
128 Bit Registers := 1
|
||||
97 Bit Registers := 5
|
||||
16 Bit Registers := 7
|
||||
7 Bit Registers := 1
|
||||
6 Bit Registers := 1
|
||||
5 Bit Registers := 1
|
||||
3 Bit Registers := 2
|
||||
1 Bit Registers := 13
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 2
|
||||
2 Input 1 Bit Muxes := 4
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 220 (col length:60)
|
||||
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+------+------+
|
||||
| |Cell |Count |
|
||||
+------+------+------+
|
||||
|1 |LUT1 | 3|
|
||||
|2 |LUT2 | 5|
|
||||
|3 |LUT3 | 215|
|
||||
|4 |LUT4 | 11|
|
||||
|5 |LUT5 | 22|
|
||||
|6 |LUT6 | 148|
|
||||
|7 |MUXF7 | 32|
|
||||
|8 |MUXF8 | 16|
|
||||
|9 |FDRE | 739|
|
||||
+------+------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 291 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:34 ; elapsed = 00:00:50 . Memory (MB): peak = 2514.125 ; gain = 524.449
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 2514.125 ; gain = 596.750
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 2514.125 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 48 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2514.125 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Synth Design complete | Checksum: 479f714d
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
20 Infos, 140 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:59 ; elapsed = 00:01:03 . Memory (MB): peak = 2514.125 ; gain = 1001.438
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp' has been generated.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_cur_flt_state, cache-ID = 8d048e0917528583
|
||||
INFO: [Coretcl 2-1174] Renamed 5 cell refs.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file vio_cur_flt_state_utilization_synth.rpt -pb vio_cur_flt_state_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Jun 24 13:53:40 2026...
|
||||
Binary file not shown.
@@ -0,0 +1,178 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
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| Date : Wed Jun 24 13:53:39 2026
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| Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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| Command : report_utilization -file vio_cur_flt_state_utilization_synth.rpt -pb vio_cur_flt_state_utilization_synth.pb
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| Design : vio_cur_flt_state
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| Device : xc7z020clg400-2
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| Speed File : -2
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| Design State : Synthesized
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---------------------------------------------------------------------------------------------------------------------------------------------
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Memory
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3. DSP
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4. IO and GT Specific
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5. Clocking
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6. Specific Feature
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7. Primitives
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8. Black Boxes
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9. Instantiated Netlists
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1. Slice Logic
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--------------
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+-------------------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-------------------------+------+-------+------------+-----------+-------+
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| Slice LUTs* | 389 | 0 | 0 | 53200 | 0.73 |
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| LUT as Logic | 389 | 0 | 0 | 53200 | 0.73 |
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| LUT as Memory | 0 | 0 | 0 | 17400 | 0.00 |
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| Slice Registers | 739 | 0 | 0 | 106400 | 0.69 |
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| Register as Flip Flop | 739 | 0 | 0 | 106400 | 0.69 |
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| Register as Latch | 0 | 0 | 0 | 106400 | 0.00 |
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| F7 Muxes | 32 | 0 | 0 | 26600 | 0.12 |
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| F8 Muxes | 16 | 0 | 0 | 13300 | 0.12 |
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+-------------------------+------+-------+------------+-----------+-------+
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* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
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Warning! LUT value is adjusted to account for LUT combining.
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 0 | Yes | - | Set |
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| 0 | Yes | - | Reset |
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| 0 | Yes | Set | - |
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| 739 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. Memory
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---------
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+----------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+----------------+------+-------+------------+-----------+-------+
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| Block RAM Tile | 0 | 0 | 0 | 140 | 0.00 |
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| RAMB36/FIFO* | 0 | 0 | 0 | 140 | 0.00 |
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| RAMB18 | 0 | 0 | 0 | 280 | 0.00 |
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+----------------+------+-------+------------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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3. DSP
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------
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+-----------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-----------+------+-------+------------+-----------+-------+
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| DSPs | 0 | 0 | 0 | 220 | 0.00 |
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+-----------+------+-------+------------+-----------+-------+
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4. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-----------------------------+------+-------+------------+-----------+-------+
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| Bonded IOB | 0 | 0 | 0 | 125 | 0.00 |
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| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
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| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
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| PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 |
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| PHASER_REF | 0 | 0 | 0 | 4 | 0.00 |
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| OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 |
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| IN_FIFO | 0 | 0 | 0 | 16 | 0.00 |
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| IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 |
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| IBUFDS | 0 | 0 | 0 | 121 | 0.00 |
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| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 |
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| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 |
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| ILOGIC | 0 | 0 | 0 | 125 | 0.00 |
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| OLOGIC | 0 | 0 | 0 | 125 | 0.00 |
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+-----------------------------+------+-------+------------+-----------+-------+
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5. Clocking
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-----------
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+------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+------------+------+-------+------------+-----------+-------+
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| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
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| BUFIO | 0 | 0 | 0 | 16 | 0.00 |
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| MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 |
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| PLLE2_ADV | 0 | 0 | 0 | 4 | 0.00 |
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| BUFMRCE | 0 | 0 | 0 | 8 | 0.00 |
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| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
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| BUFR | 0 | 0 | 0 | 16 | 0.00 |
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+------------+------+-------+------------+-----------+-------+
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6. Specific Feature
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||||
-------------------
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+-------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-------------+------+-------+------------+-----------+-------+
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| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
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| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
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| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
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| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
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| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
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| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
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| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
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| XADC | 0 | 0 | 0 | 1 | 0.00 |
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+-------------+------+-------+------------+-----------+-------+
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7. Primitives
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-------------
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+----------+------+---------------------+
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| Ref Name | Used | Functional Category |
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+----------+------+---------------------+
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| FDRE | 739 | Flop & Latch |
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| LUT3 | 215 | LUT |
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| LUT6 | 148 | LUT |
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| MUXF7 | 32 | MuxFx |
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| LUT5 | 22 | LUT |
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| MUXF8 | 16 | MuxFx |
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| LUT4 | 11 | LUT |
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| LUT2 | 5 | LUT |
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| LUT1 | 3 | LUT |
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+----------+------+---------------------+
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8. Black Boxes
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||||
--------------
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||||
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+----------+------+
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||||
| Ref Name | Used |
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||||
+----------+------+
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||||
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||||
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||||
9. Instantiated Netlists
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||||
------------------------
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||||
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||||
+----------+------+
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||||
| Ref Name | Used |
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||||
+----------+------+
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||||
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||||
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@@ -0,0 +1,14 @@
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#-----------------------------------------------------------
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# Vivado v2023.1 (64-bit)
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# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
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# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
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# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
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# Start of session at: Wed Jun 24 13:52:09 2026
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# Process ID: 30740
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# Current directory: D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1
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# Command line: vivado.exe -log vio_cur_flt_state.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_cur_flt_state.tcl
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# Log file: D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1/vio_cur_flt_state.vds
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# Journal file: D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/vio_cur_flt_state_synth_1\vivado.jou
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# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
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#-----------------------------------------------------------
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source vio_cur_flt_state.tcl -notrace
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Binary file not shown.
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Block a user