GEM/BSI-901-fpga-software
9
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

sync chunk 11/12

Browse Source
This commit is contained in:
chunk-sync
2026-09-11 16:18:36 +08:00
parent c315cef09e
commit c2c1bb2648
922 changed files with 102283 additions and 6793 deletions
Download Patch File Download Diff File Expand all files Collapse all files
c64_pro.runs/synth_1/c64pro_top_utilization_synth.rpt
+75 -62
View File
@@ -1,11 +1,11 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Sun Aug 4 13:40:31 2024
| Host : 840-5CG14025H4 running 64-bit major release (build 9200)
| Date : Fri Sep 4 15:27:46 2026
| Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
| Command : report_utilization -file c64pro_top_utilization_synth.rpt -pb c64pro_top_utilization_synth.pb
| Design : c64pro_top
| Device : xc7z010clg400-2
| Device : xc7z020clg400-2
| Speed File : -2
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------------------------
@@ -31,14 +31,14 @@ Table of Contents
+-------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs* | 6173 | 0 | 0 | 17600 | 35.07 |
| LUT as Logic | 6173 | 0 | 0 | 17600 | 35.07 |
| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 |
| Slice Registers | 11236 | 0 | 0 | 35200 | 31.92 |
| Register as Flip Flop | 11108 | 0 | 0 | 35200 | 31.56 |
| Register as Latch | 128 | 0 | 0 | 35200 | 0.36 |
| F7 Muxes | 997 | 0 | 0 | 8800 | 11.33 |
| F8 Muxes | 452 | 0 | 0 | 4400 | 10.27 |
| Slice LUTs* | 7721 | 0 | 0 | 53200 | 14.51 |
| LUT as Logic | 7721 | 0 | 0 | 53200 | 14.51 |
| LUT as Memory | 0 | 0 | 0 | 17400 | 0.00 |
| Slice Registers | 11803 | 0 | 0 | 106400 | 11.09 |
| Register as Flip Flop | 11803 | 0 | 0 | 106400 | 11.09 |
| Register as Latch | 0 | 0 | 0 | 106400 | 0.00 |
| F7 Muxes | 1594 | 0 | 0 | 26600 | 5.99 |
| F8 Muxes | 712 | 0 | 0 | 13300 | 5.35 |
+-------------------------+-------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
@@ -56,10 +56,10 @@ Warning! LUT value is adjusted to account for LUT combining.
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 366 | Yes | - | Set |
| 10838 | Yes | - | Reset |
| 32 | Yes | Set | - |
| 0 | Yes | Reset | - |
| 49 | Yes | - | Set |
| 11681 | Yes | - | Reset |
| 64 | Yes | Set | - |
| 9 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -69,9 +69,9 @@ Warning! LUT value is adjusted to account for LUT combining.
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 60 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 60 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 120 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 140 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 140 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 280 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -82,7 +82,7 @@ Warning! LUT value is adjusted to account for LUT combining.
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 80 | 0.00 |
| DSPs | 0 | 0 | 0 | 220 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
@@ -92,20 +92,20 @@ Warning! LUT value is adjusted to account for LUT combining.
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 76 | 0 | 0 | 100 | 76.00 |
| Bonded IOB | 58 | 0 | 0 | 125 | 46.40 |
| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 96 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 100 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 100 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 4 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 121 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 125 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 125 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
@@ -115,13 +115,13 @@ Warning! LUT value is adjusted to account for LUT combining.
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 4 | 0 | 0 | 32 | 12.50 |
| BUFIO | 0 | 0 | 0 | 8 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 48 | 0.00 |
| BUFR | 0 | 0 | 0 | 8 | 0.00 |
| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
| BUFIO | 0 | 0 | 0 | 16 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 8 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 0 | 16 | 0.00 |
+------------+------+-------+------------+-----------+-------+
@@ -148,23 +148,22 @@ Warning! LUT value is adjusted to account for LUT combining.
+----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+----------+-------+---------------------+
| FDCE | 10710 | Flop & Latch |
| LUT6 | 3858 | LUT |
| MUXF7 | 997 | MuxFx |
| LUT3 | 855 | LUT |
| LUT5 | 846 | LUT |
| LUT2 | 841 | LUT |
| LUT4 | 672 | LUT |
| MUXF8 | 452 | MuxFx |
| FDPE | 366 | Flop & Latch |
| CARRY4 | 274 | CarryLogic |
| LUT1 | 133 | LUT |
| LDCE | 128 | Flop & Latch |
| OBUF | 56 | IO |
| FDSE | 32 | Flop & Latch |
| IBUF | 20 | IO |
| OBUFT | 4 | IO |
| BUFG | 4 | Clock |
| FDCE | 11681 | Flop & Latch |
| LUT6 | 4593 | LUT |
| MUXF7 | 1594 | MuxFx |
| LUT2 | 1186 | LUT |
| LUT3 | 794 | LUT |
| LUT5 | 783 | LUT |
| MUXF8 | 712 | MuxFx |
| LUT1 | 653 | LUT |
| LUT4 | 541 | LUT |
| CARRY4 | 436 | CarryLogic |
| FDSE | 64 | Flop & Latch |
| FDPE | 49 | Flop & Latch |
| IBUF | 32 | IO |
| OBUFT | 27 | IO |
| OBUF | 26 | IO |
| FDRE | 9 | Flop & Latch |
+----------+-------+---------------------+
@@ -174,27 +173,41 @@ Warning! LUT value is adjusted to account for LUT combining.
+------------------------------------+------+
| Ref Name | Used |
+------------------------------------+------+
| mult_gen_au8_bu9_p8 | 4 |
| axis_data_fifo_w32_d32 | 4 |
| c_add_s16_s32 | 3 |
| axis_data_fifo_w8_d128 | 2 |
| vio_cur_flt_state | 1 |
| fifo_generator_1 | 1 |
| fifo_generator_0 | 1 |
| design_a9_1_smartconnect_0_0 | 1 |
| design_a9_1_rst_ps7_0_50M_0 | 1 |
| design_a9_1_processing_system7_0_0 | 1 |
| design_a9_1_axis_data_fifo_2_0 | 1 |
| design_a9_1_axis_data_fifo_1_1 | 1 |
| design_a9_1_axis_data_fifo_1_0 | 1 |
| design_a9_1_axis_data_fifo_0_0 | 1 |
| design_a9_1_axi_smc_0 | 1 |
| design_a9_1_axi_iic_1_0 | 1 |
| design_a9_1_axi_iic_0_0 | 1 |
| design_a9_1_axi_quad_spi_0_0 | 1 |
| design_a9_1_axi_gpio_1_0 | 1 |
| design_a9_1_axi_gpio_0_0 | 1 |
| design_a9_1_axi_dma_2_0 | 1 |
| design_a9_1_axi_dma_1_1 | 1 |
| design_a9_1_axi_dma_1_0 | 1 |
| design_a9_1_axi_dma_0_0 | 1 |
| design_a9_1_axi_bram_ctrl_6_0 | 1 |
| design_a9_1_axi_bram_ctrl_5_0 | 1 |
| design_a9_1_axi_bram_ctrl_4_0 | 1 |
| design_a9_1_axi_bram_ctrl_3_1 | 1 |
| design_a9_1_axi_bram_ctrl_3_0 | 1 |
| design_a9_1_axi_bram_ctrl_2_0 | 1 |
| design_a9_1_axi_bram_ctrl_1_0 | 1 |
| design_a9_1_axi_bram_ctrl_0_0 | 1 |
| dds_stim_16ch | 1 |
| axis_data_fifo_w8_d128 | 1 |
| axis_data_fifo_w32_d16 | 1 |
| design_a9_1_Z_IO_0 | 1 |
| design_a9_1_ZCHECK_SPI_0 | 1 |
| design_a9_1_STIM_SPI_0 | 1 |
| design_a9_1_CHANN_SEL_0 | 1 |
| design_a9_1_CHANN_EN_2 | 1 |
| design_a9_1_CHANN_EN_1 | 1 |
| design_a9_1_CHANN_EN_0 | 1 |
+------------------------------------+------+