GEM/BSI-901-fpga-software
9
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

sync chunk 11/12

Browse Source
This commit is contained in:
chunk-sync
2026-09-11 16:18:36 +08:00
parent c315cef09e
commit c2c1bb2648
922 changed files with 102283 additions and 6793 deletions
Download Patch File Download Diff File Expand all files Collapse all files
c64_pro.runs/impl_1/c64pro_top_utilization_placed.rpt
+116 -95
View File
@@ -1,11 +1,11 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Sun Aug 4 13:42:57 2024
| Host : 840-5CG14025H4 running 64-bit major release (build 9200)
| Date : Fri Sep 4 15:37:38 2026
| Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
| Command : report_utilization -file c64pro_top_utilization_placed.rpt -pb c64pro_top_utilization_placed.pb
| Design : c64pro_top
| Device : xc7z010clg400-2
| Device : xc7z020clg400-2
| Speed File : -2
| Design State : Fully Placed
---------------------------------------------------------------------------------------------------------------------------------------------
@@ -32,16 +32,16 @@ Table of Contents
+----------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs | 12212 | 0 | 0 | 17600 | 69.39 |
| LUT as Logic | 11627 | 0 | 0 | 17600 | 66.06 |
| LUT as Memory | 585 | 0 | 0 | 6000 | 9.75 |
| LUT as Distributed RAM | 444 | 0 | | | |
| LUT as Shift Register | 141 | 0 | | | |
| Slice Registers | 18749 | 0 | 0 | 35200 | 53.26 |
| Register as Flip Flop | 18621 | 0 | 0 | 35200 | 52.90 |
| Register as Latch | 128 | 0 | 0 | 35200 | 0.36 |
| F7 Muxes | 1013 | 0 | 0 | 8800 | 11.51 |
| F8 Muxes | 460 | 0 | 0 | 4400 | 10.45 |
| Slice LUTs | 23324 | 0 | 0 | 53200 | 43.84 |
| LUT as Logic | 21761 | 0 | 0 | 53200 | 40.90 |
| LUT as Memory | 1563 | 0 | 0 | 17400 | 8.98 |
| LUT as Distributed RAM | 558 | 0 | | | |
| LUT as Shift Register | 1005 | 0 | | | |
| Slice Registers | 33794 | 0 | 0 | 106400 | 31.76 |
| Register as Flip Flop | 33794 | 0 | 0 | 106400 | 31.76 |
| Register as Latch | 0 | 0 | 0 | 106400 | 0.00 |
| F7 Muxes | 1872 | 0 | 0 | 26600 | 7.04 |
| F8 Muxes | 792 | 0 | 0 | 13300 | 5.95 |
+----------------------------+-------+-------+------------+-----------+-------+
* Warning! LUT value is adjusted to account for LUT combining.
@@ -58,10 +58,10 @@ Table of Contents
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 370 | Yes | - | Set |
| 11101 | Yes | - | Reset |
| 535 | Yes | Set | - |
| 6743 | Yes | Reset | - |
| 90 | Yes | - | Set |
| 12487 | Yes | - | Reset |
| 859 | Yes | Set | - |
| 20367 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -71,28 +71,28 @@ Table of Contents
+--------------------------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+-------+-------+------------+-----------+-------+
| Slice | 4395 | 0 | 0 | 4400 | 99.89 |
| SLICEL | 2897 | 0 | | | |
| SLICEM | 1498 | 0 | | | |
| LUT as Logic | 11627 | 0 | 0 | 17600 | 66.06 |
| Slice | 11328 | 0 | 0 | 13300 | 85.17 |
| SLICEL | 7545 | 0 | | | |
| SLICEM | 3783 | 0 | | | |
| LUT as Logic | 21761 | 0 | 0 | 53200 | 40.90 |
| using O5 output only | 0 | | | | |
| using O6 output only | 8850 | | | | |
| using O5 and O6 | 2777 | | | | |
| LUT as Memory | 585 | 0 | 0 | 6000 | 9.75 |
| LUT as Distributed RAM | 444 | 0 | | | |
| using O6 output only | 17358 | | | | |
| using O5 and O6 | 4403 | | | | |
| LUT as Memory | 1563 | 0 | 0 | 17400 | 8.98 |
| LUT as Distributed RAM | 558 | 0 | | | |
| using O5 output only | 0 | | | | |
| using O6 output only | 4 | | | | |
| using O5 and O6 | 440 | | | | |
| LUT as Shift Register | 141 | 0 | | | |
| using O5 output only | 0 | | | | |
| using O6 output only | 54 | | | | |
| using O5 and O6 | 87 | | | | |
| Slice Registers | 18749 | 0 | 0 | 35200 | 53.26 |
| Register driven from within the Slice | 7217 | | | | |
| Register driven from outside the Slice | 11532 | | | | |
| LUT in front of the register is unused | 7275 | | | | |
| LUT in front of the register is used | 4257 | | | | |
| Unique Control Sets | 1031 | | 0 | 4400 | 23.43 |
| using O6 output only | 6 | | | | |
| using O5 and O6 | 552 | | | | |
| LUT as Shift Register | 1005 | 0 | | | |
| using O5 output only | 7 | | | | |
| using O6 output only | 185 | | | | |
| using O5 and O6 | 813 | | | | |
| Slice Registers | 33794 | 0 | 0 | 106400 | 31.76 |
| Register driven from within the Slice | 15274 | | | | |
| Register driven from outside the Slice | 18520 | | | | |
| LUT in front of the register is unused | 14377 | | | | |
| LUT in front of the register is used | 4143 | | | | |
| Unique Control Sets | 1907 | | 0 | 13300 | 14.34 |
+--------------------------------------------+-------+-------+------------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
@@ -103,11 +103,11 @@ Table of Contents
+-------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 26 | 0 | 0 | 60 | 43.33 |
| RAMB36/FIFO* | 24 | 0 | 0 | 60 | 40.00 |
| RAMB36E1 only | 24 | | | | |
| RAMB18 | 4 | 0 | 0 | 120 | 3.33 |
| RAMB18E1 only | 4 | | | | |
| Block RAM Tile | 105 | 0 | 0 | 140 | 75.00 |
| RAMB36/FIFO* | 102 | 0 | 0 | 140 | 72.86 |
| RAMB36E1 only | 102 | | | | |
| RAMB18 | 6 | 0 | 0 | 280 | 2.14 |
| RAMB18E1 only | 6 | | | | |
+-------------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -118,7 +118,7 @@ Table of Contents
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 80 | 0.00 |
| DSPs | 0 | 0 | 0 | 220 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
@@ -128,22 +128,25 @@ Table of Contents
+-----------------------------+------+-------+------------+-----------+--------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+--------+
| Bonded IOB | 76 | 76 | 0 | 100 | 76.00 |
| IOB Master Pads | 37 | | | | |
| IOB Slave Pads | 35 | | | | |
| Bonded IOB | 58 | 58 | 0 | 125 | 46.40 |
| IOB Master Pads | 22 | | | | |
| IOB Slave Pads | 34 | | | | |
| IOB Flip Flops | 9 | 9 | | | |
| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 130 | 130 | 0 | 130 | 100.00 |
| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 96 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 100 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 100 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 4 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 121 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 |
| ILOGIC | 6 | 6 | 0 | 125 | 4.80 |
| IFF_Register | 6 | 6 | | | |
| OLOGIC | 3 | 3 | 0 | 125 | 2.40 |
| OUTFF_Register | 3 | 3 | | | |
+-----------------------------+------+-------+------------+-----------+--------+
@@ -153,13 +156,13 @@ Table of Contents
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 |
| BUFIO | 0 | 0 | 0 | 8 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 48 | 0.00 |
| BUFR | 0 | 0 | 0 | 8 | 0.00 |
| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
| BUFIO | 0 | 0 | 0 | 16 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 8 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 0 | 16 | 0.00 |
+------------+------+-------+------------+-----------+-------+
@@ -169,7 +172,7 @@ Table of Contents
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| BSCANE2 | 1 | 0 | 0 | 4 | 25.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
@@ -186,31 +189,33 @@ Table of Contents
+----------+-------+----------------------+
| Ref Name | Used | Functional Category |
+----------+-------+----------------------+
| FDCE | 10973 | Flop & Latch |
| FDRE | 6743 | Flop & Latch |
| LUT6 | 5463 | LUT |
| LUT3 | 2377 | LUT |
| LUT5 | 2076 | LUT |
| LUT2 | 1977 | LUT |
| LUT4 | 1895 | LUT |
| MUXF7 | 1013 | MuxFx |
| RAMD32 | 666 | Distributed Memory |
| LUT1 | 616 | LUT |
| CARRY4 | 565 | CarryLogic |
| FDSE | 535 | Flop & Latch |
| MUXF8 | 460 | MuxFx |
| FDPE | 370 | Flop & Latch |
| SRL16E | 228 | Distributed Memory |
| RAMS32 | 218 | Distributed Memory |
| FDRE | 20367 | Flop & Latch |
| FDCE | 12487 | Flop & Latch |
| LUT6 | 9778 | LUT |
| LUT3 | 4324 | LUT |
| LUT2 | 3478 | LUT |
| LUT4 | 3448 | LUT |
| LUT5 | 3330 | LUT |
| MUXF7 | 1872 | MuxFx |
| LUT1 | 1806 | LUT |
| SRL16E | 1288 | Distributed Memory |
| CARRY4 | 988 | CarryLogic |
| FDSE | 859 | Flop & Latch |
| RAMD32 | 840 | Distributed Memory |
| MUXF8 | 792 | MuxFx |
| SRLC32E | 528 | Distributed Memory |
| RAMS32 | 270 | Distributed Memory |
| BIBUF | 130 | IO |
| LDCE | 128 | Flop & Latch |
| OBUF | 56 | IO |
| RAMB36E1 | 24 | Block Memory |
| IBUF | 20 | IO |
| BUFG | 5 | Clock |
| RAMB18E1 | 4 | Block Memory |
| OBUFT | 4 | IO |
| RAMB36E1 | 102 | Block Memory |
| FDPE | 90 | Flop & Latch |
| IBUF | 32 | IO |
| OBUFT | 27 | IO |
| OBUF | 26 | IO |
| RAMB18E1 | 6 | Block Memory |
| SRLC16E | 2 | Distributed Memory |
| BUFG | 2 | Clock |
| PS7 | 1 | Specialized Resource |
| BSCANE2 | 1 | Others |
+----------+-------+----------------------+
@@ -228,27 +233,43 @@ Table of Contents
+------------------------------------+------+
| Ref Name | Used |
+------------------------------------+------+
| mult_gen_au8_bu9_p8 | 4 |
| axis_data_fifo_w32_d32 | 4 |
| c_add_s16_s32 | 3 |
| axis_data_fifo_w8_d128 | 2 |
| vio_cur_flt_state | 1 |
| u_ila_0 | 1 |
| fifo_generator_1 | 1 |
| fifo_generator_0 | 1 |
| design_a9_1_smartconnect_0_0 | 1 |
| design_a9_1_rst_ps7_0_50M_0 | 1 |
| design_a9_1_processing_system7_0_0 | 1 |
| design_a9_1_axis_data_fifo_2_0 | 1 |
| design_a9_1_axis_data_fifo_1_1 | 1 |
| design_a9_1_axis_data_fifo_1_0 | 1 |
| design_a9_1_axis_data_fifo_0_0 | 1 |
| design_a9_1_axi_smc_0 | 1 |
| design_a9_1_axi_iic_1_0 | 1 |
| design_a9_1_axi_iic_0_0 | 1 |
| design_a9_1_axi_quad_spi_0_0 | 1 |
| design_a9_1_axi_gpio_1_0 | 1 |
| design_a9_1_axi_gpio_0_0 | 1 |
| design_a9_1_axi_dma_2_0 | 1 |
| design_a9_1_axi_dma_1_1 | 1 |
| design_a9_1_axi_dma_1_0 | 1 |
| design_a9_1_axi_dma_0_0 | 1 |
| design_a9_1_axi_bram_ctrl_6_0 | 1 |
| design_a9_1_axi_bram_ctrl_5_0 | 1 |
| design_a9_1_axi_bram_ctrl_4_0 | 1 |
| design_a9_1_axi_bram_ctrl_3_1 | 1 |
| design_a9_1_axi_bram_ctrl_3_0 | 1 |
| design_a9_1_axi_bram_ctrl_2_0 | 1 |
| design_a9_1_axi_bram_ctrl_1_0 | 1 |
| design_a9_1_axi_bram_ctrl_0_0 | 1 |
| dds_stim_16ch | 1 |
| axis_data_fifo_w8_d128 | 1 |
| axis_data_fifo_w32_d16 | 1 |
| design_a9_1_Z_IO_0 | 1 |
| design_a9_1_ZCHECK_SPI_0 | 1 |
| design_a9_1_STIM_SPI_0 | 1 |
| design_a9_1_CHANN_SEL_0 | 1 |
| design_a9_1_CHANN_EN_2 | 1 |
| design_a9_1_CHANN_EN_1 | 1 |
| design_a9_1_CHANN_EN_0 | 1 |
| dbg_hub | 1 |
+------------------------------------+------+