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2026-09-11 16:18:36 +08:00
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c64_pro.runs/impl_1/c64pro_top_power_routed.rpt
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@@ -1,11 +1,11 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Sun Aug 4 13:44:39 2024
| Host : 840-5CG14025H4 running 64-bit major release (build 9200)
| Date : Fri Sep 4 15:41:33 2026
| Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
| Command : report_power -file c64pro_top_power_routed.rpt -pb c64pro_top_power_summary_routed.pb -rpx c64pro_top_power_routed.rpx
| Design : c64pro_top
| Device : xc7z010clg400-2
| Device : xc7z020clg400-2
| Design State : routed
| Grade : commercial
| Process : typical
@@ -30,14 +30,14 @@ Table of Contents
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 1.263 |
| Total On-Chip Power (W) | 1.582 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 1.145 |
| Device Static (W) | 0.118 |
| Dynamic (W) | 1.431 |
| Device Static (W) | 0.151 |
| Effective TJA (C/W) | 11.5 |
| Max Ambient (C) | 70.4 |
| Junction Temperature (C) | 39.6 |
| Max Ambient (C) | 66.7 |
| Junction Temperature (C) | 43.3 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
@@ -52,22 +52,21 @@ Table of Contents
+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks | 0.033 | 3 | --- | --- |
| Slice Logic | 0.021 | 37606 | --- | --- |
| LUT as Logic | 0.019 | 11627 | 17600 | 66.06 |
| CARRY4 | <0.001 | 565 | 4400 | 12.84 |
| Register | <0.001 | 18749 | 35200 | 53.26 |
| LUT as Distributed RAM | <0.001 | 444 | 6000 | 7.40 |
| F7/F8 Muxes | <0.001 | 1473 | 17600 | 8.37 |
| LUT as Shift Register | <0.001 | 141 | 6000 | 2.35 |
| BUFG | <0.001 | 4 | 32 | 12.50 |
| Others | 0.000 | 1299 | --- | --- |
| Signals | 0.033 | 26449 | --- | --- |
| Block RAM | 0.012 | 26 | 60 | 43.33 |
| I/O | 0.003 | 76 | 100 | 76.00 |
| PS7 | 1.043 | 1 | --- | --- |
| Static Power | 0.118 | | | |
| Total | 1.263 | | | |
| Clocks | 0.099 | 4 | --- | --- |
| Slice Logic | 0.038 | 70198 | --- | --- |
| LUT as Logic | 0.034 | 21761 | 53200 | 40.90 |
| Register | 0.002 | 33794 | 106400 | 31.76 |
| CARRY4 | 0.001 | 988 | 13300 | 7.43 |
| F7/F8 Muxes | <0.001 | 2664 | 53200 | 5.01 |
| LUT as Distributed RAM | <0.001 | 558 | 17400 | 3.21 |
| LUT as Shift Register | <0.001 | 1005 | 17400 | 5.78 |
| Others | 0.000 | 3660 | --- | --- |
| Signals | 0.050 | 46880 | --- | --- |
| Block RAM | 0.062 | 105 | 140 | 75.00 |
| I/O | 0.008 | 58 | 125 | 46.40 |
| PS7 | 1.175 | 1 | --- | --- |
| Static Power | 0.151 | | | |
| Total | 1.582 | | | |
+--------------------------+-----------+----------+-----------+-----------------+
@@ -77,25 +76,25 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint | 1.000 | 0.105 | 0.098 | 0.007 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.007 | 0.000 | 0.007 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.002 | 0.001 | 0.001 | NA | Unspecified | NA |
| Vccint | 1.000 | 0.261 | 0.244 | 0.018 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.015 | 0.000 | 0.015 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccbram | 1.000 | 0.003 | 0.001 | 0.002 | NA | Unspecified | NA |
| Vccbram | 1.000 | 0.012 | 0.005 | 0.007 | NA | Unspecified | NA |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccpint | 1.000 | 0.573 | 0.547 | 0.025 | NA | Unspecified | NA |
| Vccpint | 1.000 | 0.707 | 0.678 | 0.029 | NA | Unspecified | NA |
| Vccpaux | 1.800 | 0.035 | 0.025 | 0.010 | NA | Unspecified | NA |
| Vccpll | 1.800 | 0.018 | 0.015 | 0.003 | NA | Unspecified | NA |
| Vccpll | 1.800 | 0.017 | 0.014 | 0.003 | NA | Unspecified | NA |
| Vcco_ddr | 1.350 | 0.311 | 0.309 | 0.002 | NA | Unspecified | NA |
| Vcco_mio0 | 3.300 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
| Vcco_mio1 | 1.800 | 0.002 | 0.001 | 0.001 | NA | Unspecified | NA |
| Vcco_mio1 | 1.800 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
@@ -137,11 +136,12 @@ Table of Contents
2.2 Clock Constraints
---------------------
+------------+--------------------------------------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+------------+--------------------------------------------------------------------------+-----------------+
| clk_fpga_0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | 10.0 |
+------------+--------------------------------------------------------------------------+-----------------+
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------+
| clk_fpga_0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | 10.0 |
| dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TCK | 33.0 |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------+
3. Detailed Reports
@@ -150,33 +150,53 @@ Table of Contents
3.1 By Hierarchy
----------------
+-------------------------------+-----------+
| Name | Power (W) |
+-------------------------------+-----------+
| c64pro_top | 1.145 |
| u_pl_top | 0.043 |
| u_eeg_top | 0.007 |
| u_eeg_upload | 0.002 |
| u_rhs2116_top | 0.017 |
| u_sine_wave_gen | 0.003 |
| u_trans_distribute | 0.003 |
| u_transmit_config | 0.005 |
| u_upload_top | 0.018 |
| u_upload_config | 0.005 |
| u_upload_protocol_intan | 0.002 |
| u_upload_protocol_ql | 0.003 |
| u_upload_sort | 0.008 |
| u_ps_a9_1 | 1.098 |
| design_a9_1_i | 1.089 |
| axi_dma_0 | 0.002 |
| axi_dma_1 | 0.003 |
| axi_iic_0 | 0.001 |
| axi_iic_1 | 0.001 |
| axi_smc | 0.010 |
| axis_data_fifo_0 | 0.004 |
| axis_data_fifo_1 | 0.006 |
| processing_system7_0 | 1.043 |
| smartconnect_0 | 0.016 |
+-------------------------------+-----------+
+---------------------------------------------+-----------+
| Name | Power (W) |
+---------------------------------------------+-----------+
| c64pro_top | 1.431 |
| dbg_hub | 0.003 |
| inst | 0.003 |
| BSCANID.u_xsdbm_id | 0.003 |
| u_ila_0 | 0.040 |
| inst | 0.040 |
| ila_core_inst | 0.040 |
| u_pl_top | 0.082 |
| u0_eeg_top | 0.005 |
| transmit_arrange[0].u_ads1299_arrange | 0.001 |
| u_eeg_upload | 0.001 |
| u0_upload_top | 0.033 |
| u_upload_config | 0.015 |
| u_upload_protocol_intan | 0.003 |
| u_upload_protocol_ql | 0.004 |
| u_upload_sort | 0.010 |
| u1_eeg_top | 0.002 |
| u1_upload_top | 0.029 |
| u_upload_config | 0.012 |
| u_upload_protocol_intan | 0.003 |
| u_upload_protocol_ql | 0.004 |
| u_upload_sort | 0.009 |
| u_cur_mon_top | 0.010 |
| u0_fifo_generator_1 | 0.002 |
| u_cur_mon_config | 0.002 |
| u_cur_monitor | 0.001 |
| u_vio_cur_flt_state | 0.002 |
| u_eeg_emg_upload | 0.003 |
| u0_fifo_generator_0 | 0.003 |
| u_ps_a9_1 | 1.304 |
| design_a9_1_i | 1.298 |
| CUR_SPI | 0.004 |
| STIM_SPI | 0.004 |
| ZCHECK_SPI | 0.004 |
| axi_dma_0 | 0.002 |
| axi_dma_1 | 0.005 |
| axi_dma_2 | 0.005 |
| axi_dma_3 | 0.005 |
| axi_smc | 0.020 |
| axis_data_fifo_1 | 0.001 |
| axis_data_fifo_2 | 0.012 |
| axis_data_fifo_3 | 0.033 |
| processing_system7_0 | 1.175 |
| smartconnect_0 | 0.025 |
+---------------------------------------------+-----------+