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2026-09-11 16:18:36 +08:00
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c64_pro.runs/impl_1/c64pro_top_placed.dcp
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c64_pro.runs/impl_1/c64pro_top_power_routed.rpt
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@@ -1,11 +1,11 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Sun Aug 4 13:44:39 2024
| Host : 840-5CG14025H4 running 64-bit major release (build 9200)
| Date : Fri Sep 4 15:41:33 2026
| Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
| Command : report_power -file c64pro_top_power_routed.rpt -pb c64pro_top_power_summary_routed.pb -rpx c64pro_top_power_routed.rpx
| Design : c64pro_top
| Device : xc7z010clg400-2
| Device : xc7z020clg400-2
| Design State : routed
| Grade : commercial
| Process : typical
@@ -30,14 +30,14 @@ Table of Contents
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 1.263 |
| Total On-Chip Power (W) | 1.582 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 1.145 |
| Device Static (W) | 0.118 |
| Dynamic (W) | 1.431 |
| Device Static (W) | 0.151 |
| Effective TJA (C/W) | 11.5 |
| Max Ambient (C) | 70.4 |
| Junction Temperature (C) | 39.6 |
| Max Ambient (C) | 66.7 |
| Junction Temperature (C) | 43.3 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
@@ -52,22 +52,21 @@ Table of Contents
+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks | 0.033 | 3 | --- | --- |
| Slice Logic | 0.021 | 37606 | --- | --- |
| LUT as Logic | 0.019 | 11627 | 17600 | 66.06 |
| CARRY4 | <0.001 | 565 | 4400 | 12.84 |
| Register | <0.001 | 18749 | 35200 | 53.26 |
| LUT as Distributed RAM | <0.001 | 444 | 6000 | 7.40 |
| F7/F8 Muxes | <0.001 | 1473 | 17600 | 8.37 |
| LUT as Shift Register | <0.001 | 141 | 6000 | 2.35 |
| BUFG | <0.001 | 4 | 32 | 12.50 |
| Others | 0.000 | 1299 | --- | --- |
| Signals | 0.033 | 26449 | --- | --- |
| Block RAM | 0.012 | 26 | 60 | 43.33 |
| I/O | 0.003 | 76 | 100 | 76.00 |
| PS7 | 1.043 | 1 | --- | --- |
| Static Power | 0.118 | | | |
| Total | 1.263 | | | |
| Clocks | 0.099 | 4 | --- | --- |
| Slice Logic | 0.038 | 70198 | --- | --- |
| LUT as Logic | 0.034 | 21761 | 53200 | 40.90 |
| Register | 0.002 | 33794 | 106400 | 31.76 |
| CARRY4 | 0.001 | 988 | 13300 | 7.43 |
| F7/F8 Muxes | <0.001 | 2664 | 53200 | 5.01 |
| LUT as Distributed RAM | <0.001 | 558 | 17400 | 3.21 |
| LUT as Shift Register | <0.001 | 1005 | 17400 | 5.78 |
| Others | 0.000 | 3660 | --- | --- |
| Signals | 0.050 | 46880 | --- | --- |
| Block RAM | 0.062 | 105 | 140 | 75.00 |
| I/O | 0.008 | 58 | 125 | 46.40 |
| PS7 | 1.175 | 1 | --- | --- |
| Static Power | 0.151 | | | |
| Total | 1.582 | | | |
+--------------------------+-----------+----------+-----------+-----------------+
@@ -77,25 +76,25 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint | 1.000 | 0.105 | 0.098 | 0.007 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.007 | 0.000 | 0.007 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.002 | 0.001 | 0.001 | NA | Unspecified | NA |
| Vccint | 1.000 | 0.261 | 0.244 | 0.018 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.015 | 0.000 | 0.015 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccbram | 1.000 | 0.003 | 0.001 | 0.002 | NA | Unspecified | NA |
| Vccbram | 1.000 | 0.012 | 0.005 | 0.007 | NA | Unspecified | NA |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccpint | 1.000 | 0.573 | 0.547 | 0.025 | NA | Unspecified | NA |
| Vccpint | 1.000 | 0.707 | 0.678 | 0.029 | NA | Unspecified | NA |
| Vccpaux | 1.800 | 0.035 | 0.025 | 0.010 | NA | Unspecified | NA |
| Vccpll | 1.800 | 0.018 | 0.015 | 0.003 | NA | Unspecified | NA |
| Vccpll | 1.800 | 0.017 | 0.014 | 0.003 | NA | Unspecified | NA |
| Vcco_ddr | 1.350 | 0.311 | 0.309 | 0.002 | NA | Unspecified | NA |
| Vcco_mio0 | 3.300 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
| Vcco_mio1 | 1.800 | 0.002 | 0.001 | 0.001 | NA | Unspecified | NA |
| Vcco_mio1 | 1.800 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
@@ -137,11 +136,12 @@ Table of Contents
2.2 Clock Constraints
---------------------
+------------+--------------------------------------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+------------+--------------------------------------------------------------------------+-----------------+
| clk_fpga_0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | 10.0 |
+------------+--------------------------------------------------------------------------+-----------------+
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------+
| clk_fpga_0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | 10.0 |
| dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TCK | 33.0 |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------+
3. Detailed Reports
@@ -150,33 +150,53 @@ Table of Contents
3.1 By Hierarchy
----------------
+-------------------------------+-----------+
| Name | Power (W) |
+-------------------------------+-----------+
| c64pro_top | 1.145 |
| u_pl_top | 0.043 |
| u_eeg_top | 0.007 |
| u_eeg_upload | 0.002 |
| u_rhs2116_top | 0.017 |
| u_sine_wave_gen | 0.003 |
| u_trans_distribute | 0.003 |
| u_transmit_config | 0.005 |
| u_upload_top | 0.018 |
| u_upload_config | 0.005 |
| u_upload_protocol_intan | 0.002 |
| u_upload_protocol_ql | 0.003 |
| u_upload_sort | 0.008 |
| u_ps_a9_1 | 1.098 |
| design_a9_1_i | 1.089 |
| axi_dma_0 | 0.002 |
| axi_dma_1 | 0.003 |
| axi_iic_0 | 0.001 |
| axi_iic_1 | 0.001 |
| axi_smc | 0.010 |
| axis_data_fifo_0 | 0.004 |
| axis_data_fifo_1 | 0.006 |
| processing_system7_0 | 1.043 |
| smartconnect_0 | 0.016 |
+-------------------------------+-----------+
+---------------------------------------------+-----------+
| Name | Power (W) |
+---------------------------------------------+-----------+
| c64pro_top | 1.431 |
| dbg_hub | 0.003 |
| inst | 0.003 |
| BSCANID.u_xsdbm_id | 0.003 |
| u_ila_0 | 0.040 |
| inst | 0.040 |
| ila_core_inst | 0.040 |
| u_pl_top | 0.082 |
| u0_eeg_top | 0.005 |
| transmit_arrange[0].u_ads1299_arrange | 0.001 |
| u_eeg_upload | 0.001 |
| u0_upload_top | 0.033 |
| u_upload_config | 0.015 |
| u_upload_protocol_intan | 0.003 |
| u_upload_protocol_ql | 0.004 |
| u_upload_sort | 0.010 |
| u1_eeg_top | 0.002 |
| u1_upload_top | 0.029 |
| u_upload_config | 0.012 |
| u_upload_protocol_intan | 0.003 |
| u_upload_protocol_ql | 0.004 |
| u_upload_sort | 0.009 |
| u_cur_mon_top | 0.010 |
| u0_fifo_generator_1 | 0.002 |
| u_cur_mon_config | 0.002 |
| u_cur_monitor | 0.001 |
| u_vio_cur_flt_state | 0.002 |
| u_eeg_emg_upload | 0.003 |
| u0_fifo_generator_0 | 0.003 |
| u_ps_a9_1 | 1.304 |
| design_a9_1_i | 1.298 |
| CUR_SPI | 0.004 |
| STIM_SPI | 0.004 |
| ZCHECK_SPI | 0.004 |
| axi_dma_0 | 0.002 |
| axi_dma_1 | 0.005 |
| axi_dma_2 | 0.005 |
| axi_dma_3 | 0.005 |
| axi_smc | 0.020 |
| axis_data_fifo_1 | 0.001 |
| axis_data_fifo_2 | 0.012 |
| axis_data_fifo_3 | 0.033 |
| processing_system7_0 | 1.175 |
| smartconnect_0 | 0.025 |
+---------------------------------------------+-----------+
c64_pro.runs/impl_1/c64pro_top_power_routed.rpx
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c64_pro.runs/impl_1/c64pro_top_power_summary_routed.pb
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c64_pro.runs/impl_1/c64pro_top_route_status.pb
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c64_pro.runs/impl_1/c64pro_top_route_status.rpt
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Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 43247 :
# of nets not needing routing.......... : 16664 :
# of internally routed nets........ : 16304 :
# of nets with no loads............ : 360 :
# of routable nets..................... : 26583 :
# of fully routed nets............. : 26583 :
# of logical nets.......................... : 84782 :
# of nets not needing routing.......... : 37766 :
# of internally routed nets........ : 37183 :
# of nets with no loads............ : 583 :
# of routable nets..................... : 47016 :
# of fully routed nets............. : 47016 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :
c64_pro.runs/impl_1/c64pro_top_routed.dcp
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c64_pro.runs/impl_1/c64pro_top_timing_summary_routed.pb
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c64_pro.runs/impl_1/c64pro_top_timing_summary_routed.rpt
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c64_pro.runs/impl_1/c64pro_top_timing_summary_routed.rpx
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c64_pro.runs/impl_1/c64pro_top_utilization_placed.pb
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c64_pro.runs/impl_1/c64pro_top_utilization_placed.rpt
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Sun Aug 4 13:42:57 2024
| Host : 840-5CG14025H4 running 64-bit major release (build 9200)
| Date : Fri Sep 4 15:37:38 2026
| Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
| Command : report_utilization -file c64pro_top_utilization_placed.rpt -pb c64pro_top_utilization_placed.pb
| Design : c64pro_top
| Device : xc7z010clg400-2
| Device : xc7z020clg400-2
| Speed File : -2
| Design State : Fully Placed
---------------------------------------------------------------------------------------------------------------------------------------------
@@ -32,16 +32,16 @@ Table of Contents
+----------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs | 12212 | 0 | 0 | 17600 | 69.39 |
| LUT as Logic | 11627 | 0 | 0 | 17600 | 66.06 |
| LUT as Memory | 585 | 0 | 0 | 6000 | 9.75 |
| LUT as Distributed RAM | 444 | 0 | | | |
| LUT as Shift Register | 141 | 0 | | | |
| Slice Registers | 18749 | 0 | 0 | 35200 | 53.26 |
| Register as Flip Flop | 18621 | 0 | 0 | 35200 | 52.90 |
| Register as Latch | 128 | 0 | 0 | 35200 | 0.36 |
| F7 Muxes | 1013 | 0 | 0 | 8800 | 11.51 |
| F8 Muxes | 460 | 0 | 0 | 4400 | 10.45 |
| Slice LUTs | 23324 | 0 | 0 | 53200 | 43.84 |
| LUT as Logic | 21761 | 0 | 0 | 53200 | 40.90 |
| LUT as Memory | 1563 | 0 | 0 | 17400 | 8.98 |
| LUT as Distributed RAM | 558 | 0 | | | |
| LUT as Shift Register | 1005 | 0 | | | |
| Slice Registers | 33794 | 0 | 0 | 106400 | 31.76 |
| Register as Flip Flop | 33794 | 0 | 0 | 106400 | 31.76 |
| Register as Latch | 0 | 0 | 0 | 106400 | 0.00 |
| F7 Muxes | 1872 | 0 | 0 | 26600 | 7.04 |
| F8 Muxes | 792 | 0 | 0 | 13300 | 5.95 |
+----------------------------+-------+-------+------------+-----------+-------+
* Warning! LUT value is adjusted to account for LUT combining.
@@ -58,10 +58,10 @@ Table of Contents
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 370 | Yes | - | Set |
| 11101 | Yes | - | Reset |
| 535 | Yes | Set | - |
| 6743 | Yes | Reset | - |
| 90 | Yes | - | Set |
| 12487 | Yes | - | Reset |
| 859 | Yes | Set | - |
| 20367 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -71,28 +71,28 @@ Table of Contents
+--------------------------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+-------+-------+------------+-----------+-------+
| Slice | 4395 | 0 | 0 | 4400 | 99.89 |
| SLICEL | 2897 | 0 | | | |
| SLICEM | 1498 | 0 | | | |
| LUT as Logic | 11627 | 0 | 0 | 17600 | 66.06 |
| Slice | 11328 | 0 | 0 | 13300 | 85.17 |
| SLICEL | 7545 | 0 | | | |
| SLICEM | 3783 | 0 | | | |
| LUT as Logic | 21761 | 0 | 0 | 53200 | 40.90 |
| using O5 output only | 0 | | | | |
| using O6 output only | 8850 | | | | |
| using O5 and O6 | 2777 | | | | |
| LUT as Memory | 585 | 0 | 0 | 6000 | 9.75 |
| LUT as Distributed RAM | 444 | 0 | | | |
| using O6 output only | 17358 | | | | |
| using O5 and O6 | 4403 | | | | |
| LUT as Memory | 1563 | 0 | 0 | 17400 | 8.98 |
| LUT as Distributed RAM | 558 | 0 | | | |
| using O5 output only | 0 | | | | |
| using O6 output only | 4 | | | | |
| using O5 and O6 | 440 | | | | |
| LUT as Shift Register | 141 | 0 | | | |
| using O5 output only | 0 | | | | |
| using O6 output only | 54 | | | | |
| using O5 and O6 | 87 | | | | |
| Slice Registers | 18749 | 0 | 0 | 35200 | 53.26 |
| Register driven from within the Slice | 7217 | | | | |
| Register driven from outside the Slice | 11532 | | | | |
| LUT in front of the register is unused | 7275 | | | | |
| LUT in front of the register is used | 4257 | | | | |
| Unique Control Sets | 1031 | | 0 | 4400 | 23.43 |
| using O6 output only | 6 | | | | |
| using O5 and O6 | 552 | | | | |
| LUT as Shift Register | 1005 | 0 | | | |
| using O5 output only | 7 | | | | |
| using O6 output only | 185 | | | | |
| using O5 and O6 | 813 | | | | |
| Slice Registers | 33794 | 0 | 0 | 106400 | 31.76 |
| Register driven from within the Slice | 15274 | | | | |
| Register driven from outside the Slice | 18520 | | | | |
| LUT in front of the register is unused | 14377 | | | | |
| LUT in front of the register is used | 4143 | | | | |
| Unique Control Sets | 1907 | | 0 | 13300 | 14.34 |
+--------------------------------------------+-------+-------+------------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
@@ -103,11 +103,11 @@ Table of Contents
+-------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 26 | 0 | 0 | 60 | 43.33 |
| RAMB36/FIFO* | 24 | 0 | 0 | 60 | 40.00 |
| RAMB36E1 only | 24 | | | | |
| RAMB18 | 4 | 0 | 0 | 120 | 3.33 |
| RAMB18E1 only | 4 | | | | |
| Block RAM Tile | 105 | 0 | 0 | 140 | 75.00 |
| RAMB36/FIFO* | 102 | 0 | 0 | 140 | 72.86 |
| RAMB36E1 only | 102 | | | | |
| RAMB18 | 6 | 0 | 0 | 280 | 2.14 |
| RAMB18E1 only | 6 | | | | |
+-------------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -118,7 +118,7 @@ Table of Contents
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 80 | 0.00 |
| DSPs | 0 | 0 | 0 | 220 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
@@ -128,22 +128,25 @@ Table of Contents
+-----------------------------+------+-------+------------+-----------+--------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+--------+
| Bonded IOB | 76 | 76 | 0 | 100 | 76.00 |
| IOB Master Pads | 37 | | | | |
| IOB Slave Pads | 35 | | | | |
| Bonded IOB | 58 | 58 | 0 | 125 | 46.40 |
| IOB Master Pads | 22 | | | | |
| IOB Slave Pads | 34 | | | | |
| IOB Flip Flops | 9 | 9 | | | |
| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 130 | 130 | 0 | 130 | 100.00 |
| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 96 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 100 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 100 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 4 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 121 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 |
| ILOGIC | 6 | 6 | 0 | 125 | 4.80 |
| IFF_Register | 6 | 6 | | | |
| OLOGIC | 3 | 3 | 0 | 125 | 2.40 |
| OUTFF_Register | 3 | 3 | | | |
+-----------------------------+------+-------+------------+-----------+--------+
@@ -153,13 +156,13 @@ Table of Contents
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 |
| BUFIO | 0 | 0 | 0 | 8 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 48 | 0.00 |
| BUFR | 0 | 0 | 0 | 8 | 0.00 |
| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
| BUFIO | 0 | 0 | 0 | 16 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 4 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 8 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 0 | 16 | 0.00 |
+------------+------+-------+------------+-----------+-------+
@@ -169,7 +172,7 @@ Table of Contents
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| BSCANE2 | 1 | 0 | 0 | 4 | 25.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
@@ -186,31 +189,33 @@ Table of Contents
+----------+-------+----------------------+
| Ref Name | Used | Functional Category |
+----------+-------+----------------------+
| FDCE | 10973 | Flop & Latch |
| FDRE | 6743 | Flop & Latch |
| LUT6 | 5463 | LUT |
| LUT3 | 2377 | LUT |
| LUT5 | 2076 | LUT |
| LUT2 | 1977 | LUT |
| LUT4 | 1895 | LUT |
| MUXF7 | 1013 | MuxFx |
| RAMD32 | 666 | Distributed Memory |
| LUT1 | 616 | LUT |
| CARRY4 | 565 | CarryLogic |
| FDSE | 535 | Flop & Latch |
| MUXF8 | 460 | MuxFx |
| FDPE | 370 | Flop & Latch |
| SRL16E | 228 | Distributed Memory |
| RAMS32 | 218 | Distributed Memory |
| FDRE | 20367 | Flop & Latch |
| FDCE | 12487 | Flop & Latch |
| LUT6 | 9778 | LUT |
| LUT3 | 4324 | LUT |
| LUT2 | 3478 | LUT |
| LUT4 | 3448 | LUT |
| LUT5 | 3330 | LUT |
| MUXF7 | 1872 | MuxFx |
| LUT1 | 1806 | LUT |
| SRL16E | 1288 | Distributed Memory |
| CARRY4 | 988 | CarryLogic |
| FDSE | 859 | Flop & Latch |
| RAMD32 | 840 | Distributed Memory |
| MUXF8 | 792 | MuxFx |
| SRLC32E | 528 | Distributed Memory |
| RAMS32 | 270 | Distributed Memory |
| BIBUF | 130 | IO |
| LDCE | 128 | Flop & Latch |
| OBUF | 56 | IO |
| RAMB36E1 | 24 | Block Memory |
| IBUF | 20 | IO |
| BUFG | 5 | Clock |
| RAMB18E1 | 4 | Block Memory |
| OBUFT | 4 | IO |
| RAMB36E1 | 102 | Block Memory |
| FDPE | 90 | Flop & Latch |
| IBUF | 32 | IO |
| OBUFT | 27 | IO |
| OBUF | 26 | IO |
| RAMB18E1 | 6 | Block Memory |
| SRLC16E | 2 | Distributed Memory |
| BUFG | 2 | Clock |
| PS7 | 1 | Specialized Resource |
| BSCANE2 | 1 | Others |
+----------+-------+----------------------+
@@ -228,27 +233,43 @@ Table of Contents
+------------------------------------+------+
| Ref Name | Used |
+------------------------------------+------+
| mult_gen_au8_bu9_p8 | 4 |
| axis_data_fifo_w32_d32 | 4 |
| c_add_s16_s32 | 3 |
| axis_data_fifo_w8_d128 | 2 |
| vio_cur_flt_state | 1 |
| u_ila_0 | 1 |
| fifo_generator_1 | 1 |
| fifo_generator_0 | 1 |
| design_a9_1_smartconnect_0_0 | 1 |
| design_a9_1_rst_ps7_0_50M_0 | 1 |
| design_a9_1_processing_system7_0_0 | 1 |
| design_a9_1_axis_data_fifo_2_0 | 1 |
| design_a9_1_axis_data_fifo_1_1 | 1 |
| design_a9_1_axis_data_fifo_1_0 | 1 |
| design_a9_1_axis_data_fifo_0_0 | 1 |
| design_a9_1_axi_smc_0 | 1 |
| design_a9_1_axi_iic_1_0 | 1 |
| design_a9_1_axi_iic_0_0 | 1 |
| design_a9_1_axi_quad_spi_0_0 | 1 |
| design_a9_1_axi_gpio_1_0 | 1 |
| design_a9_1_axi_gpio_0_0 | 1 |
| design_a9_1_axi_dma_2_0 | 1 |
| design_a9_1_axi_dma_1_1 | 1 |
| design_a9_1_axi_dma_1_0 | 1 |
| design_a9_1_axi_dma_0_0 | 1 |
| design_a9_1_axi_bram_ctrl_6_0 | 1 |
| design_a9_1_axi_bram_ctrl_5_0 | 1 |
| design_a9_1_axi_bram_ctrl_4_0 | 1 |
| design_a9_1_axi_bram_ctrl_3_1 | 1 |
| design_a9_1_axi_bram_ctrl_3_0 | 1 |
| design_a9_1_axi_bram_ctrl_2_0 | 1 |
| design_a9_1_axi_bram_ctrl_1_0 | 1 |
| design_a9_1_axi_bram_ctrl_0_0 | 1 |
| dds_stim_16ch | 1 |
| axis_data_fifo_w8_d128 | 1 |
| axis_data_fifo_w32_d16 | 1 |
| design_a9_1_Z_IO_0 | 1 |
| design_a9_1_ZCHECK_SPI_0 | 1 |
| design_a9_1_STIM_SPI_0 | 1 |
| design_a9_1_CHANN_SEL_0 | 1 |
| design_a9_1_CHANN_EN_2 | 1 |
| design_a9_1_CHANN_EN_1 | 1 |
| design_a9_1_CHANN_EN_0 | 1 |
| dbg_hub | 1 |
+------------------------------------+------+
c64_pro.runs/impl_1/debug_nets.ltx
+3333
View File
File diff suppressed because it is too large Load Diff
c64_pro.runs/impl_1/gen_run.xml
+106 -157
View File
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7z010clg400-2" LaunchTime="1722749886">
<GenRun Id="impl_1" LaunchPart="xc7z020clg400-2" LaunchTime="1788506600">
<File Type="ROUTE-PWR" Name="c64pro_top_power_routed.rpt"/>
<File Type="PA-TCL" Name="c64pro_top.tcl"/>
<File Type="ROUTE-PWR-SUM" Name="c64pro_top_power_summary_routed.pb"/>
@@ -86,13 +86,6 @@
<File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/design_a9_1/design_a9_1.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -107,13 +100,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/switch/adg1414_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_arrange.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -121,13 +107,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_spi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -142,27 +121,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/switch/channel_switch.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/cnv_res_collect.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/utils/debouncing.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -177,6 +135,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/upload/eeg_emg_upload.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -191,13 +156,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/emg/emg_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/led_ctrl.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -219,13 +177,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/rhs2116_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/utils/run_time.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -233,83 +184,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/sine_gen.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/utils/spi_full_duplex_master.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/stim_event_collect.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/stim_monitor.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_arrange.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_distribute.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_timer.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/transmit_config.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/transmit_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/trigger/trigger_detection.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/trigger/trigger_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_config.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -352,6 +226,90 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_mon_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_mon_config.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_ch_map.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_monitor.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/acq_collect.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/ad7689_dual_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/stim_config.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_top1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_spi1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_if1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="c64pro_top"/>
@@ -377,25 +335,8 @@
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_misc.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_pm.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_rsh2116.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/c64pro_pins_ic.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
@@ -417,10 +358,18 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w32_d32"/>
<BlockFileSet Type="BlockSrcs" Name="dds_stim_16ch"/>
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w32_d16"/>
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w8_d128"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axi_gpio_0_0"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_CHANN_EN_1"/>
<BlockFileSet Type="BlockSrcs" Name="fifo_generator_1"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_processing_system7_0_0"/>
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w8_d128"/>
<BlockFileSet Type="BlockSrcs" Name="fifo_generator_0"/>
<BlockFileSet Type="BlockSrcs" Name="c_add_s16_s32"/>
<BlockFileSet Type="BlockSrcs" Name="vio_cur_flt_state"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_CHANN_EN_2"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_STIM_SPI_0"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_ZCHECK_SPI_0"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axis_data_fifo_1_1"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axis_data_fifo_2_0"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axi_dma_1_1"/>
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axi_dma_2_0"/>
</GenRun>
c64_pro.runs/impl_1/init_design.pb
BIN
View File
Binary file not shown.
c64_pro.runs/impl_1/opt_design.pb
BIN
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Binary file not shown.
c64_pro.runs/impl_1/place_design.pb
BIN
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Binary file not shown.
c64_pro.runs/impl_1/project.wdf
+207 -25
View File
@@ -1,30 +1,70 @@
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3530:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3530:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3530:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3533:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3533:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3533:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:36:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3530:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3530:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3530:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3533:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3533:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3533:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6432353233623139653262643461386238663261323330623032333436393263:506172656e742050412070726f6a656374204944:00
eof:2414909475
eof:1170702916
c64_pro.runs/impl_1/route_design.pb
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c64_pro.runs/impl_1/runme.log
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c64_pro.runs/impl_1/runme.sh
+1 -1
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@@ -25,7 +25,7 @@ else
fi
export LD_LIBRARY_PATH
HD_PWD='D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1'
HD_PWD='D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/impl_1'
cd "$HD_PWD"
HD_LOG=runme.log
c64_pro.runs/impl_1/vivado.jou
+6 -6
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@@ -3,12 +3,12 @@
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Sun Aug 4 13:40:39 2024
# Process ID: 63460
# Current directory: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1
# Start of session at: Fri Sep 4 15:27:55 2026
# Process ID: 20488
# Current directory: D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/impl_1
# Command line: vivado.exe -log c64pro_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source c64pro_top.tcl -notrace
# Log file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1/c64pro_top.vdi
# Journal file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1\vivado.jou
# Running On: 840-5CG14025H4, OS: Windows, CPU Frequency: 2803 MHz, CPU Physical cores: 4, Host memory: 34024 MB
# Log file: D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/impl_1/c64pro_top.vdi
# Journal file: D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/impl_1\vivado.jou
# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
#-----------------------------------------------------------
source c64pro_top.tcl -notrace
c64_pro.runs/impl_1/vivado.pb
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c64_pro.runs/impl_1/write_bitstream.pb
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