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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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// Date : Wed Jun 24 13:54:12 2026
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// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_dma_2_0_stub.v
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// Design : design_a9_1_axi_dma_2_0
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z020clg400-2
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "axi_dma,Vivado 2023.1" *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_lite_aclk, m_axi_s2mm_aclk, axi_resetn,
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s_axi_lite_awvalid, s_axi_lite_awready, s_axi_lite_awaddr, s_axi_lite_wvalid,
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s_axi_lite_wready, s_axi_lite_wdata, s_axi_lite_bresp, s_axi_lite_bvalid,
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s_axi_lite_bready, s_axi_lite_arvalid, s_axi_lite_arready, s_axi_lite_araddr,
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s_axi_lite_rvalid, s_axi_lite_rready, s_axi_lite_rdata, s_axi_lite_rresp,
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m_axi_s2mm_awaddr, m_axi_s2mm_awlen, m_axi_s2mm_awsize, m_axi_s2mm_awburst,
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m_axi_s2mm_awprot, m_axi_s2mm_awcache, m_axi_s2mm_awvalid, m_axi_s2mm_awready,
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m_axi_s2mm_wdata, m_axi_s2mm_wstrb, m_axi_s2mm_wlast, m_axi_s2mm_wvalid,
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m_axi_s2mm_wready, m_axi_s2mm_bresp, m_axi_s2mm_bvalid, m_axi_s2mm_bready,
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s2mm_prmry_reset_out_n, s_axis_s2mm_tdata, s_axis_s2mm_tkeep, s_axis_s2mm_tvalid,
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s_axis_s2mm_tready, s_axis_s2mm_tlast, s2mm_introut, axi_dma_tstvec)
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/* synthesis syn_black_box black_box_pad_pin="axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_s2mm_awaddr[31:0],m_axi_s2mm_awlen[7:0],m_axi_s2mm_awsize[2:0],m_axi_s2mm_awburst[1:0],m_axi_s2mm_awprot[2:0],m_axi_s2mm_awcache[3:0],m_axi_s2mm_awvalid,m_axi_s2mm_awready,m_axi_s2mm_wdata[31:0],m_axi_s2mm_wstrb[3:0],m_axi_s2mm_wlast,m_axi_s2mm_wvalid,m_axi_s2mm_wready,m_axi_s2mm_bresp[1:0],m_axi_s2mm_bvalid,m_axi_s2mm_bready,s2mm_prmry_reset_out_n,s_axis_s2mm_tdata[31:0],s_axis_s2mm_tkeep[3:0],s_axis_s2mm_tvalid,s_axis_s2mm_tready,s_axis_s2mm_tlast,s2mm_introut,axi_dma_tstvec[31:0]" */
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/* synthesis syn_force_seq_prim="s_axi_lite_aclk" */
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/* synthesis syn_force_seq_prim="m_axi_s2mm_aclk" */;
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input s_axi_lite_aclk /* synthesis syn_isclock = 1 */;
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input m_axi_s2mm_aclk /* synthesis syn_isclock = 1 */;
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input axi_resetn;
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input s_axi_lite_awvalid;
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output s_axi_lite_awready;
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input [9:0]s_axi_lite_awaddr;
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input s_axi_lite_wvalid;
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output s_axi_lite_wready;
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input [31:0]s_axi_lite_wdata;
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output [1:0]s_axi_lite_bresp;
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output s_axi_lite_bvalid;
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input s_axi_lite_bready;
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input s_axi_lite_arvalid;
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output s_axi_lite_arready;
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input [9:0]s_axi_lite_araddr;
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output s_axi_lite_rvalid;
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input s_axi_lite_rready;
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output [31:0]s_axi_lite_rdata;
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output [1:0]s_axi_lite_rresp;
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output [31:0]m_axi_s2mm_awaddr;
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output [7:0]m_axi_s2mm_awlen;
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output [2:0]m_axi_s2mm_awsize;
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output [1:0]m_axi_s2mm_awburst;
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output [2:0]m_axi_s2mm_awprot;
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output [3:0]m_axi_s2mm_awcache;
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output m_axi_s2mm_awvalid;
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input m_axi_s2mm_awready;
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output [31:0]m_axi_s2mm_wdata;
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output [3:0]m_axi_s2mm_wstrb;
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output m_axi_s2mm_wlast;
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output m_axi_s2mm_wvalid;
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input m_axi_s2mm_wready;
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input [1:0]m_axi_s2mm_bresp;
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input m_axi_s2mm_bvalid;
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output m_axi_s2mm_bready;
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output s2mm_prmry_reset_out_n;
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input [31:0]s_axis_s2mm_tdata;
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input [3:0]s_axis_s2mm_tkeep;
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input s_axis_s2mm_tvalid;
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output s_axis_s2mm_tready;
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input s_axis_s2mm_tlast;
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output s2mm_introut;
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output [31:0]axi_dma_tstvec;
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endmodule
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@@ -0,0 +1,73 @@
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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-- Date : Wed Jun 24 13:54:12 2026
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-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_dma_2_0_stub.vhdl
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-- Design : design_a9_1_axi_dma_2_0
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7z020clg400-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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Port (
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s_axi_lite_aclk : in STD_LOGIC;
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m_axi_s2mm_aclk : in STD_LOGIC;
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axi_resetn : in STD_LOGIC;
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s_axi_lite_awvalid : in STD_LOGIC;
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s_axi_lite_awready : out STD_LOGIC;
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s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
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s_axi_lite_wvalid : in STD_LOGIC;
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s_axi_lite_wready : out STD_LOGIC;
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s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
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s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
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s_axi_lite_bvalid : out STD_LOGIC;
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s_axi_lite_bready : in STD_LOGIC;
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s_axi_lite_arvalid : in STD_LOGIC;
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s_axi_lite_arready : out STD_LOGIC;
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s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
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s_axi_lite_rvalid : out STD_LOGIC;
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s_axi_lite_rready : in STD_LOGIC;
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s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
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s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
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m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
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m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
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m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
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m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
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m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
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m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axi_s2mm_awvalid : out STD_LOGIC;
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m_axi_s2mm_awready : in STD_LOGIC;
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m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
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m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axi_s2mm_wlast : out STD_LOGIC;
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m_axi_s2mm_wvalid : out STD_LOGIC;
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m_axi_s2mm_wready : in STD_LOGIC;
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m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
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m_axi_s2mm_bvalid : in STD_LOGIC;
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m_axi_s2mm_bready : out STD_LOGIC;
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s2mm_prmry_reset_out_n : out STD_LOGIC;
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s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
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s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
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s_axis_s2mm_tvalid : in STD_LOGIC;
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s_axis_s2mm_tready : out STD_LOGIC;
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s_axis_s2mm_tlast : in STD_LOGIC;
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s2mm_introut : out STD_LOGIC;
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axi_dma_tstvec : out STD_LOGIC_VECTOR ( 31 downto 0 )
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);
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end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "s_axi_lite_aclk,m_axi_s2mm_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_s2mm_awaddr[31:0],m_axi_s2mm_awlen[7:0],m_axi_s2mm_awsize[2:0],m_axi_s2mm_awburst[1:0],m_axi_s2mm_awprot[2:0],m_axi_s2mm_awcache[3:0],m_axi_s2mm_awvalid,m_axi_s2mm_awready,m_axi_s2mm_wdata[31:0],m_axi_s2mm_wstrb[3:0],m_axi_s2mm_wlast,m_axi_s2mm_wvalid,m_axi_s2mm_wready,m_axi_s2mm_bresp[1:0],m_axi_s2mm_bvalid,m_axi_s2mm_bready,s2mm_prmry_reset_out_n,s_axis_s2mm_tdata[31:0],s_axis_s2mm_tkeep[3:0],s_axis_s2mm_tvalid,s_axis_s2mm_tready,s_axis_s2mm_tlast,s2mm_introut,axi_dma_tstvec[31:0]";
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attribute x_core_info : string;
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attribute x_core_info of stub : architecture is "axi_dma,Vivado 2023.1";
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begin
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end;
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@@ -0,0 +1,2 @@
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||||
NumberHits:1
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||||
Timestamp: Wed Jun 24 05:54:37 UTC 2026
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