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2026-09-11 14:44:43 +08:00
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c64_pro.cache/ip/2023.1/9/d/9d0181c5500db426/9d0181c5500db426.xci
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c64_pro.cache/ip/2023.1/9/d/9d0181c5500db426/mult_gen_au8_bu9_p8.dcp
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c64_pro.cache/ip/2023.1/9/d/9d0181c5500db426/mult_gen_au8_bu9_p8_sim_netlist.v
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c64_pro.cache/ip/2023.1/9/d/9d0181c5500db426/mult_gen_au8_bu9_p8_sim_netlist.vhdl
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c64_pro.cache/ip/2023.1/9/d/9d0181c5500db426/mult_gen_au8_bu9_p8_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Oct 28 21:01:02 2025
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_gen_au8_bu9_p8_stub.v
// Design : mult_gen_au8_bu9_p8
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_18,Vivado 2023.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, A, B, CE, P)
/* synthesis syn_black_box black_box_pad_pin="A[7:0],B[8:0],CE,P[7:0]" */
/* synthesis syn_force_seq_prim="CLK" */;
input CLK /* synthesis syn_isclock = 1 */;
input [7:0]A;
input [8:0]B;
input CE;
output [7:0]P;
endmodule
c64_pro.cache/ip/2023.1/9/d/9d0181c5500db426/mult_gen_au8_bu9_p8_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Tue Oct 28 21:01:02 2025
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_gen_au8_bu9_p8_stub.vhdl
-- Design : mult_gen_au8_bu9_p8
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 8 downto 0 );
CE : in STD_LOGIC;
P : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[7:0],B[8:0],CE,P[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_18,Vivado 2023.1";
begin
end;