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c64_pro.cache/ip/2023.1/0/a/0aadbf6f359b7f74/0aadbf6f359b7f74.xci
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c64_pro.cache/ip/2023.1/0/a/0aadbf6f359b7f74/dds_stim_16ch.dcp
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Oct 28 21:01:13 2025
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_stim_16ch_stub.v
// Design : dds_stim_16ch
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0_22,Vivado 2023.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aclken, aresetn, s_axis_config_tvalid,
s_axis_config_tdata, s_axis_config_tlast, m_axis_data_tvalid, m_axis_data_tdata,
m_axis_phase_tvalid, m_axis_phase_tdata, event_s_config_tlast_missing,
event_s_config_tlast_unexpected)
/* synthesis syn_black_box black_box_pad_pin="aclken,aresetn,s_axis_config_tvalid,s_axis_config_tdata[63:0],s_axis_config_tlast,m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0],event_s_config_tlast_missing,event_s_config_tlast_unexpected" */
/* synthesis syn_force_seq_prim="aclk" */;
input aclk /* synthesis syn_isclock = 1 */;
input aclken;
input aresetn;
input s_axis_config_tvalid;
input [63:0]s_axis_config_tdata;
input s_axis_config_tlast;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
output m_axis_phase_tvalid;
output [31:0]m_axis_phase_tdata;
output event_s_config_tlast_missing;
output event_s_config_tlast_unexpected;
endmodule
c64_pro.cache/ip/2023.1/0/a/0aadbf6f359b7f74/dds_stim_16ch_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Tue Oct 28 21:01:13 2025
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_stim_16ch_stub.vhdl
-- Design : dds_stim_16ch
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aclken,aresetn,s_axis_config_tvalid,s_axis_config_tdata[63:0],s_axis_config_tlast,m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0],event_s_config_tlast_missing,event_s_config_tlast_unexpected";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "dds_compiler_v6_0_22,Vivado 2023.1";
begin
end;