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# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
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||||
create_clock -period 10 -name CLK [get_ports CLK]
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|
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@@ -0,0 +1,714 @@
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||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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// Date : Wed Jun 24 13:53:34 2026
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// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
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// Command : write_verilog -force -mode funcsim
|
||||
// d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32_sim_netlist.v
|
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// Design : c_add_s16_s32
|
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// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
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// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
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// Device : xc7z020clg400-2
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// --------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
|
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|
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(* CHECK_LICENSE_TYPE = "c_add_s16_s32,c_addsub_v12_0_15,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "c_addsub_v12_0_15,Vivado 2023.1" *)
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(* NotValidForBitStream *)
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module c_add_s16_s32
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(A,
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B,
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CLK,
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CE,
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SCLR,
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S);
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(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef" *) input [15:0]A;
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(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef" *) input [31:0]B;
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(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF s_intf:c_out_intf:sinit_intf:sset_intf:bypass_intf:c_in_intf:add_intf:b_intf:a_intf, ASSOCIATED_RESET SCLR, ASSOCIATED_CLKEN CE, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input CLK;
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(* x_interface_info = "xilinx.com:signal:clockenable:1.0 ce_intf CE" *) (* x_interface_parameter = "XIL_INTERFACENAME ce_intf, POLARITY ACTIVE_HIGH" *) input CE;
|
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(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) (* x_interface_parameter = "XIL_INTERFACENAME sclr_intf, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input SCLR;
|
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(* x_interface_info = "xilinx.com:signal:data:1.0 s_intf DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME s_intf, LAYERED_METADATA undef" *) output [31:0]S;
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|
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wire [15:0]A;
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wire [31:0]B;
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wire CE;
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wire CLK;
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wire [31:0]S;
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wire SCLR;
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wire NLW_U0_C_OUT_UNCONNECTED;
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|
||||
(* C_AINIT_VAL = "0" *)
|
||||
(* C_BORROW_LOW = "1" *)
|
||||
(* C_CE_OVERRIDES_BYPASS = "1" *)
|
||||
(* C_CE_OVERRIDES_SCLR = "0" *)
|
||||
(* C_HAS_CE = "1" *)
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(* C_HAS_SCLR = "1" *)
|
||||
(* C_HAS_SINIT = "0" *)
|
||||
(* C_HAS_SSET = "0" *)
|
||||
(* C_IMPLEMENTATION = "0" *)
|
||||
(* C_SCLR_OVERRIDES_SSET = "1" *)
|
||||
(* C_SINIT_VAL = "0" *)
|
||||
(* C_VERBOSITY = "0" *)
|
||||
(* C_XDEVICEFAMILY = "zynq" *)
|
||||
(* c_a_type = "0" *)
|
||||
(* c_a_width = "16" *)
|
||||
(* c_add_mode = "0" *)
|
||||
(* c_b_constant = "0" *)
|
||||
(* c_b_type = "0" *)
|
||||
(* c_b_value = "00000000000000000000000000000000" *)
|
||||
(* c_b_width = "32" *)
|
||||
(* c_bypass_low = "0" *)
|
||||
(* c_has_bypass = "0" *)
|
||||
(* c_has_c_in = "0" *)
|
||||
(* c_has_c_out = "0" *)
|
||||
(* c_latency = "1" *)
|
||||
(* c_out_width = "32" *)
|
||||
(* downgradeipidentifiedwarnings = "yes" *)
|
||||
(* is_du_within_envelope = "true" *)
|
||||
c_add_s16_s32_c_addsub_v12_0_15 U0
|
||||
(.A(A),
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.ADD(1'b1),
|
||||
.B(B),
|
||||
.BYPASS(1'b0),
|
||||
.CE(CE),
|
||||
.CLK(CLK),
|
||||
.C_IN(1'b0),
|
||||
.C_OUT(NLW_U0_C_OUT_UNCONNECTED),
|
||||
.S(S),
|
||||
.SCLR(SCLR),
|
||||
.SINIT(1'b0),
|
||||
.SSET(1'b0));
|
||||
endmodule
|
||||
`pragma protect begin_protected
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||||
`pragma protect version = 1
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`pragma protect encrypt_agent = "XILINX"
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`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
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SX+V9Q==
|
||||
`pragma protect end_protected
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
@@ -0,0 +1,960 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jun 24 13:53:35 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32_sim_netlist.vhdl
|
||||
-- Design : c_add_s16_s32
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
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||||
`protect begin_protected
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`protect key_block
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`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
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|
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|
||||
`protect key_block
|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
|
||||
`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
|
||||
`protect encoding = (enctype="BASE64", line_length=76, bytes=384)
|
||||
`protect key_block
|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
|
||||
`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
|
||||
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
|
||||
`protect key_block
|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
|
||||
`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
|
||||
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
|
||||
`protect key_block
|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
|
||||
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
|
||||
`protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`protect data_method = "AES128-CBC"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 41648)
|
||||
`protect data_block
|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
z/xDP9k/alUut0XlJMt8OE0vdJyprZSvBdDckC4d4IsHETrrR0U=
|
||||
`protect end_protected
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity c_add_s16_s32 is
|
||||
port (
|
||||
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
B : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
CLK : in STD_LOGIC;
|
||||
CE : in STD_LOGIC;
|
||||
SCLR : in STD_LOGIC;
|
||||
S : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of c_add_s16_s32 : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of c_add_s16_s32 : entity is "c_add_s16_s32,c_addsub_v12_0_15,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of c_add_s16_s32 : entity is "yes";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of c_add_s16_s32 : entity is "c_addsub_v12_0_15,Vivado 2023.1";
|
||||
end c_add_s16_s32;
|
||||
|
||||
architecture STRUCTURE of c_add_s16_s32 is
|
||||
signal NLW_U0_C_OUT_UNCONNECTED : STD_LOGIC;
|
||||
attribute C_AINIT_VAL : string;
|
||||
attribute C_AINIT_VAL of U0 : label is "0";
|
||||
attribute C_BORROW_LOW : integer;
|
||||
attribute C_BORROW_LOW of U0 : label is 1;
|
||||
attribute C_CE_OVERRIDES_BYPASS : integer;
|
||||
attribute C_CE_OVERRIDES_BYPASS of U0 : label is 1;
|
||||
attribute C_CE_OVERRIDES_SCLR : integer;
|
||||
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
|
||||
attribute C_HAS_CE : integer;
|
||||
attribute C_HAS_CE of U0 : label is 1;
|
||||
attribute C_HAS_SCLR : integer;
|
||||
attribute C_HAS_SCLR of U0 : label is 1;
|
||||
attribute C_HAS_SINIT : integer;
|
||||
attribute C_HAS_SINIT of U0 : label is 0;
|
||||
attribute C_HAS_SSET : integer;
|
||||
attribute C_HAS_SSET of U0 : label is 0;
|
||||
attribute C_IMPLEMENTATION : integer;
|
||||
attribute C_IMPLEMENTATION of U0 : label is 0;
|
||||
attribute C_SCLR_OVERRIDES_SSET : integer;
|
||||
attribute C_SCLR_OVERRIDES_SSET of U0 : label is 1;
|
||||
attribute C_SINIT_VAL : string;
|
||||
attribute C_SINIT_VAL of U0 : label is "0";
|
||||
attribute C_VERBOSITY : integer;
|
||||
attribute C_VERBOSITY of U0 : label is 0;
|
||||
attribute C_XDEVICEFAMILY : string;
|
||||
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
|
||||
attribute c_a_type : integer;
|
||||
attribute c_a_type of U0 : label is 0;
|
||||
attribute c_a_width : integer;
|
||||
attribute c_a_width of U0 : label is 16;
|
||||
attribute c_add_mode : integer;
|
||||
attribute c_add_mode of U0 : label is 0;
|
||||
attribute c_b_constant : integer;
|
||||
attribute c_b_constant of U0 : label is 0;
|
||||
attribute c_b_type : integer;
|
||||
attribute c_b_type of U0 : label is 0;
|
||||
attribute c_b_value : string;
|
||||
attribute c_b_value of U0 : label is "00000000000000000000000000000000";
|
||||
attribute c_b_width : integer;
|
||||
attribute c_b_width of U0 : label is 32;
|
||||
attribute c_bypass_low : integer;
|
||||
attribute c_bypass_low of U0 : label is 0;
|
||||
attribute c_has_bypass : integer;
|
||||
attribute c_has_bypass of U0 : label is 0;
|
||||
attribute c_has_c_in : integer;
|
||||
attribute c_has_c_in of U0 : label is 0;
|
||||
attribute c_has_c_out : integer;
|
||||
attribute c_has_c_out of U0 : label is 0;
|
||||
attribute c_latency : integer;
|
||||
attribute c_latency of U0 : label is 1;
|
||||
attribute c_out_width : integer;
|
||||
attribute c_out_width of U0 : label is 32;
|
||||
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
|
||||
attribute is_du_within_envelope : string;
|
||||
attribute is_du_within_envelope of U0 : label is "true";
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of CE : signal is "xilinx.com:signal:clockenable:1.0 ce_intf CE";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of CE : signal is "XIL_INTERFACENAME ce_intf, POLARITY ACTIVE_HIGH";
|
||||
attribute x_interface_info of CLK : signal is "xilinx.com:signal:clock:1.0 clk_intf CLK";
|
||||
attribute x_interface_parameter of CLK : signal is "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF s_intf:c_out_intf:sinit_intf:sset_intf:bypass_intf:c_in_intf:add_intf:b_intf:a_intf, ASSOCIATED_RESET SCLR, ASSOCIATED_CLKEN CE, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
attribute x_interface_info of SCLR : signal is "xilinx.com:signal:reset:1.0 sclr_intf RST";
|
||||
attribute x_interface_parameter of SCLR : signal is "XIL_INTERFACENAME sclr_intf, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
attribute x_interface_info of A : signal is "xilinx.com:signal:data:1.0 a_intf DATA";
|
||||
attribute x_interface_parameter of A : signal is "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef";
|
||||
attribute x_interface_info of B : signal is "xilinx.com:signal:data:1.0 b_intf DATA";
|
||||
attribute x_interface_parameter of B : signal is "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef";
|
||||
attribute x_interface_info of S : signal is "xilinx.com:signal:data:1.0 s_intf DATA";
|
||||
attribute x_interface_parameter of S : signal is "XIL_INTERFACENAME s_intf, LAYERED_METADATA undef";
|
||||
begin
|
||||
U0: entity work.c_add_s16_s32_c_addsub_v12_0_15
|
||||
port map (
|
||||
A(15 downto 0) => A(15 downto 0),
|
||||
ADD => '1',
|
||||
B(31 downto 0) => B(31 downto 0),
|
||||
BYPASS => '0',
|
||||
CE => CE,
|
||||
CLK => CLK,
|
||||
C_IN => '0',
|
||||
C_OUT => NLW_U0_C_OUT_UNCONNECTED,
|
||||
S(31 downto 0) => S(31 downto 0),
|
||||
SCLR => SCLR,
|
||||
SINIT => '0',
|
||||
SSET => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,27 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jun 24 13:53:34 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32_stub.v
|
||||
// Design : c_add_s16_s32
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "c_addsub_v12_0_15,Vivado 2023.1" *)
|
||||
module c_add_s16_s32(A, B, CLK, CE, SCLR, S)
|
||||
/* synthesis syn_black_box black_box_pad_pin="A[15:0],B[31:0],CE,SCLR,S[31:0]" */
|
||||
/* synthesis syn_force_seq_prim="CLK" */;
|
||||
input [15:0]A;
|
||||
input [31:0]B;
|
||||
input CLK /* synthesis syn_isclock = 1 */;
|
||||
input CE;
|
||||
input SCLR;
|
||||
output [31:0]S;
|
||||
endmodule
|
||||
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jun 24 13:53:34 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32_stub.vhdl
|
||||
-- Design : c_add_s16_s32
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity c_add_s16_s32 is
|
||||
Port (
|
||||
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
B : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
CLK : in STD_LOGIC;
|
||||
CE : in STD_LOGIC;
|
||||
SCLR : in STD_LOGIC;
|
||||
S : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end c_add_s16_s32;
|
||||
|
||||
architecture stub of c_add_s16_s32 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "A[15:0],B[31:0],CLK,CE,SCLR,S[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "c_addsub_v12_0_15,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,556 @@
|
||||
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||||
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`protect key_block
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||||
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|
||||
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||||
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|
||||
|
||||
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
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||||
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|
||||
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|
||||
|
||||
`protect data_method = "AES128-CBC"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26688)
|
||||
`protect data_block
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
pVymNs54aqFxMlYA
|
||||
`protect end_protected
|
||||
@@ -0,0 +1,492 @@
|
||||
`protect begin_protected
|
||||
`protect version = 1
|
||||
`protect encrypt_agent = "XILINX"
|
||||
`protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
|
||||
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`protect key_block
|
||||
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||||
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|
||||
uX24UhjI+kMuKQRzx3g=
|
||||
|
||||
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
iL5Gqr04bWc1L3is9+Fjy23oDboW3J0I8h91Ww==
|
||||
|
||||
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`protect key_block
|
||||
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|
||||
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||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,441 @@
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
|
||||
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|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`protect key_block
|
||||
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||||
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|
||||
|
||||
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|
||||
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|
||||
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||||
`protect end_protected
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,181 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:c_addsub:12.0
|
||||
-- IP Revision: 15
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY c_addsub_v12_0_15;
|
||||
USE c_addsub_v12_0_15.c_addsub_v12_0_15;
|
||||
|
||||
ENTITY c_add_s16_s32 IS
|
||||
PORT (
|
||||
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
CLK : IN STD_LOGIC;
|
||||
CE : IN STD_LOGIC;
|
||||
SCLR : IN STD_LOGIC;
|
||||
S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END c_add_s16_s32;
|
||||
|
||||
ARCHITECTURE c_add_s16_s32_arch OF c_add_s16_s32 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF c_add_s16_s32_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT c_addsub_v12_0_15 IS
|
||||
GENERIC (
|
||||
C_VERBOSITY : INTEGER;
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_IMPLEMENTATION : INTEGER;
|
||||
C_A_WIDTH : INTEGER;
|
||||
C_B_WIDTH : INTEGER;
|
||||
C_OUT_WIDTH : INTEGER;
|
||||
C_CE_OVERRIDES_SCLR : INTEGER;
|
||||
C_A_TYPE : INTEGER;
|
||||
C_B_TYPE : INTEGER;
|
||||
C_LATENCY : INTEGER;
|
||||
C_ADD_MODE : INTEGER;
|
||||
C_B_CONSTANT : INTEGER;
|
||||
C_B_VALUE : STRING;
|
||||
C_AINIT_VAL : STRING;
|
||||
C_SINIT_VAL : STRING;
|
||||
C_CE_OVERRIDES_BYPASS : INTEGER;
|
||||
C_BYPASS_LOW : INTEGER;
|
||||
C_SCLR_OVERRIDES_SSET : INTEGER;
|
||||
C_HAS_C_IN : INTEGER;
|
||||
C_HAS_C_OUT : INTEGER;
|
||||
C_BORROW_LOW : INTEGER;
|
||||
C_HAS_CE : INTEGER;
|
||||
C_HAS_BYPASS : INTEGER;
|
||||
C_HAS_SCLR : INTEGER;
|
||||
C_HAS_SSET : INTEGER;
|
||||
C_HAS_SINIT : INTEGER
|
||||
);
|
||||
PORT (
|
||||
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
CLK : IN STD_LOGIC;
|
||||
ADD : IN STD_LOGIC;
|
||||
C_IN : IN STD_LOGIC;
|
||||
CE : IN STD_LOGIC;
|
||||
BYPASS : IN STD_LOGIC;
|
||||
SCLR : IN STD_LOGIC;
|
||||
SSET : IN STD_LOGIC;
|
||||
SINIT : IN STD_LOGIC;
|
||||
C_OUT : OUT STD_LOGIC;
|
||||
S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT c_addsub_v12_0_15;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF c_add_s16_s32_arch: ARCHITECTURE IS "c_addsub_v12_0_15,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF c_add_s16_s32_arch : ARCHITECTURE IS "c_add_s16_s32,c_addsub_v12_0_15,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF c_add_s16_s32_arch: ARCHITECTURE IS "c_add_s16_s32,c_addsub_v12_0_15,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=c_addsub,x_ipVersion=12.0,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_XDEVICEFAMILY=zynq,C_IMPLEMENTATION=0,C_A_WIDTH=16,C_B_WIDTH=32,C_OUT_WIDTH=32,C_CE_OVERRIDES_SCLR=0,C_A_TYPE=0,C_B_TYPE=0,C_LATENCY=1,C_ADD_MODE=0,C_B_CONSTANT=0,C_B_VALUE=00000000000000000000000000000000,C_AINIT_VAL=0,C_SINIT_VAL=0,C_CE_OVERRIDES_BYPASS=1,C_BYPASS_LOW=0,C_SCLR_OVERRIDES_" &
|
||||
"SSET=1,C_HAS_C_IN=0,C_HAS_C_OUT=0,C_BORROW_LOW=1,C_HAS_CE=1,C_HAS_BYPASS=0,C_HAS_SCLR=1,C_HAS_SSET=0,C_HAS_SINIT=0}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF A: SIGNAL IS "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF B: SIGNAL IS "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CE: SIGNAL IS "XIL_INTERFACENAME ce_intf, POLARITY ACTIVE_HIGH";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CE: SIGNAL IS "xilinx.com:signal:clockenable:1.0 ce_intf CE";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF s_intf:c_out_intf:sinit_intf:sset_intf:bypass_intf:c_in_intf:add_intf:b_intf:a_intf, ASSOCIATED_RESET SCLR, ASSOCIATED_CLKEN CE, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S: SIGNAL IS "XIL_INTERFACENAME s_intf, LAYERED_METADATA undef";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S: SIGNAL IS "xilinx.com:signal:data:1.0 s_intf DATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF SCLR: SIGNAL IS "XIL_INTERFACENAME sclr_intf, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SCLR: SIGNAL IS "xilinx.com:signal:reset:1.0 sclr_intf RST";
|
||||
BEGIN
|
||||
U0 : c_addsub_v12_0_15
|
||||
GENERIC MAP (
|
||||
C_VERBOSITY => 0,
|
||||
C_XDEVICEFAMILY => "zynq",
|
||||
C_IMPLEMENTATION => 0,
|
||||
C_A_WIDTH => 16,
|
||||
C_B_WIDTH => 32,
|
||||
C_OUT_WIDTH => 32,
|
||||
C_CE_OVERRIDES_SCLR => 0,
|
||||
C_A_TYPE => 0,
|
||||
C_B_TYPE => 0,
|
||||
C_LATENCY => 1,
|
||||
C_ADD_MODE => 0,
|
||||
C_B_CONSTANT => 0,
|
||||
C_B_VALUE => "00000000000000000000000000000000",
|
||||
C_AINIT_VAL => "0",
|
||||
C_SINIT_VAL => "0",
|
||||
C_CE_OVERRIDES_BYPASS => 1,
|
||||
C_BYPASS_LOW => 0,
|
||||
C_SCLR_OVERRIDES_SSET => 1,
|
||||
C_HAS_C_IN => 0,
|
||||
C_HAS_C_OUT => 0,
|
||||
C_BORROW_LOW => 1,
|
||||
C_HAS_CE => 1,
|
||||
C_HAS_BYPASS => 0,
|
||||
C_HAS_SCLR => 1,
|
||||
C_HAS_SSET => 0,
|
||||
C_HAS_SINIT => 0
|
||||
)
|
||||
PORT MAP (
|
||||
A => A,
|
||||
B => B,
|
||||
CLK => CLK,
|
||||
ADD => '1',
|
||||
C_IN => '0',
|
||||
CE => CE,
|
||||
BYPASS => '0',
|
||||
SCLR => SCLR,
|
||||
SSET => '0',
|
||||
SINIT => '0',
|
||||
S => S
|
||||
);
|
||||
END c_add_s16_s32_arch;
|
||||
Binary file not shown.
@@ -0,0 +1,64 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
#------------------------------------------------------------------------------#
|
||||
# Native FIFO Constraints #
|
||||
#------------------------------------------------------------------------------#
|
||||
|
||||
|
||||
|
||||
|
||||
################################################################################
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,69 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
#------------------------------------------------------------------------------#
|
||||
# Native FIFO Constraints #
|
||||
#------------------------------------------------------------------------------#
|
||||
|
||||
#set wr_clock [get_clocks -of_objects [get_ports wr_clk]]
|
||||
#set rd_clock [get_clocks -of_objects [get_ports rd_clk]]
|
||||
#set wr_clk_period [get_property PERIOD $wr_clock]
|
||||
#set rd_clk_period [get_property PERIOD $rd_clock]
|
||||
#set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
|
||||
|
||||
|
||||
# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
|
||||
|
||||
## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock]
|
||||
## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] $skew_value
|
||||
|
||||
## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock]
|
||||
## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] $skew_value
|
||||
#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.sckt_wrst_i_reg}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_inst/Q_reg_reg[0]}]
|
||||
#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[3].rd_rst_inst/Q_reg_reg[0]}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_wr_inst/Q_reg_reg[0]}]
|
||||
################################################################################
|
||||
@@ -0,0 +1,59 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 10 -name wr_clk [get_ports wr_clk]
|
||||
|
||||
create_clock -period 10 -name rd_clk [get_ports rd_clk]
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,34 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jun 24 13:53:58 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_stub.v
|
||||
// Design : fifo_generator_1
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fifo_generator_v13_2_8,Vivado 2023.1" *)
|
||||
module fifo_generator_1(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
|
||||
empty, wr_rst_busy, rd_rst_busy)
|
||||
/* synthesis syn_black_box black_box_pad_pin="rst,din[31:0],wr_en,rd_en,dout[31:0],full,empty,wr_rst_busy,rd_rst_busy" */
|
||||
/* synthesis syn_force_seq_prim="wr_clk" */
|
||||
/* synthesis syn_force_seq_prim="rd_clk" */;
|
||||
input rst;
|
||||
input wr_clk /* synthesis syn_isclock = 1 */;
|
||||
input rd_clk /* synthesis syn_isclock = 1 */;
|
||||
input [31:0]din;
|
||||
input wr_en;
|
||||
input rd_en;
|
||||
output [31:0]dout;
|
||||
output full;
|
||||
output empty;
|
||||
output wr_rst_busy;
|
||||
output rd_rst_busy;
|
||||
endmodule
|
||||
@@ -0,0 +1,41 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jun 24 13:53:58 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_stub.vhdl
|
||||
-- Design : fifo_generator_1
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity fifo_generator_1 is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
wr_clk : in STD_LOGIC;
|
||||
rd_clk : in STD_LOGIC;
|
||||
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
wr_en : in STD_LOGIC;
|
||||
rd_en : in STD_LOGIC;
|
||||
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
full : out STD_LOGIC;
|
||||
empty : out STD_LOGIC;
|
||||
wr_rst_busy : out STD_LOGIC;
|
||||
rd_rst_busy : out STD_LOGIC
|
||||
);
|
||||
|
||||
end fifo_generator_1;
|
||||
|
||||
architecture stub of fifo_generator_1 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,wr_rst_busy,rd_rst_busy";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_8,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,862 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
-- IP Revision: 8
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY fifo_generator_v13_2_8;
|
||||
USE fifo_generator_v13_2_8.fifo_generator_v13_2_8;
|
||||
|
||||
ENTITY fifo_generator_1 IS
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC;
|
||||
wr_rst_busy : OUT STD_LOGIC;
|
||||
rd_rst_busy : OUT STD_LOGIC
|
||||
);
|
||||
END fifo_generator_1;
|
||||
|
||||
ARCHITECTURE fifo_generator_1_arch OF fifo_generator_1 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_1_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT fifo_generator_v13_2_8 IS
|
||||
GENERIC (
|
||||
C_COMMON_CLOCK : INTEGER;
|
||||
C_SELECT_XPM : INTEGER;
|
||||
C_COUNT_TYPE : INTEGER;
|
||||
C_DATA_COUNT_WIDTH : INTEGER;
|
||||
C_DEFAULT_VALUE : STRING;
|
||||
C_DIN_WIDTH : INTEGER;
|
||||
C_DOUT_RST_VAL : STRING;
|
||||
C_DOUT_WIDTH : INTEGER;
|
||||
C_ENABLE_RLOCS : INTEGER;
|
||||
C_FAMILY : STRING;
|
||||
C_FULL_FLAGS_RST_VAL : INTEGER;
|
||||
C_HAS_ALMOST_EMPTY : INTEGER;
|
||||
C_HAS_ALMOST_FULL : INTEGER;
|
||||
C_HAS_BACKUP : INTEGER;
|
||||
C_HAS_DATA_COUNT : INTEGER;
|
||||
C_HAS_INT_CLK : INTEGER;
|
||||
C_HAS_MEMINIT_FILE : INTEGER;
|
||||
C_HAS_OVERFLOW : INTEGER;
|
||||
C_HAS_RD_DATA_COUNT : INTEGER;
|
||||
C_HAS_RD_RST : INTEGER;
|
||||
C_HAS_RST : INTEGER;
|
||||
C_HAS_SRST : INTEGER;
|
||||
C_HAS_UNDERFLOW : INTEGER;
|
||||
C_HAS_VALID : INTEGER;
|
||||
C_HAS_WR_ACK : INTEGER;
|
||||
C_HAS_WR_DATA_COUNT : INTEGER;
|
||||
C_HAS_WR_RST : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE : INTEGER;
|
||||
C_INIT_WR_PNTR_VAL : INTEGER;
|
||||
C_MEMORY_TYPE : INTEGER;
|
||||
C_MIF_FILE_NAME : STRING;
|
||||
C_OPTIMIZATION_MODE : INTEGER;
|
||||
C_OVERFLOW_LOW : INTEGER;
|
||||
C_PRELOAD_LATENCY : INTEGER;
|
||||
C_PRELOAD_REGS : INTEGER;
|
||||
C_PRIM_FIFO_TYPE : STRING;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
|
||||
C_PROG_EMPTY_TYPE : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
|
||||
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
|
||||
C_PROG_FULL_TYPE : INTEGER;
|
||||
C_RD_DATA_COUNT_WIDTH : INTEGER;
|
||||
C_RD_DEPTH : INTEGER;
|
||||
C_RD_FREQ : INTEGER;
|
||||
C_RD_PNTR_WIDTH : INTEGER;
|
||||
C_UNDERFLOW_LOW : INTEGER;
|
||||
C_USE_DOUT_RST : INTEGER;
|
||||
C_USE_ECC : INTEGER;
|
||||
C_USE_EMBEDDED_REG : INTEGER;
|
||||
C_USE_PIPELINE_REG : INTEGER;
|
||||
C_POWER_SAVING_MODE : INTEGER;
|
||||
C_USE_FIFO16_FLAGS : INTEGER;
|
||||
C_USE_FWFT_DATA_COUNT : INTEGER;
|
||||
C_VALID_LOW : INTEGER;
|
||||
C_WR_ACK_LOW : INTEGER;
|
||||
C_WR_DATA_COUNT_WIDTH : INTEGER;
|
||||
C_WR_DEPTH : INTEGER;
|
||||
C_WR_FREQ : INTEGER;
|
||||
C_WR_PNTR_WIDTH : INTEGER;
|
||||
C_WR_RESPONSE_LATENCY : INTEGER;
|
||||
C_MSGON_VAL : INTEGER;
|
||||
C_ENABLE_RST_SYNC : INTEGER;
|
||||
C_EN_SAFETY_CKT : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE : INTEGER;
|
||||
C_SYNCHRONIZER_STAGE : INTEGER;
|
||||
C_INTERFACE_TYPE : INTEGER;
|
||||
C_AXI_TYPE : INTEGER;
|
||||
C_HAS_AXI_WR_CHANNEL : INTEGER;
|
||||
C_HAS_AXI_RD_CHANNEL : INTEGER;
|
||||
C_HAS_SLAVE_CE : INTEGER;
|
||||
C_HAS_MASTER_CE : INTEGER;
|
||||
C_ADD_NGC_CONSTRAINT : INTEGER;
|
||||
C_USE_COMMON_OVERFLOW : INTEGER;
|
||||
C_USE_COMMON_UNDERFLOW : INTEGER;
|
||||
C_USE_DEFAULT_SETTINGS : INTEGER;
|
||||
C_AXI_ID_WIDTH : INTEGER;
|
||||
C_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_AXI_DATA_WIDTH : INTEGER;
|
||||
C_AXI_LEN_WIDTH : INTEGER;
|
||||
C_AXI_LOCK_WIDTH : INTEGER;
|
||||
C_HAS_AXI_ID : INTEGER;
|
||||
C_HAS_AXI_AWUSER : INTEGER;
|
||||
C_HAS_AXI_WUSER : INTEGER;
|
||||
C_HAS_AXI_BUSER : INTEGER;
|
||||
C_HAS_AXI_ARUSER : INTEGER;
|
||||
C_HAS_AXI_RUSER : INTEGER;
|
||||
C_AXI_ARUSER_WIDTH : INTEGER;
|
||||
C_AXI_AWUSER_WIDTH : INTEGER;
|
||||
C_AXI_WUSER_WIDTH : INTEGER;
|
||||
C_AXI_BUSER_WIDTH : INTEGER;
|
||||
C_AXI_RUSER_WIDTH : INTEGER;
|
||||
C_HAS_AXIS_TDATA : INTEGER;
|
||||
C_HAS_AXIS_TID : INTEGER;
|
||||
C_HAS_AXIS_TDEST : INTEGER;
|
||||
C_HAS_AXIS_TUSER : INTEGER;
|
||||
C_HAS_AXIS_TREADY : INTEGER;
|
||||
C_HAS_AXIS_TLAST : INTEGER;
|
||||
C_HAS_AXIS_TSTRB : INTEGER;
|
||||
C_HAS_AXIS_TKEEP : INTEGER;
|
||||
C_AXIS_TDATA_WIDTH : INTEGER;
|
||||
C_AXIS_TID_WIDTH : INTEGER;
|
||||
C_AXIS_TDEST_WIDTH : INTEGER;
|
||||
C_AXIS_TUSER_WIDTH : INTEGER;
|
||||
C_AXIS_TSTRB_WIDTH : INTEGER;
|
||||
C_AXIS_TKEEP_WIDTH : INTEGER;
|
||||
C_WACH_TYPE : INTEGER;
|
||||
C_WDCH_TYPE : INTEGER;
|
||||
C_WRCH_TYPE : INTEGER;
|
||||
C_RACH_TYPE : INTEGER;
|
||||
C_RDCH_TYPE : INTEGER;
|
||||
C_AXIS_TYPE : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
|
||||
C_APPLICATION_TYPE_WACH : INTEGER;
|
||||
C_APPLICATION_TYPE_WDCH : INTEGER;
|
||||
C_APPLICATION_TYPE_WRCH : INTEGER;
|
||||
C_APPLICATION_TYPE_RACH : INTEGER;
|
||||
C_APPLICATION_TYPE_RDCH : INTEGER;
|
||||
C_APPLICATION_TYPE_AXIS : INTEGER;
|
||||
C_PRIM_FIFO_TYPE_WACH : STRING;
|
||||
C_PRIM_FIFO_TYPE_WDCH : STRING;
|
||||
C_PRIM_FIFO_TYPE_WRCH : STRING;
|
||||
C_PRIM_FIFO_TYPE_RACH : STRING;
|
||||
C_PRIM_FIFO_TYPE_RDCH : STRING;
|
||||
C_PRIM_FIFO_TYPE_AXIS : STRING;
|
||||
C_USE_ECC_WACH : INTEGER;
|
||||
C_USE_ECC_WDCH : INTEGER;
|
||||
C_USE_ECC_WRCH : INTEGER;
|
||||
C_USE_ECC_RACH : INTEGER;
|
||||
C_USE_ECC_RDCH : INTEGER;
|
||||
C_USE_ECC_AXIS : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
|
||||
C_DIN_WIDTH_WACH : INTEGER;
|
||||
C_DIN_WIDTH_WDCH : INTEGER;
|
||||
C_DIN_WIDTH_WRCH : INTEGER;
|
||||
C_DIN_WIDTH_RACH : INTEGER;
|
||||
C_DIN_WIDTH_RDCH : INTEGER;
|
||||
C_DIN_WIDTH_AXIS : INTEGER;
|
||||
C_WR_DEPTH_WACH : INTEGER;
|
||||
C_WR_DEPTH_WDCH : INTEGER;
|
||||
C_WR_DEPTH_WRCH : INTEGER;
|
||||
C_WR_DEPTH_RACH : INTEGER;
|
||||
C_WR_DEPTH_RDCH : INTEGER;
|
||||
C_WR_DEPTH_AXIS : INTEGER;
|
||||
C_WR_PNTR_WIDTH_WACH : INTEGER;
|
||||
C_WR_PNTR_WIDTH_WDCH : INTEGER;
|
||||
C_WR_PNTR_WIDTH_WRCH : INTEGER;
|
||||
C_WR_PNTR_WIDTH_RACH : INTEGER;
|
||||
C_WR_PNTR_WIDTH_RDCH : INTEGER;
|
||||
C_WR_PNTR_WIDTH_AXIS : INTEGER;
|
||||
C_HAS_DATA_COUNTS_WACH : INTEGER;
|
||||
C_HAS_DATA_COUNTS_WDCH : INTEGER;
|
||||
C_HAS_DATA_COUNTS_WRCH : INTEGER;
|
||||
C_HAS_DATA_COUNTS_RACH : INTEGER;
|
||||
C_HAS_DATA_COUNTS_RDCH : INTEGER;
|
||||
C_HAS_DATA_COUNTS_AXIS : INTEGER;
|
||||
C_HAS_PROG_FLAGS_WACH : INTEGER;
|
||||
C_HAS_PROG_FLAGS_WDCH : INTEGER;
|
||||
C_HAS_PROG_FLAGS_WRCH : INTEGER;
|
||||
C_HAS_PROG_FLAGS_RACH : INTEGER;
|
||||
C_HAS_PROG_FLAGS_RDCH : INTEGER;
|
||||
C_HAS_PROG_FLAGS_AXIS : INTEGER;
|
||||
C_PROG_FULL_TYPE_WACH : INTEGER;
|
||||
C_PROG_FULL_TYPE_WDCH : INTEGER;
|
||||
C_PROG_FULL_TYPE_WRCH : INTEGER;
|
||||
C_PROG_FULL_TYPE_RACH : INTEGER;
|
||||
C_PROG_FULL_TYPE_RDCH : INTEGER;
|
||||
C_PROG_FULL_TYPE_AXIS : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
|
||||
C_PROG_EMPTY_TYPE_WACH : INTEGER;
|
||||
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
|
||||
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
|
||||
C_PROG_EMPTY_TYPE_RACH : INTEGER;
|
||||
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
|
||||
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
|
||||
C_REG_SLICE_MODE_WACH : INTEGER;
|
||||
C_REG_SLICE_MODE_WDCH : INTEGER;
|
||||
C_REG_SLICE_MODE_WRCH : INTEGER;
|
||||
C_REG_SLICE_MODE_RACH : INTEGER;
|
||||
C_REG_SLICE_MODE_RDCH : INTEGER;
|
||||
C_REG_SLICE_MODE_AXIS : INTEGER
|
||||
);
|
||||
PORT (
|
||||
backup : IN STD_LOGIC;
|
||||
backup_marker : IN STD_LOGIC;
|
||||
clk : IN STD_LOGIC;
|
||||
rst : IN STD_LOGIC;
|
||||
srst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
wr_rst : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
rd_rst : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
int_clk : IN STD_LOGIC;
|
||||
injectdbiterr : IN STD_LOGIC;
|
||||
injectsbiterr : IN STD_LOGIC;
|
||||
sleep : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
almost_full : OUT STD_LOGIC;
|
||||
wr_ack : OUT STD_LOGIC;
|
||||
overflow : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC;
|
||||
almost_empty : OUT STD_LOGIC;
|
||||
valid : OUT STD_LOGIC;
|
||||
underflow : OUT STD_LOGIC;
|
||||
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
prog_full : OUT STD_LOGIC;
|
||||
prog_empty : OUT STD_LOGIC;
|
||||
sbiterr : OUT STD_LOGIC;
|
||||
dbiterr : OUT STD_LOGIC;
|
||||
wr_rst_busy : OUT STD_LOGIC;
|
||||
rd_rst_busy : OUT STD_LOGIC;
|
||||
m_aclk : IN STD_LOGIC;
|
||||
s_aclk : IN STD_LOGIC;
|
||||
s_aresetn : IN STD_LOGIC;
|
||||
m_aclk_en : IN STD_LOGIC;
|
||||
s_aclk_en : IN STD_LOGIC;
|
||||
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_awvalid : OUT STD_LOGIC;
|
||||
m_axi_awready : IN STD_LOGIC;
|
||||
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_wlast : OUT STD_LOGIC;
|
||||
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_wvalid : OUT STD_LOGIC;
|
||||
m_axi_wready : IN STD_LOGIC;
|
||||
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_bvalid : IN STD_LOGIC;
|
||||
m_axi_bready : OUT STD_LOGIC;
|
||||
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_arvalid : OUT STD_LOGIC;
|
||||
m_axi_arready : IN STD_LOGIC;
|
||||
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_rlast : IN STD_LOGIC;
|
||||
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_rvalid : IN STD_LOGIC;
|
||||
m_axi_rready : OUT STD_LOGIC;
|
||||
s_axis_tvalid : IN STD_LOGIC;
|
||||
s_axis_tready : OUT STD_LOGIC;
|
||||
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_tlast : IN STD_LOGIC;
|
||||
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_tvalid : OUT STD_LOGIC;
|
||||
m_axis_tready : IN STD_LOGIC;
|
||||
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_tlast : OUT STD_LOGIC;
|
||||
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_aw_injectsbiterr : IN STD_LOGIC;
|
||||
axi_aw_injectdbiterr : IN STD_LOGIC;
|
||||
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_aw_sbiterr : OUT STD_LOGIC;
|
||||
axi_aw_dbiterr : OUT STD_LOGIC;
|
||||
axi_aw_overflow : OUT STD_LOGIC;
|
||||
axi_aw_underflow : OUT STD_LOGIC;
|
||||
axi_aw_prog_full : OUT STD_LOGIC;
|
||||
axi_aw_prog_empty : OUT STD_LOGIC;
|
||||
axi_w_injectsbiterr : IN STD_LOGIC;
|
||||
axi_w_injectdbiterr : IN STD_LOGIC;
|
||||
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axi_w_sbiterr : OUT STD_LOGIC;
|
||||
axi_w_dbiterr : OUT STD_LOGIC;
|
||||
axi_w_overflow : OUT STD_LOGIC;
|
||||
axi_w_underflow : OUT STD_LOGIC;
|
||||
axi_w_prog_full : OUT STD_LOGIC;
|
||||
axi_w_prog_empty : OUT STD_LOGIC;
|
||||
axi_b_injectsbiterr : IN STD_LOGIC;
|
||||
axi_b_injectdbiterr : IN STD_LOGIC;
|
||||
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_b_sbiterr : OUT STD_LOGIC;
|
||||
axi_b_dbiterr : OUT STD_LOGIC;
|
||||
axi_b_overflow : OUT STD_LOGIC;
|
||||
axi_b_underflow : OUT STD_LOGIC;
|
||||
axi_b_prog_full : OUT STD_LOGIC;
|
||||
axi_b_prog_empty : OUT STD_LOGIC;
|
||||
axi_ar_injectsbiterr : IN STD_LOGIC;
|
||||
axi_ar_injectdbiterr : IN STD_LOGIC;
|
||||
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_ar_sbiterr : OUT STD_LOGIC;
|
||||
axi_ar_dbiterr : OUT STD_LOGIC;
|
||||
axi_ar_overflow : OUT STD_LOGIC;
|
||||
axi_ar_underflow : OUT STD_LOGIC;
|
||||
axi_ar_prog_full : OUT STD_LOGIC;
|
||||
axi_ar_prog_empty : OUT STD_LOGIC;
|
||||
axi_r_injectsbiterr : IN STD_LOGIC;
|
||||
axi_r_injectdbiterr : IN STD_LOGIC;
|
||||
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axi_r_sbiterr : OUT STD_LOGIC;
|
||||
axi_r_dbiterr : OUT STD_LOGIC;
|
||||
axi_r_overflow : OUT STD_LOGIC;
|
||||
axi_r_underflow : OUT STD_LOGIC;
|
||||
axi_r_prog_full : OUT STD_LOGIC;
|
||||
axi_r_prog_empty : OUT STD_LOGIC;
|
||||
axis_injectsbiterr : IN STD_LOGIC;
|
||||
axis_injectdbiterr : IN STD_LOGIC;
|
||||
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axis_sbiterr : OUT STD_LOGIC;
|
||||
axis_dbiterr : OUT STD_LOGIC;
|
||||
axis_overflow : OUT STD_LOGIC;
|
||||
axis_underflow : OUT STD_LOGIC;
|
||||
axis_prog_full : OUT STD_LOGIC;
|
||||
axis_prog_empty : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT fifo_generator_v13_2_8;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF fifo_generator_1_arch: ARCHITECTURE IS "fifo_generator_v13_2_8,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_1_arch : ARCHITECTURE IS "fifo_generator_1,fifo_generator_v13_2_8,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_1_arch: ARCHITECTURE IS "fifo_generator_1,fifo_generator_v13_2_8,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.2,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_H" &
|
||||
"AS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FUL" &
|
||||
"L_THRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_I" &
|
||||
"NTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSE" &
|
||||
"R_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATIO" &
|
||||
"N_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=" &
|
||||
"0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RD" &
|
||||
"CH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WA" &
|
||||
"CH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH" &
|
||||
"_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF rd_clk: SIGNAL IS "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF wr_clk: SIGNAL IS "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
|
||||
BEGIN
|
||||
U0 : fifo_generator_v13_2_8
|
||||
GENERIC MAP (
|
||||
C_COMMON_CLOCK => 0,
|
||||
C_SELECT_XPM => 0,
|
||||
C_COUNT_TYPE => 0,
|
||||
C_DATA_COUNT_WIDTH => 10,
|
||||
C_DEFAULT_VALUE => "BlankString",
|
||||
C_DIN_WIDTH => 32,
|
||||
C_DOUT_RST_VAL => "0",
|
||||
C_DOUT_WIDTH => 32,
|
||||
C_ENABLE_RLOCS => 0,
|
||||
C_FAMILY => "zynq",
|
||||
C_FULL_FLAGS_RST_VAL => 1,
|
||||
C_HAS_ALMOST_EMPTY => 0,
|
||||
C_HAS_ALMOST_FULL => 0,
|
||||
C_HAS_BACKUP => 0,
|
||||
C_HAS_DATA_COUNT => 0,
|
||||
C_HAS_INT_CLK => 0,
|
||||
C_HAS_MEMINIT_FILE => 0,
|
||||
C_HAS_OVERFLOW => 0,
|
||||
C_HAS_RD_DATA_COUNT => 0,
|
||||
C_HAS_RD_RST => 0,
|
||||
C_HAS_RST => 1,
|
||||
C_HAS_SRST => 0,
|
||||
C_HAS_UNDERFLOW => 0,
|
||||
C_HAS_VALID => 0,
|
||||
C_HAS_WR_ACK => 0,
|
||||
C_HAS_WR_DATA_COUNT => 0,
|
||||
C_HAS_WR_RST => 0,
|
||||
C_IMPLEMENTATION_TYPE => 2,
|
||||
C_INIT_WR_PNTR_VAL => 0,
|
||||
C_MEMORY_TYPE => 1,
|
||||
C_MIF_FILE_NAME => "BlankString",
|
||||
C_OPTIMIZATION_MODE => 0,
|
||||
C_OVERFLOW_LOW => 0,
|
||||
C_PRELOAD_LATENCY => 1,
|
||||
C_PRELOAD_REGS => 0,
|
||||
C_PRIM_FIFO_TYPE => "1kx36",
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
|
||||
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
|
||||
C_PROG_EMPTY_TYPE => 0,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
|
||||
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
|
||||
C_PROG_FULL_TYPE => 0,
|
||||
C_RD_DATA_COUNT_WIDTH => 10,
|
||||
C_RD_DEPTH => 1024,
|
||||
C_RD_FREQ => 1,
|
||||
C_RD_PNTR_WIDTH => 10,
|
||||
C_UNDERFLOW_LOW => 0,
|
||||
C_USE_DOUT_RST => 1,
|
||||
C_USE_ECC => 0,
|
||||
C_USE_EMBEDDED_REG => 0,
|
||||
C_USE_PIPELINE_REG => 0,
|
||||
C_POWER_SAVING_MODE => 0,
|
||||
C_USE_FIFO16_FLAGS => 0,
|
||||
C_USE_FWFT_DATA_COUNT => 0,
|
||||
C_VALID_LOW => 0,
|
||||
C_WR_ACK_LOW => 0,
|
||||
C_WR_DATA_COUNT_WIDTH => 10,
|
||||
C_WR_DEPTH => 1024,
|
||||
C_WR_FREQ => 1,
|
||||
C_WR_PNTR_WIDTH => 10,
|
||||
C_WR_RESPONSE_LATENCY => 1,
|
||||
C_MSGON_VAL => 1,
|
||||
C_ENABLE_RST_SYNC => 1,
|
||||
C_EN_SAFETY_CKT => 1,
|
||||
C_ERROR_INJECTION_TYPE => 0,
|
||||
C_SYNCHRONIZER_STAGE => 2,
|
||||
C_INTERFACE_TYPE => 0,
|
||||
C_AXI_TYPE => 1,
|
||||
C_HAS_AXI_WR_CHANNEL => 1,
|
||||
C_HAS_AXI_RD_CHANNEL => 1,
|
||||
C_HAS_SLAVE_CE => 0,
|
||||
C_HAS_MASTER_CE => 0,
|
||||
C_ADD_NGC_CONSTRAINT => 0,
|
||||
C_USE_COMMON_OVERFLOW => 0,
|
||||
C_USE_COMMON_UNDERFLOW => 0,
|
||||
C_USE_DEFAULT_SETTINGS => 0,
|
||||
C_AXI_ID_WIDTH => 1,
|
||||
C_AXI_ADDR_WIDTH => 32,
|
||||
C_AXI_DATA_WIDTH => 64,
|
||||
C_AXI_LEN_WIDTH => 8,
|
||||
C_AXI_LOCK_WIDTH => 1,
|
||||
C_HAS_AXI_ID => 0,
|
||||
C_HAS_AXI_AWUSER => 0,
|
||||
C_HAS_AXI_WUSER => 0,
|
||||
C_HAS_AXI_BUSER => 0,
|
||||
C_HAS_AXI_ARUSER => 0,
|
||||
C_HAS_AXI_RUSER => 0,
|
||||
C_AXI_ARUSER_WIDTH => 1,
|
||||
C_AXI_AWUSER_WIDTH => 1,
|
||||
C_AXI_WUSER_WIDTH => 1,
|
||||
C_AXI_BUSER_WIDTH => 1,
|
||||
C_AXI_RUSER_WIDTH => 1,
|
||||
C_HAS_AXIS_TDATA => 1,
|
||||
C_HAS_AXIS_TID => 0,
|
||||
C_HAS_AXIS_TDEST => 0,
|
||||
C_HAS_AXIS_TUSER => 1,
|
||||
C_HAS_AXIS_TREADY => 1,
|
||||
C_HAS_AXIS_TLAST => 0,
|
||||
C_HAS_AXIS_TSTRB => 0,
|
||||
C_HAS_AXIS_TKEEP => 0,
|
||||
C_AXIS_TDATA_WIDTH => 8,
|
||||
C_AXIS_TID_WIDTH => 1,
|
||||
C_AXIS_TDEST_WIDTH => 1,
|
||||
C_AXIS_TUSER_WIDTH => 4,
|
||||
C_AXIS_TSTRB_WIDTH => 1,
|
||||
C_AXIS_TKEEP_WIDTH => 1,
|
||||
C_WACH_TYPE => 0,
|
||||
C_WDCH_TYPE => 0,
|
||||
C_WRCH_TYPE => 0,
|
||||
C_RACH_TYPE => 0,
|
||||
C_RDCH_TYPE => 0,
|
||||
C_AXIS_TYPE => 0,
|
||||
C_IMPLEMENTATION_TYPE_WACH => 1,
|
||||
C_IMPLEMENTATION_TYPE_WDCH => 1,
|
||||
C_IMPLEMENTATION_TYPE_WRCH => 1,
|
||||
C_IMPLEMENTATION_TYPE_RACH => 1,
|
||||
C_IMPLEMENTATION_TYPE_RDCH => 1,
|
||||
C_IMPLEMENTATION_TYPE_AXIS => 1,
|
||||
C_APPLICATION_TYPE_WACH => 0,
|
||||
C_APPLICATION_TYPE_WDCH => 0,
|
||||
C_APPLICATION_TYPE_WRCH => 0,
|
||||
C_APPLICATION_TYPE_RACH => 0,
|
||||
C_APPLICATION_TYPE_RDCH => 0,
|
||||
C_APPLICATION_TYPE_AXIS => 0,
|
||||
C_PRIM_FIFO_TYPE_WACH => "512x36",
|
||||
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
|
||||
C_PRIM_FIFO_TYPE_WRCH => "512x36",
|
||||
C_PRIM_FIFO_TYPE_RACH => "512x36",
|
||||
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
|
||||
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
|
||||
C_USE_ECC_WACH => 0,
|
||||
C_USE_ECC_WDCH => 0,
|
||||
C_USE_ECC_WRCH => 0,
|
||||
C_USE_ECC_RACH => 0,
|
||||
C_USE_ECC_RDCH => 0,
|
||||
C_USE_ECC_AXIS => 0,
|
||||
C_ERROR_INJECTION_TYPE_WACH => 0,
|
||||
C_ERROR_INJECTION_TYPE_WDCH => 0,
|
||||
C_ERROR_INJECTION_TYPE_WRCH => 0,
|
||||
C_ERROR_INJECTION_TYPE_RACH => 0,
|
||||
C_ERROR_INJECTION_TYPE_RDCH => 0,
|
||||
C_ERROR_INJECTION_TYPE_AXIS => 0,
|
||||
C_DIN_WIDTH_WACH => 1,
|
||||
C_DIN_WIDTH_WDCH => 64,
|
||||
C_DIN_WIDTH_WRCH => 2,
|
||||
C_DIN_WIDTH_RACH => 32,
|
||||
C_DIN_WIDTH_RDCH => 64,
|
||||
C_DIN_WIDTH_AXIS => 1,
|
||||
C_WR_DEPTH_WACH => 16,
|
||||
C_WR_DEPTH_WDCH => 1024,
|
||||
C_WR_DEPTH_WRCH => 16,
|
||||
C_WR_DEPTH_RACH => 16,
|
||||
C_WR_DEPTH_RDCH => 1024,
|
||||
C_WR_DEPTH_AXIS => 1024,
|
||||
C_WR_PNTR_WIDTH_WACH => 4,
|
||||
C_WR_PNTR_WIDTH_WDCH => 10,
|
||||
C_WR_PNTR_WIDTH_WRCH => 4,
|
||||
C_WR_PNTR_WIDTH_RACH => 4,
|
||||
C_WR_PNTR_WIDTH_RDCH => 10,
|
||||
C_WR_PNTR_WIDTH_AXIS => 10,
|
||||
C_HAS_DATA_COUNTS_WACH => 0,
|
||||
C_HAS_DATA_COUNTS_WDCH => 0,
|
||||
C_HAS_DATA_COUNTS_WRCH => 0,
|
||||
C_HAS_DATA_COUNTS_RACH => 0,
|
||||
C_HAS_DATA_COUNTS_RDCH => 0,
|
||||
C_HAS_DATA_COUNTS_AXIS => 0,
|
||||
C_HAS_PROG_FLAGS_WACH => 0,
|
||||
C_HAS_PROG_FLAGS_WDCH => 0,
|
||||
C_HAS_PROG_FLAGS_WRCH => 0,
|
||||
C_HAS_PROG_FLAGS_RACH => 0,
|
||||
C_HAS_PROG_FLAGS_RDCH => 0,
|
||||
C_HAS_PROG_FLAGS_AXIS => 0,
|
||||
C_PROG_FULL_TYPE_WACH => 0,
|
||||
C_PROG_FULL_TYPE_WDCH => 0,
|
||||
C_PROG_FULL_TYPE_WRCH => 0,
|
||||
C_PROG_FULL_TYPE_RACH => 0,
|
||||
C_PROG_FULL_TYPE_RDCH => 0,
|
||||
C_PROG_FULL_TYPE_AXIS => 0,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
|
||||
C_PROG_EMPTY_TYPE_WACH => 0,
|
||||
C_PROG_EMPTY_TYPE_WDCH => 0,
|
||||
C_PROG_EMPTY_TYPE_WRCH => 0,
|
||||
C_PROG_EMPTY_TYPE_RACH => 0,
|
||||
C_PROG_EMPTY_TYPE_RDCH => 0,
|
||||
C_PROG_EMPTY_TYPE_AXIS => 0,
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
|
||||
C_REG_SLICE_MODE_WACH => 0,
|
||||
C_REG_SLICE_MODE_WDCH => 0,
|
||||
C_REG_SLICE_MODE_WRCH => 0,
|
||||
C_REG_SLICE_MODE_RACH => 0,
|
||||
C_REG_SLICE_MODE_RDCH => 0,
|
||||
C_REG_SLICE_MODE_AXIS => 0
|
||||
)
|
||||
PORT MAP (
|
||||
backup => '0',
|
||||
backup_marker => '0',
|
||||
clk => '0',
|
||||
rst => rst,
|
||||
srst => '0',
|
||||
wr_clk => wr_clk,
|
||||
wr_rst => '0',
|
||||
rd_clk => rd_clk,
|
||||
rd_rst => '0',
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
int_clk => '0',
|
||||
injectdbiterr => '0',
|
||||
injectsbiterr => '0',
|
||||
sleep => '0',
|
||||
dout => dout,
|
||||
full => full,
|
||||
empty => empty,
|
||||
wr_rst_busy => wr_rst_busy,
|
||||
rd_rst_busy => rd_rst_busy,
|
||||
m_aclk => '0',
|
||||
s_aclk => '0',
|
||||
s_aresetn => '0',
|
||||
m_aclk_en => '0',
|
||||
s_aclk_en => '0',
|
||||
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awvalid => '0',
|
||||
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
|
||||
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi_wlast => '0',
|
||||
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_wvalid => '0',
|
||||
s_axi_bready => '0',
|
||||
m_axi_awready => '0',
|
||||
m_axi_wready => '0',
|
||||
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axi_bvalid => '0',
|
||||
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_arvalid => '0',
|
||||
s_axi_rready => '0',
|
||||
m_axi_arready => '0',
|
||||
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
|
||||
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_rlast => '0',
|
||||
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axi_rvalid => '0',
|
||||
s_axis_tvalid => '0',
|
||||
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_tlast => '0',
|
||||
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
m_axis_tready => '0',
|
||||
axi_aw_injectsbiterr => '0',
|
||||
axi_aw_injectdbiterr => '0',
|
||||
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_w_injectsbiterr => '0',
|
||||
axi_w_injectdbiterr => '0',
|
||||
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
axi_b_injectsbiterr => '0',
|
||||
axi_b_injectdbiterr => '0',
|
||||
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_ar_injectsbiterr => '0',
|
||||
axi_ar_injectdbiterr => '0',
|
||||
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_r_injectsbiterr => '0',
|
||||
axi_r_injectdbiterr => '0',
|
||||
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
axis_injectsbiterr => '0',
|
||||
axis_injectdbiterr => '0',
|
||||
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
|
||||
);
|
||||
END fifo_generator_1_arch;
|
||||
Binary file not shown.
@@ -0,0 +1,75 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
// IP Revision: 8
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
fifo_generator_3 your_instance_name (
|
||||
.rst(rst), // input wire rst
|
||||
.wr_clk(wr_clk), // input wire wr_clk
|
||||
.rd_clk(rd_clk), // input wire rd_clk
|
||||
.din(din), // input wire [23 : 0] din
|
||||
.wr_en(wr_en), // input wire wr_en
|
||||
.rd_en(rd_en), // input wire rd_en
|
||||
.dout(dout), // output wire [23 : 0] dout
|
||||
.full(full), // output wire full
|
||||
.empty(empty), // output wire empty
|
||||
.wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy
|
||||
.rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file fifo_generator_3.v when simulating
|
||||
// the core, fifo_generator_3. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,96 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
-- IP Revision: 8
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT fifo_generator_3
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC;
|
||||
wr_rst_busy : OUT STD_LOGIC;
|
||||
rd_rst_busy : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : fifo_generator_3
|
||||
PORT MAP (
|
||||
rst => rst,
|
||||
wr_clk => wr_clk,
|
||||
rd_clk => rd_clk,
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
dout => dout,
|
||||
full => full,
|
||||
empty => empty,
|
||||
wr_rst_busy => wr_rst_busy,
|
||||
rd_rst_busy => rd_rst_busy
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file fifo_generator_3.vhd when simulating
|
||||
-- the core, fifo_generator_3. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
#------------------------------------------------------------------------------#
|
||||
# Native FIFO Constraints #
|
||||
#------------------------------------------------------------------------------#
|
||||
|
||||
|
||||
|
||||
|
||||
################################################################################
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,69 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
#------------------------------------------------------------------------------#
|
||||
# Native FIFO Constraints #
|
||||
#------------------------------------------------------------------------------#
|
||||
|
||||
#set wr_clock [get_clocks -of_objects [get_ports wr_clk]]
|
||||
#set rd_clock [get_clocks -of_objects [get_ports rd_clk]]
|
||||
#set wr_clk_period [get_property PERIOD $wr_clock]
|
||||
#set rd_clk_period [get_property PERIOD $rd_clock]
|
||||
#set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
|
||||
|
||||
|
||||
# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
|
||||
|
||||
## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock]
|
||||
## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] $skew_value
|
||||
|
||||
## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock]
|
||||
## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] $skew_value
|
||||
#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.sckt_wrst_i_reg}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_inst/Q_reg_reg[0]}]
|
||||
#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[3].rd_rst_inst/Q_reg_reg[0]}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_wr_inst/Q_reg_reg[0]}]
|
||||
################################################################################
|
||||
@@ -0,0 +1,59 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 10 -name wr_clk [get_ports wr_clk]
|
||||
|
||||
create_clock -period 10 -name rd_clk [get_ports rd_clk]
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,34 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Oct 28 21:01:29 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/Project/A64/pl/a64_v0/LJS.gen/sources_1/ip/fifo_generator_3/fifo_generator_3_stub.v
|
||||
// Design : fifo_generator_3
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fifo_generator_v13_2_8,Vivado 2023.1" *)
|
||||
module fifo_generator_3(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
|
||||
empty, wr_rst_busy, rd_rst_busy)
|
||||
/* synthesis syn_black_box black_box_pad_pin="rst,din[23:0],wr_en,rd_en,dout[23:0],full,empty,wr_rst_busy,rd_rst_busy" */
|
||||
/* synthesis syn_force_seq_prim="wr_clk" */
|
||||
/* synthesis syn_force_seq_prim="rd_clk" */;
|
||||
input rst;
|
||||
input wr_clk /* synthesis syn_isclock = 1 */;
|
||||
input rd_clk /* synthesis syn_isclock = 1 */;
|
||||
input [23:0]din;
|
||||
input wr_en;
|
||||
input rd_en;
|
||||
output [23:0]dout;
|
||||
output full;
|
||||
output empty;
|
||||
output wr_rst_busy;
|
||||
output rd_rst_busy;
|
||||
endmodule
|
||||
@@ -0,0 +1,41 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Oct 28 21:01:29 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- d:/Project/A64/pl/a64_v0/LJS.gen/sources_1/ip/fifo_generator_3/fifo_generator_3_stub.vhdl
|
||||
-- Design : fifo_generator_3
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity fifo_generator_3 is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
wr_clk : in STD_LOGIC;
|
||||
rd_clk : in STD_LOGIC;
|
||||
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
|
||||
wr_en : in STD_LOGIC;
|
||||
rd_en : in STD_LOGIC;
|
||||
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
|
||||
full : out STD_LOGIC;
|
||||
empty : out STD_LOGIC;
|
||||
wr_rst_busy : out STD_LOGIC;
|
||||
rd_rst_busy : out STD_LOGIC
|
||||
);
|
||||
|
||||
end fifo_generator_3;
|
||||
|
||||
architecture stub of fifo_generator_3 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[23:0],wr_en,rd_en,dout[23:0],full,empty,wr_rst_busy,rd_rst_busy";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_8,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,528 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
// IP Revision: 8
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module fifo_generator_3 (
|
||||
rst,
|
||||
wr_clk,
|
||||
rd_clk,
|
||||
din,
|
||||
wr_en,
|
||||
rd_en,
|
||||
dout,
|
||||
full,
|
||||
empty,
|
||||
wr_rst_busy,
|
||||
rd_rst_busy
|
||||
);
|
||||
|
||||
input wire rst;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
|
||||
input wire wr_clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
|
||||
input wire rd_clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
|
||||
input wire [23 : 0] din;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
|
||||
input wire wr_en;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
|
||||
input wire rd_en;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
|
||||
output wire [23 : 0] dout;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
|
||||
output wire full;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
|
||||
output wire empty;
|
||||
output wire wr_rst_busy;
|
||||
output wire rd_rst_busy;
|
||||
|
||||
fifo_generator_v13_2_8 #(
|
||||
.C_COMMON_CLOCK(0),
|
||||
.C_SELECT_XPM(0),
|
||||
.C_COUNT_TYPE(0),
|
||||
.C_DATA_COUNT_WIDTH(10),
|
||||
.C_DEFAULT_VALUE("BlankString"),
|
||||
.C_DIN_WIDTH(24),
|
||||
.C_DOUT_RST_VAL("0"),
|
||||
.C_DOUT_WIDTH(24),
|
||||
.C_ENABLE_RLOCS(0),
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FULL_FLAGS_RST_VAL(1),
|
||||
.C_HAS_ALMOST_EMPTY(0),
|
||||
.C_HAS_ALMOST_FULL(0),
|
||||
.C_HAS_BACKUP(0),
|
||||
.C_HAS_DATA_COUNT(0),
|
||||
.C_HAS_INT_CLK(0),
|
||||
.C_HAS_MEMINIT_FILE(0),
|
||||
.C_HAS_OVERFLOW(0),
|
||||
.C_HAS_RD_DATA_COUNT(0),
|
||||
.C_HAS_RD_RST(0),
|
||||
.C_HAS_RST(1),
|
||||
.C_HAS_SRST(0),
|
||||
.C_HAS_UNDERFLOW(0),
|
||||
.C_HAS_VALID(0),
|
||||
.C_HAS_WR_ACK(0),
|
||||
.C_HAS_WR_DATA_COUNT(0),
|
||||
.C_HAS_WR_RST(0),
|
||||
.C_IMPLEMENTATION_TYPE(2),
|
||||
.C_INIT_WR_PNTR_VAL(0),
|
||||
.C_MEMORY_TYPE(1),
|
||||
.C_MIF_FILE_NAME("BlankString"),
|
||||
.C_OPTIMIZATION_MODE(0),
|
||||
.C_OVERFLOW_LOW(0),
|
||||
.C_PRELOAD_LATENCY(1),
|
||||
.C_PRELOAD_REGS(0),
|
||||
.C_PRIM_FIFO_TYPE("1kx36"),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
|
||||
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
|
||||
.C_PROG_EMPTY_TYPE(0),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL(1021),
|
||||
.C_PROG_FULL_THRESH_NEGATE_VAL(1020),
|
||||
.C_PROG_FULL_TYPE(0),
|
||||
.C_RD_DATA_COUNT_WIDTH(10),
|
||||
.C_RD_DEPTH(1024),
|
||||
.C_RD_FREQ(1),
|
||||
.C_RD_PNTR_WIDTH(10),
|
||||
.C_UNDERFLOW_LOW(0),
|
||||
.C_USE_DOUT_RST(1),
|
||||
.C_USE_ECC(0),
|
||||
.C_USE_EMBEDDED_REG(0),
|
||||
.C_USE_PIPELINE_REG(0),
|
||||
.C_POWER_SAVING_MODE(0),
|
||||
.C_USE_FIFO16_FLAGS(0),
|
||||
.C_USE_FWFT_DATA_COUNT(0),
|
||||
.C_VALID_LOW(0),
|
||||
.C_WR_ACK_LOW(0),
|
||||
.C_WR_DATA_COUNT_WIDTH(10),
|
||||
.C_WR_DEPTH(1024),
|
||||
.C_WR_FREQ(1),
|
||||
.C_WR_PNTR_WIDTH(10),
|
||||
.C_WR_RESPONSE_LATENCY(1),
|
||||
.C_MSGON_VAL(1),
|
||||
.C_ENABLE_RST_SYNC(1),
|
||||
.C_EN_SAFETY_CKT(1),
|
||||
.C_ERROR_INJECTION_TYPE(0),
|
||||
.C_SYNCHRONIZER_STAGE(2),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_HAS_AXI_WR_CHANNEL(1),
|
||||
.C_HAS_AXI_RD_CHANNEL(1),
|
||||
.C_HAS_SLAVE_CE(0),
|
||||
.C_HAS_MASTER_CE(0),
|
||||
.C_ADD_NGC_CONSTRAINT(0),
|
||||
.C_USE_COMMON_OVERFLOW(0),
|
||||
.C_USE_COMMON_UNDERFLOW(0),
|
||||
.C_USE_DEFAULT_SETTINGS(0),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(64),
|
||||
.C_AXI_LEN_WIDTH(8),
|
||||
.C_AXI_LOCK_WIDTH(1),
|
||||
.C_HAS_AXI_ID(0),
|
||||
.C_HAS_AXI_AWUSER(0),
|
||||
.C_HAS_AXI_WUSER(0),
|
||||
.C_HAS_AXI_BUSER(0),
|
||||
.C_HAS_AXI_ARUSER(0),
|
||||
.C_HAS_AXI_RUSER(0),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_HAS_AXIS_TDATA(1),
|
||||
.C_HAS_AXIS_TID(0),
|
||||
.C_HAS_AXIS_TDEST(0),
|
||||
.C_HAS_AXIS_TUSER(1),
|
||||
.C_HAS_AXIS_TREADY(1),
|
||||
.C_HAS_AXIS_TLAST(0),
|
||||
.C_HAS_AXIS_TSTRB(0),
|
||||
.C_HAS_AXIS_TKEEP(0),
|
||||
.C_AXIS_TDATA_WIDTH(8),
|
||||
.C_AXIS_TID_WIDTH(1),
|
||||
.C_AXIS_TDEST_WIDTH(1),
|
||||
.C_AXIS_TUSER_WIDTH(4),
|
||||
.C_AXIS_TSTRB_WIDTH(1),
|
||||
.C_AXIS_TKEEP_WIDTH(1),
|
||||
.C_WACH_TYPE(0),
|
||||
.C_WDCH_TYPE(0),
|
||||
.C_WRCH_TYPE(0),
|
||||
.C_RACH_TYPE(0),
|
||||
.C_RDCH_TYPE(0),
|
||||
.C_AXIS_TYPE(0),
|
||||
.C_IMPLEMENTATION_TYPE_WACH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WDCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WRCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_RACH(1),
|
||||
.C_IMPLEMENTATION_TYPE_RDCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_AXIS(1),
|
||||
.C_APPLICATION_TYPE_WACH(0),
|
||||
.C_APPLICATION_TYPE_WDCH(0),
|
||||
.C_APPLICATION_TYPE_WRCH(0),
|
||||
.C_APPLICATION_TYPE_RACH(0),
|
||||
.C_APPLICATION_TYPE_RDCH(0),
|
||||
.C_APPLICATION_TYPE_AXIS(0),
|
||||
.C_PRIM_FIFO_TYPE_WACH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
|
||||
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_RACH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
|
||||
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
|
||||
.C_USE_ECC_WACH(0),
|
||||
.C_USE_ECC_WDCH(0),
|
||||
.C_USE_ECC_WRCH(0),
|
||||
.C_USE_ECC_RACH(0),
|
||||
.C_USE_ECC_RDCH(0),
|
||||
.C_USE_ECC_AXIS(0),
|
||||
.C_ERROR_INJECTION_TYPE_WACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WRCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_RACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_RDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_AXIS(0),
|
||||
.C_DIN_WIDTH_WACH(1),
|
||||
.C_DIN_WIDTH_WDCH(64),
|
||||
.C_DIN_WIDTH_WRCH(2),
|
||||
.C_DIN_WIDTH_RACH(32),
|
||||
.C_DIN_WIDTH_RDCH(64),
|
||||
.C_DIN_WIDTH_AXIS(1),
|
||||
.C_WR_DEPTH_WACH(16),
|
||||
.C_WR_DEPTH_WDCH(1024),
|
||||
.C_WR_DEPTH_WRCH(16),
|
||||
.C_WR_DEPTH_RACH(16),
|
||||
.C_WR_DEPTH_RDCH(1024),
|
||||
.C_WR_DEPTH_AXIS(1024),
|
||||
.C_WR_PNTR_WIDTH_WACH(4),
|
||||
.C_WR_PNTR_WIDTH_WDCH(10),
|
||||
.C_WR_PNTR_WIDTH_WRCH(4),
|
||||
.C_WR_PNTR_WIDTH_RACH(4),
|
||||
.C_WR_PNTR_WIDTH_RDCH(10),
|
||||
.C_WR_PNTR_WIDTH_AXIS(10),
|
||||
.C_HAS_DATA_COUNTS_WACH(0),
|
||||
.C_HAS_DATA_COUNTS_WDCH(0),
|
||||
.C_HAS_DATA_COUNTS_WRCH(0),
|
||||
.C_HAS_DATA_COUNTS_RACH(0),
|
||||
.C_HAS_DATA_COUNTS_RDCH(0),
|
||||
.C_HAS_DATA_COUNTS_AXIS(0),
|
||||
.C_HAS_PROG_FLAGS_WACH(0),
|
||||
.C_HAS_PROG_FLAGS_WDCH(0),
|
||||
.C_HAS_PROG_FLAGS_WRCH(0),
|
||||
.C_HAS_PROG_FLAGS_RACH(0),
|
||||
.C_HAS_PROG_FLAGS_RDCH(0),
|
||||
.C_HAS_PROG_FLAGS_AXIS(0),
|
||||
.C_PROG_FULL_TYPE_WACH(0),
|
||||
.C_PROG_FULL_TYPE_WDCH(0),
|
||||
.C_PROG_FULL_TYPE_WRCH(0),
|
||||
.C_PROG_FULL_TYPE_RACH(0),
|
||||
.C_PROG_FULL_TYPE_RDCH(0),
|
||||
.C_PROG_FULL_TYPE_AXIS(0),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
|
||||
.C_PROG_EMPTY_TYPE_WACH(0),
|
||||
.C_PROG_EMPTY_TYPE_WDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_WRCH(0),
|
||||
.C_PROG_EMPTY_TYPE_RACH(0),
|
||||
.C_PROG_EMPTY_TYPE_RDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_AXIS(0),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
|
||||
.C_REG_SLICE_MODE_WACH(0),
|
||||
.C_REG_SLICE_MODE_WDCH(0),
|
||||
.C_REG_SLICE_MODE_WRCH(0),
|
||||
.C_REG_SLICE_MODE_RACH(0),
|
||||
.C_REG_SLICE_MODE_RDCH(0),
|
||||
.C_REG_SLICE_MODE_AXIS(0)
|
||||
) inst (
|
||||
.backup(1'D0),
|
||||
.backup_marker(1'D0),
|
||||
.clk(1'D0),
|
||||
.rst(rst),
|
||||
.srst(1'D0),
|
||||
.wr_clk(wr_clk),
|
||||
.wr_rst(1'D0),
|
||||
.rd_clk(rd_clk),
|
||||
.rd_rst(1'D0),
|
||||
.din(din),
|
||||
.wr_en(wr_en),
|
||||
.rd_en(rd_en),
|
||||
.prog_empty_thresh(10'B0),
|
||||
.prog_empty_thresh_assert(10'B0),
|
||||
.prog_empty_thresh_negate(10'B0),
|
||||
.prog_full_thresh(10'B0),
|
||||
.prog_full_thresh_assert(10'B0),
|
||||
.prog_full_thresh_negate(10'B0),
|
||||
.int_clk(1'D0),
|
||||
.injectdbiterr(1'D0),
|
||||
.injectsbiterr(1'D0),
|
||||
.sleep(1'D0),
|
||||
.dout(dout),
|
||||
.full(full),
|
||||
.almost_full(),
|
||||
.wr_ack(),
|
||||
.overflow(),
|
||||
.empty(empty),
|
||||
.almost_empty(),
|
||||
.valid(),
|
||||
.underflow(),
|
||||
.data_count(),
|
||||
.rd_data_count(),
|
||||
.wr_data_count(),
|
||||
.prog_full(),
|
||||
.prog_empty(),
|
||||
.sbiterr(),
|
||||
.dbiterr(),
|
||||
.wr_rst_busy(wr_rst_busy),
|
||||
.rd_rst_busy(rd_rst_busy),
|
||||
.m_aclk(1'D0),
|
||||
.s_aclk(1'D0),
|
||||
.s_aresetn(1'D0),
|
||||
.m_aclk_en(1'D0),
|
||||
.s_aclk_en(1'D0),
|
||||
.s_axi_awid(1'B0),
|
||||
.s_axi_awaddr(32'B0),
|
||||
.s_axi_awlen(8'B0),
|
||||
.s_axi_awsize(3'B0),
|
||||
.s_axi_awburst(2'B0),
|
||||
.s_axi_awlock(1'B0),
|
||||
.s_axi_awcache(4'B0),
|
||||
.s_axi_awprot(3'B0),
|
||||
.s_axi_awqos(4'B0),
|
||||
.s_axi_awregion(4'B0),
|
||||
.s_axi_awuser(1'B0),
|
||||
.s_axi_awvalid(1'D0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wid(1'B0),
|
||||
.s_axi_wdata(64'B0),
|
||||
.s_axi_wstrb(8'B0),
|
||||
.s_axi_wlast(1'D0),
|
||||
.s_axi_wuser(1'B0),
|
||||
.s_axi_wvalid(1'D0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'D0),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(),
|
||||
.m_axi_awready(1'D0),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(),
|
||||
.m_axi_wstrb(),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(),
|
||||
.m_axi_wready(1'D0),
|
||||
.m_axi_bid(1'B0),
|
||||
.m_axi_bresp(2'B0),
|
||||
.m_axi_buser(1'B0),
|
||||
.m_axi_bvalid(1'D0),
|
||||
.m_axi_bready(),
|
||||
.s_axi_arid(1'B0),
|
||||
.s_axi_araddr(32'B0),
|
||||
.s_axi_arlen(8'B0),
|
||||
.s_axi_arsize(3'B0),
|
||||
.s_axi_arburst(2'B0),
|
||||
.s_axi_arlock(1'B0),
|
||||
.s_axi_arcache(4'B0),
|
||||
.s_axi_arprot(3'B0),
|
||||
.s_axi_arqos(4'B0),
|
||||
.s_axi_arregion(4'B0),
|
||||
.s_axi_aruser(1'B0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'D0),
|
||||
.m_axi_rid(1'B0),
|
||||
.m_axi_rdata(64'B0),
|
||||
.m_axi_rresp(2'B0),
|
||||
.m_axi_rlast(1'D0),
|
||||
.m_axi_ruser(1'B0),
|
||||
.m_axi_rvalid(1'D0),
|
||||
.m_axi_rready(),
|
||||
.s_axis_tvalid(1'D0),
|
||||
.s_axis_tready(),
|
||||
.s_axis_tdata(8'B0),
|
||||
.s_axis_tstrb(1'B0),
|
||||
.s_axis_tkeep(1'B0),
|
||||
.s_axis_tlast(1'D0),
|
||||
.s_axis_tid(1'B0),
|
||||
.s_axis_tdest(1'B0),
|
||||
.s_axis_tuser(4'B0),
|
||||
.m_axis_tvalid(),
|
||||
.m_axis_tready(1'D0),
|
||||
.m_axis_tdata(),
|
||||
.m_axis_tstrb(),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser(),
|
||||
.axi_aw_injectsbiterr(1'D0),
|
||||
.axi_aw_injectdbiterr(1'D0),
|
||||
.axi_aw_prog_full_thresh(4'B0),
|
||||
.axi_aw_prog_empty_thresh(4'B0),
|
||||
.axi_aw_data_count(),
|
||||
.axi_aw_wr_data_count(),
|
||||
.axi_aw_rd_data_count(),
|
||||
.axi_aw_sbiterr(),
|
||||
.axi_aw_dbiterr(),
|
||||
.axi_aw_overflow(),
|
||||
.axi_aw_underflow(),
|
||||
.axi_aw_prog_full(),
|
||||
.axi_aw_prog_empty(),
|
||||
.axi_w_injectsbiterr(1'D0),
|
||||
.axi_w_injectdbiterr(1'D0),
|
||||
.axi_w_prog_full_thresh(10'B0),
|
||||
.axi_w_prog_empty_thresh(10'B0),
|
||||
.axi_w_data_count(),
|
||||
.axi_w_wr_data_count(),
|
||||
.axi_w_rd_data_count(),
|
||||
.axi_w_sbiterr(),
|
||||
.axi_w_dbiterr(),
|
||||
.axi_w_overflow(),
|
||||
.axi_w_underflow(),
|
||||
.axi_w_prog_full(),
|
||||
.axi_w_prog_empty(),
|
||||
.axi_b_injectsbiterr(1'D0),
|
||||
.axi_b_injectdbiterr(1'D0),
|
||||
.axi_b_prog_full_thresh(4'B0),
|
||||
.axi_b_prog_empty_thresh(4'B0),
|
||||
.axi_b_data_count(),
|
||||
.axi_b_wr_data_count(),
|
||||
.axi_b_rd_data_count(),
|
||||
.axi_b_sbiterr(),
|
||||
.axi_b_dbiterr(),
|
||||
.axi_b_overflow(),
|
||||
.axi_b_underflow(),
|
||||
.axi_b_prog_full(),
|
||||
.axi_b_prog_empty(),
|
||||
.axi_ar_injectsbiterr(1'D0),
|
||||
.axi_ar_injectdbiterr(1'D0),
|
||||
.axi_ar_prog_full_thresh(4'B0),
|
||||
.axi_ar_prog_empty_thresh(4'B0),
|
||||
.axi_ar_data_count(),
|
||||
.axi_ar_wr_data_count(),
|
||||
.axi_ar_rd_data_count(),
|
||||
.axi_ar_sbiterr(),
|
||||
.axi_ar_dbiterr(),
|
||||
.axi_ar_overflow(),
|
||||
.axi_ar_underflow(),
|
||||
.axi_ar_prog_full(),
|
||||
.axi_ar_prog_empty(),
|
||||
.axi_r_injectsbiterr(1'D0),
|
||||
.axi_r_injectdbiterr(1'D0),
|
||||
.axi_r_prog_full_thresh(10'B0),
|
||||
.axi_r_prog_empty_thresh(10'B0),
|
||||
.axi_r_data_count(),
|
||||
.axi_r_wr_data_count(),
|
||||
.axi_r_rd_data_count(),
|
||||
.axi_r_sbiterr(),
|
||||
.axi_r_dbiterr(),
|
||||
.axi_r_overflow(),
|
||||
.axi_r_underflow(),
|
||||
.axi_r_prog_full(),
|
||||
.axi_r_prog_empty(),
|
||||
.axis_injectsbiterr(1'D0),
|
||||
.axis_injectdbiterr(1'D0),
|
||||
.axis_prog_full_thresh(10'B0),
|
||||
.axis_prog_empty_thresh(10'B0),
|
||||
.axis_data_count(),
|
||||
.axis_wr_data_count(),
|
||||
.axis_rd_data_count(),
|
||||
.axis_sbiterr(),
|
||||
.axis_dbiterr(),
|
||||
.axis_overflow(),
|
||||
.axis_underflow(),
|
||||
.axis_prog_full(),
|
||||
.axis_prog_empty()
|
||||
);
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,862 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
-- IP Revision: 8
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY fifo_generator_v13_2_8;
|
||||
USE fifo_generator_v13_2_8.fifo_generator_v13_2_8;
|
||||
|
||||
ENTITY fifo_generator_3 IS
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC;
|
||||
wr_rst_busy : OUT STD_LOGIC;
|
||||
rd_rst_busy : OUT STD_LOGIC
|
||||
);
|
||||
END fifo_generator_3;
|
||||
|
||||
ARCHITECTURE fifo_generator_3_arch OF fifo_generator_3 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_3_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT fifo_generator_v13_2_8 IS
|
||||
GENERIC (
|
||||
C_COMMON_CLOCK : INTEGER;
|
||||
C_SELECT_XPM : INTEGER;
|
||||
C_COUNT_TYPE : INTEGER;
|
||||
C_DATA_COUNT_WIDTH : INTEGER;
|
||||
C_DEFAULT_VALUE : STRING;
|
||||
C_DIN_WIDTH : INTEGER;
|
||||
C_DOUT_RST_VAL : STRING;
|
||||
C_DOUT_WIDTH : INTEGER;
|
||||
C_ENABLE_RLOCS : INTEGER;
|
||||
C_FAMILY : STRING;
|
||||
C_FULL_FLAGS_RST_VAL : INTEGER;
|
||||
C_HAS_ALMOST_EMPTY : INTEGER;
|
||||
C_HAS_ALMOST_FULL : INTEGER;
|
||||
C_HAS_BACKUP : INTEGER;
|
||||
C_HAS_DATA_COUNT : INTEGER;
|
||||
C_HAS_INT_CLK : INTEGER;
|
||||
C_HAS_MEMINIT_FILE : INTEGER;
|
||||
C_HAS_OVERFLOW : INTEGER;
|
||||
C_HAS_RD_DATA_COUNT : INTEGER;
|
||||
C_HAS_RD_RST : INTEGER;
|
||||
C_HAS_RST : INTEGER;
|
||||
C_HAS_SRST : INTEGER;
|
||||
C_HAS_UNDERFLOW : INTEGER;
|
||||
C_HAS_VALID : INTEGER;
|
||||
C_HAS_WR_ACK : INTEGER;
|
||||
C_HAS_WR_DATA_COUNT : INTEGER;
|
||||
C_HAS_WR_RST : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE : INTEGER;
|
||||
C_INIT_WR_PNTR_VAL : INTEGER;
|
||||
C_MEMORY_TYPE : INTEGER;
|
||||
C_MIF_FILE_NAME : STRING;
|
||||
C_OPTIMIZATION_MODE : INTEGER;
|
||||
C_OVERFLOW_LOW : INTEGER;
|
||||
C_PRELOAD_LATENCY : INTEGER;
|
||||
C_PRELOAD_REGS : INTEGER;
|
||||
C_PRIM_FIFO_TYPE : STRING;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
|
||||
C_PROG_EMPTY_TYPE : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
|
||||
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
|
||||
C_PROG_FULL_TYPE : INTEGER;
|
||||
C_RD_DATA_COUNT_WIDTH : INTEGER;
|
||||
C_RD_DEPTH : INTEGER;
|
||||
C_RD_FREQ : INTEGER;
|
||||
C_RD_PNTR_WIDTH : INTEGER;
|
||||
C_UNDERFLOW_LOW : INTEGER;
|
||||
C_USE_DOUT_RST : INTEGER;
|
||||
C_USE_ECC : INTEGER;
|
||||
C_USE_EMBEDDED_REG : INTEGER;
|
||||
C_USE_PIPELINE_REG : INTEGER;
|
||||
C_POWER_SAVING_MODE : INTEGER;
|
||||
C_USE_FIFO16_FLAGS : INTEGER;
|
||||
C_USE_FWFT_DATA_COUNT : INTEGER;
|
||||
C_VALID_LOW : INTEGER;
|
||||
C_WR_ACK_LOW : INTEGER;
|
||||
C_WR_DATA_COUNT_WIDTH : INTEGER;
|
||||
C_WR_DEPTH : INTEGER;
|
||||
C_WR_FREQ : INTEGER;
|
||||
C_WR_PNTR_WIDTH : INTEGER;
|
||||
C_WR_RESPONSE_LATENCY : INTEGER;
|
||||
C_MSGON_VAL : INTEGER;
|
||||
C_ENABLE_RST_SYNC : INTEGER;
|
||||
C_EN_SAFETY_CKT : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE : INTEGER;
|
||||
C_SYNCHRONIZER_STAGE : INTEGER;
|
||||
C_INTERFACE_TYPE : INTEGER;
|
||||
C_AXI_TYPE : INTEGER;
|
||||
C_HAS_AXI_WR_CHANNEL : INTEGER;
|
||||
C_HAS_AXI_RD_CHANNEL : INTEGER;
|
||||
C_HAS_SLAVE_CE : INTEGER;
|
||||
C_HAS_MASTER_CE : INTEGER;
|
||||
C_ADD_NGC_CONSTRAINT : INTEGER;
|
||||
C_USE_COMMON_OVERFLOW : INTEGER;
|
||||
C_USE_COMMON_UNDERFLOW : INTEGER;
|
||||
C_USE_DEFAULT_SETTINGS : INTEGER;
|
||||
C_AXI_ID_WIDTH : INTEGER;
|
||||
C_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_AXI_DATA_WIDTH : INTEGER;
|
||||
C_AXI_LEN_WIDTH : INTEGER;
|
||||
C_AXI_LOCK_WIDTH : INTEGER;
|
||||
C_HAS_AXI_ID : INTEGER;
|
||||
C_HAS_AXI_AWUSER : INTEGER;
|
||||
C_HAS_AXI_WUSER : INTEGER;
|
||||
C_HAS_AXI_BUSER : INTEGER;
|
||||
C_HAS_AXI_ARUSER : INTEGER;
|
||||
C_HAS_AXI_RUSER : INTEGER;
|
||||
C_AXI_ARUSER_WIDTH : INTEGER;
|
||||
C_AXI_AWUSER_WIDTH : INTEGER;
|
||||
C_AXI_WUSER_WIDTH : INTEGER;
|
||||
C_AXI_BUSER_WIDTH : INTEGER;
|
||||
C_AXI_RUSER_WIDTH : INTEGER;
|
||||
C_HAS_AXIS_TDATA : INTEGER;
|
||||
C_HAS_AXIS_TID : INTEGER;
|
||||
C_HAS_AXIS_TDEST : INTEGER;
|
||||
C_HAS_AXIS_TUSER : INTEGER;
|
||||
C_HAS_AXIS_TREADY : INTEGER;
|
||||
C_HAS_AXIS_TLAST : INTEGER;
|
||||
C_HAS_AXIS_TSTRB : INTEGER;
|
||||
C_HAS_AXIS_TKEEP : INTEGER;
|
||||
C_AXIS_TDATA_WIDTH : INTEGER;
|
||||
C_AXIS_TID_WIDTH : INTEGER;
|
||||
C_AXIS_TDEST_WIDTH : INTEGER;
|
||||
C_AXIS_TUSER_WIDTH : INTEGER;
|
||||
C_AXIS_TSTRB_WIDTH : INTEGER;
|
||||
C_AXIS_TKEEP_WIDTH : INTEGER;
|
||||
C_WACH_TYPE : INTEGER;
|
||||
C_WDCH_TYPE : INTEGER;
|
||||
C_WRCH_TYPE : INTEGER;
|
||||
C_RACH_TYPE : INTEGER;
|
||||
C_RDCH_TYPE : INTEGER;
|
||||
C_AXIS_TYPE : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
|
||||
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
|
||||
C_APPLICATION_TYPE_WACH : INTEGER;
|
||||
C_APPLICATION_TYPE_WDCH : INTEGER;
|
||||
C_APPLICATION_TYPE_WRCH : INTEGER;
|
||||
C_APPLICATION_TYPE_RACH : INTEGER;
|
||||
C_APPLICATION_TYPE_RDCH : INTEGER;
|
||||
C_APPLICATION_TYPE_AXIS : INTEGER;
|
||||
C_PRIM_FIFO_TYPE_WACH : STRING;
|
||||
C_PRIM_FIFO_TYPE_WDCH : STRING;
|
||||
C_PRIM_FIFO_TYPE_WRCH : STRING;
|
||||
C_PRIM_FIFO_TYPE_RACH : STRING;
|
||||
C_PRIM_FIFO_TYPE_RDCH : STRING;
|
||||
C_PRIM_FIFO_TYPE_AXIS : STRING;
|
||||
C_USE_ECC_WACH : INTEGER;
|
||||
C_USE_ECC_WDCH : INTEGER;
|
||||
C_USE_ECC_WRCH : INTEGER;
|
||||
C_USE_ECC_RACH : INTEGER;
|
||||
C_USE_ECC_RDCH : INTEGER;
|
||||
C_USE_ECC_AXIS : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
|
||||
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
|
||||
C_DIN_WIDTH_WACH : INTEGER;
|
||||
C_DIN_WIDTH_WDCH : INTEGER;
|
||||
C_DIN_WIDTH_WRCH : INTEGER;
|
||||
C_DIN_WIDTH_RACH : INTEGER;
|
||||
C_DIN_WIDTH_RDCH : INTEGER;
|
||||
C_DIN_WIDTH_AXIS : INTEGER;
|
||||
C_WR_DEPTH_WACH : INTEGER;
|
||||
C_WR_DEPTH_WDCH : INTEGER;
|
||||
C_WR_DEPTH_WRCH : INTEGER;
|
||||
C_WR_DEPTH_RACH : INTEGER;
|
||||
C_WR_DEPTH_RDCH : INTEGER;
|
||||
C_WR_DEPTH_AXIS : INTEGER;
|
||||
C_WR_PNTR_WIDTH_WACH : INTEGER;
|
||||
C_WR_PNTR_WIDTH_WDCH : INTEGER;
|
||||
C_WR_PNTR_WIDTH_WRCH : INTEGER;
|
||||
C_WR_PNTR_WIDTH_RACH : INTEGER;
|
||||
C_WR_PNTR_WIDTH_RDCH : INTEGER;
|
||||
C_WR_PNTR_WIDTH_AXIS : INTEGER;
|
||||
C_HAS_DATA_COUNTS_WACH : INTEGER;
|
||||
C_HAS_DATA_COUNTS_WDCH : INTEGER;
|
||||
C_HAS_DATA_COUNTS_WRCH : INTEGER;
|
||||
C_HAS_DATA_COUNTS_RACH : INTEGER;
|
||||
C_HAS_DATA_COUNTS_RDCH : INTEGER;
|
||||
C_HAS_DATA_COUNTS_AXIS : INTEGER;
|
||||
C_HAS_PROG_FLAGS_WACH : INTEGER;
|
||||
C_HAS_PROG_FLAGS_WDCH : INTEGER;
|
||||
C_HAS_PROG_FLAGS_WRCH : INTEGER;
|
||||
C_HAS_PROG_FLAGS_RACH : INTEGER;
|
||||
C_HAS_PROG_FLAGS_RDCH : INTEGER;
|
||||
C_HAS_PROG_FLAGS_AXIS : INTEGER;
|
||||
C_PROG_FULL_TYPE_WACH : INTEGER;
|
||||
C_PROG_FULL_TYPE_WDCH : INTEGER;
|
||||
C_PROG_FULL_TYPE_WRCH : INTEGER;
|
||||
C_PROG_FULL_TYPE_RACH : INTEGER;
|
||||
C_PROG_FULL_TYPE_RDCH : INTEGER;
|
||||
C_PROG_FULL_TYPE_AXIS : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
|
||||
C_PROG_EMPTY_TYPE_WACH : INTEGER;
|
||||
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
|
||||
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
|
||||
C_PROG_EMPTY_TYPE_RACH : INTEGER;
|
||||
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
|
||||
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
|
||||
C_REG_SLICE_MODE_WACH : INTEGER;
|
||||
C_REG_SLICE_MODE_WDCH : INTEGER;
|
||||
C_REG_SLICE_MODE_WRCH : INTEGER;
|
||||
C_REG_SLICE_MODE_RACH : INTEGER;
|
||||
C_REG_SLICE_MODE_RDCH : INTEGER;
|
||||
C_REG_SLICE_MODE_AXIS : INTEGER
|
||||
);
|
||||
PORT (
|
||||
backup : IN STD_LOGIC;
|
||||
backup_marker : IN STD_LOGIC;
|
||||
clk : IN STD_LOGIC;
|
||||
rst : IN STD_LOGIC;
|
||||
srst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
wr_rst : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
rd_rst : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
int_clk : IN STD_LOGIC;
|
||||
injectdbiterr : IN STD_LOGIC;
|
||||
injectsbiterr : IN STD_LOGIC;
|
||||
sleep : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
almost_full : OUT STD_LOGIC;
|
||||
wr_ack : OUT STD_LOGIC;
|
||||
overflow : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC;
|
||||
almost_empty : OUT STD_LOGIC;
|
||||
valid : OUT STD_LOGIC;
|
||||
underflow : OUT STD_LOGIC;
|
||||
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
prog_full : OUT STD_LOGIC;
|
||||
prog_empty : OUT STD_LOGIC;
|
||||
sbiterr : OUT STD_LOGIC;
|
||||
dbiterr : OUT STD_LOGIC;
|
||||
wr_rst_busy : OUT STD_LOGIC;
|
||||
rd_rst_busy : OUT STD_LOGIC;
|
||||
m_aclk : IN STD_LOGIC;
|
||||
s_aclk : IN STD_LOGIC;
|
||||
s_aresetn : IN STD_LOGIC;
|
||||
m_aclk_en : IN STD_LOGIC;
|
||||
s_aclk_en : IN STD_LOGIC;
|
||||
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_awvalid : OUT STD_LOGIC;
|
||||
m_axi_awready : IN STD_LOGIC;
|
||||
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_wlast : OUT STD_LOGIC;
|
||||
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_wvalid : OUT STD_LOGIC;
|
||||
m_axi_wready : IN STD_LOGIC;
|
||||
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_bvalid : IN STD_LOGIC;
|
||||
m_axi_bready : OUT STD_LOGIC;
|
||||
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_arvalid : OUT STD_LOGIC;
|
||||
m_axi_arready : IN STD_LOGIC;
|
||||
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_rlast : IN STD_LOGIC;
|
||||
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axi_rvalid : IN STD_LOGIC;
|
||||
m_axi_rready : OUT STD_LOGIC;
|
||||
s_axis_tvalid : IN STD_LOGIC;
|
||||
s_axis_tready : OUT STD_LOGIC;
|
||||
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_tlast : IN STD_LOGIC;
|
||||
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_tvalid : OUT STD_LOGIC;
|
||||
m_axis_tready : IN STD_LOGIC;
|
||||
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_tlast : OUT STD_LOGIC;
|
||||
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_aw_injectsbiterr : IN STD_LOGIC;
|
||||
axi_aw_injectdbiterr : IN STD_LOGIC;
|
||||
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_aw_sbiterr : OUT STD_LOGIC;
|
||||
axi_aw_dbiterr : OUT STD_LOGIC;
|
||||
axi_aw_overflow : OUT STD_LOGIC;
|
||||
axi_aw_underflow : OUT STD_LOGIC;
|
||||
axi_aw_prog_full : OUT STD_LOGIC;
|
||||
axi_aw_prog_empty : OUT STD_LOGIC;
|
||||
axi_w_injectsbiterr : IN STD_LOGIC;
|
||||
axi_w_injectdbiterr : IN STD_LOGIC;
|
||||
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axi_w_sbiterr : OUT STD_LOGIC;
|
||||
axi_w_dbiterr : OUT STD_LOGIC;
|
||||
axi_w_overflow : OUT STD_LOGIC;
|
||||
axi_w_underflow : OUT STD_LOGIC;
|
||||
axi_w_prog_full : OUT STD_LOGIC;
|
||||
axi_w_prog_empty : OUT STD_LOGIC;
|
||||
axi_b_injectsbiterr : IN STD_LOGIC;
|
||||
axi_b_injectdbiterr : IN STD_LOGIC;
|
||||
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_b_sbiterr : OUT STD_LOGIC;
|
||||
axi_b_dbiterr : OUT STD_LOGIC;
|
||||
axi_b_overflow : OUT STD_LOGIC;
|
||||
axi_b_underflow : OUT STD_LOGIC;
|
||||
axi_b_prog_full : OUT STD_LOGIC;
|
||||
axi_b_prog_empty : OUT STD_LOGIC;
|
||||
axi_ar_injectsbiterr : IN STD_LOGIC;
|
||||
axi_ar_injectdbiterr : IN STD_LOGIC;
|
||||
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
axi_ar_sbiterr : OUT STD_LOGIC;
|
||||
axi_ar_dbiterr : OUT STD_LOGIC;
|
||||
axi_ar_overflow : OUT STD_LOGIC;
|
||||
axi_ar_underflow : OUT STD_LOGIC;
|
||||
axi_ar_prog_full : OUT STD_LOGIC;
|
||||
axi_ar_prog_empty : OUT STD_LOGIC;
|
||||
axi_r_injectsbiterr : IN STD_LOGIC;
|
||||
axi_r_injectdbiterr : IN STD_LOGIC;
|
||||
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axi_r_sbiterr : OUT STD_LOGIC;
|
||||
axi_r_dbiterr : OUT STD_LOGIC;
|
||||
axi_r_overflow : OUT STD_LOGIC;
|
||||
axi_r_underflow : OUT STD_LOGIC;
|
||||
axi_r_prog_full : OUT STD_LOGIC;
|
||||
axi_r_prog_empty : OUT STD_LOGIC;
|
||||
axis_injectsbiterr : IN STD_LOGIC;
|
||||
axis_injectdbiterr : IN STD_LOGIC;
|
||||
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
axis_sbiterr : OUT STD_LOGIC;
|
||||
axis_dbiterr : OUT STD_LOGIC;
|
||||
axis_overflow : OUT STD_LOGIC;
|
||||
axis_underflow : OUT STD_LOGIC;
|
||||
axis_prog_full : OUT STD_LOGIC;
|
||||
axis_prog_empty : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT fifo_generator_v13_2_8;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF fifo_generator_3_arch: ARCHITECTURE IS "fifo_generator_v13_2_8,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_3_arch : ARCHITECTURE IS "fifo_generator_3,fifo_generator_v13_2_8,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_3_arch: ARCHITECTURE IS "fifo_generator_3,fifo_generator_v13_2_8,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.2,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=24,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=24,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_H" &
|
||||
"AS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FUL" &
|
||||
"L_THRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_I" &
|
||||
"NTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSE" &
|
||||
"R_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATIO" &
|
||||
"N_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=" &
|
||||
"0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RD" &
|
||||
"CH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WA" &
|
||||
"CH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH" &
|
||||
"_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF rd_clk: SIGNAL IS "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF wr_clk: SIGNAL IS "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
|
||||
BEGIN
|
||||
U0 : fifo_generator_v13_2_8
|
||||
GENERIC MAP (
|
||||
C_COMMON_CLOCK => 0,
|
||||
C_SELECT_XPM => 0,
|
||||
C_COUNT_TYPE => 0,
|
||||
C_DATA_COUNT_WIDTH => 10,
|
||||
C_DEFAULT_VALUE => "BlankString",
|
||||
C_DIN_WIDTH => 24,
|
||||
C_DOUT_RST_VAL => "0",
|
||||
C_DOUT_WIDTH => 24,
|
||||
C_ENABLE_RLOCS => 0,
|
||||
C_FAMILY => "zynq",
|
||||
C_FULL_FLAGS_RST_VAL => 1,
|
||||
C_HAS_ALMOST_EMPTY => 0,
|
||||
C_HAS_ALMOST_FULL => 0,
|
||||
C_HAS_BACKUP => 0,
|
||||
C_HAS_DATA_COUNT => 0,
|
||||
C_HAS_INT_CLK => 0,
|
||||
C_HAS_MEMINIT_FILE => 0,
|
||||
C_HAS_OVERFLOW => 0,
|
||||
C_HAS_RD_DATA_COUNT => 0,
|
||||
C_HAS_RD_RST => 0,
|
||||
C_HAS_RST => 1,
|
||||
C_HAS_SRST => 0,
|
||||
C_HAS_UNDERFLOW => 0,
|
||||
C_HAS_VALID => 0,
|
||||
C_HAS_WR_ACK => 0,
|
||||
C_HAS_WR_DATA_COUNT => 0,
|
||||
C_HAS_WR_RST => 0,
|
||||
C_IMPLEMENTATION_TYPE => 2,
|
||||
C_INIT_WR_PNTR_VAL => 0,
|
||||
C_MEMORY_TYPE => 1,
|
||||
C_MIF_FILE_NAME => "BlankString",
|
||||
C_OPTIMIZATION_MODE => 0,
|
||||
C_OVERFLOW_LOW => 0,
|
||||
C_PRELOAD_LATENCY => 1,
|
||||
C_PRELOAD_REGS => 0,
|
||||
C_PRIM_FIFO_TYPE => "1kx36",
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
|
||||
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
|
||||
C_PROG_EMPTY_TYPE => 0,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
|
||||
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
|
||||
C_PROG_FULL_TYPE => 0,
|
||||
C_RD_DATA_COUNT_WIDTH => 10,
|
||||
C_RD_DEPTH => 1024,
|
||||
C_RD_FREQ => 1,
|
||||
C_RD_PNTR_WIDTH => 10,
|
||||
C_UNDERFLOW_LOW => 0,
|
||||
C_USE_DOUT_RST => 1,
|
||||
C_USE_ECC => 0,
|
||||
C_USE_EMBEDDED_REG => 0,
|
||||
C_USE_PIPELINE_REG => 0,
|
||||
C_POWER_SAVING_MODE => 0,
|
||||
C_USE_FIFO16_FLAGS => 0,
|
||||
C_USE_FWFT_DATA_COUNT => 0,
|
||||
C_VALID_LOW => 0,
|
||||
C_WR_ACK_LOW => 0,
|
||||
C_WR_DATA_COUNT_WIDTH => 10,
|
||||
C_WR_DEPTH => 1024,
|
||||
C_WR_FREQ => 1,
|
||||
C_WR_PNTR_WIDTH => 10,
|
||||
C_WR_RESPONSE_LATENCY => 1,
|
||||
C_MSGON_VAL => 1,
|
||||
C_ENABLE_RST_SYNC => 1,
|
||||
C_EN_SAFETY_CKT => 1,
|
||||
C_ERROR_INJECTION_TYPE => 0,
|
||||
C_SYNCHRONIZER_STAGE => 2,
|
||||
C_INTERFACE_TYPE => 0,
|
||||
C_AXI_TYPE => 1,
|
||||
C_HAS_AXI_WR_CHANNEL => 1,
|
||||
C_HAS_AXI_RD_CHANNEL => 1,
|
||||
C_HAS_SLAVE_CE => 0,
|
||||
C_HAS_MASTER_CE => 0,
|
||||
C_ADD_NGC_CONSTRAINT => 0,
|
||||
C_USE_COMMON_OVERFLOW => 0,
|
||||
C_USE_COMMON_UNDERFLOW => 0,
|
||||
C_USE_DEFAULT_SETTINGS => 0,
|
||||
C_AXI_ID_WIDTH => 1,
|
||||
C_AXI_ADDR_WIDTH => 32,
|
||||
C_AXI_DATA_WIDTH => 64,
|
||||
C_AXI_LEN_WIDTH => 8,
|
||||
C_AXI_LOCK_WIDTH => 1,
|
||||
C_HAS_AXI_ID => 0,
|
||||
C_HAS_AXI_AWUSER => 0,
|
||||
C_HAS_AXI_WUSER => 0,
|
||||
C_HAS_AXI_BUSER => 0,
|
||||
C_HAS_AXI_ARUSER => 0,
|
||||
C_HAS_AXI_RUSER => 0,
|
||||
C_AXI_ARUSER_WIDTH => 1,
|
||||
C_AXI_AWUSER_WIDTH => 1,
|
||||
C_AXI_WUSER_WIDTH => 1,
|
||||
C_AXI_BUSER_WIDTH => 1,
|
||||
C_AXI_RUSER_WIDTH => 1,
|
||||
C_HAS_AXIS_TDATA => 1,
|
||||
C_HAS_AXIS_TID => 0,
|
||||
C_HAS_AXIS_TDEST => 0,
|
||||
C_HAS_AXIS_TUSER => 1,
|
||||
C_HAS_AXIS_TREADY => 1,
|
||||
C_HAS_AXIS_TLAST => 0,
|
||||
C_HAS_AXIS_TSTRB => 0,
|
||||
C_HAS_AXIS_TKEEP => 0,
|
||||
C_AXIS_TDATA_WIDTH => 8,
|
||||
C_AXIS_TID_WIDTH => 1,
|
||||
C_AXIS_TDEST_WIDTH => 1,
|
||||
C_AXIS_TUSER_WIDTH => 4,
|
||||
C_AXIS_TSTRB_WIDTH => 1,
|
||||
C_AXIS_TKEEP_WIDTH => 1,
|
||||
C_WACH_TYPE => 0,
|
||||
C_WDCH_TYPE => 0,
|
||||
C_WRCH_TYPE => 0,
|
||||
C_RACH_TYPE => 0,
|
||||
C_RDCH_TYPE => 0,
|
||||
C_AXIS_TYPE => 0,
|
||||
C_IMPLEMENTATION_TYPE_WACH => 1,
|
||||
C_IMPLEMENTATION_TYPE_WDCH => 1,
|
||||
C_IMPLEMENTATION_TYPE_WRCH => 1,
|
||||
C_IMPLEMENTATION_TYPE_RACH => 1,
|
||||
C_IMPLEMENTATION_TYPE_RDCH => 1,
|
||||
C_IMPLEMENTATION_TYPE_AXIS => 1,
|
||||
C_APPLICATION_TYPE_WACH => 0,
|
||||
C_APPLICATION_TYPE_WDCH => 0,
|
||||
C_APPLICATION_TYPE_WRCH => 0,
|
||||
C_APPLICATION_TYPE_RACH => 0,
|
||||
C_APPLICATION_TYPE_RDCH => 0,
|
||||
C_APPLICATION_TYPE_AXIS => 0,
|
||||
C_PRIM_FIFO_TYPE_WACH => "512x36",
|
||||
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
|
||||
C_PRIM_FIFO_TYPE_WRCH => "512x36",
|
||||
C_PRIM_FIFO_TYPE_RACH => "512x36",
|
||||
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
|
||||
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
|
||||
C_USE_ECC_WACH => 0,
|
||||
C_USE_ECC_WDCH => 0,
|
||||
C_USE_ECC_WRCH => 0,
|
||||
C_USE_ECC_RACH => 0,
|
||||
C_USE_ECC_RDCH => 0,
|
||||
C_USE_ECC_AXIS => 0,
|
||||
C_ERROR_INJECTION_TYPE_WACH => 0,
|
||||
C_ERROR_INJECTION_TYPE_WDCH => 0,
|
||||
C_ERROR_INJECTION_TYPE_WRCH => 0,
|
||||
C_ERROR_INJECTION_TYPE_RACH => 0,
|
||||
C_ERROR_INJECTION_TYPE_RDCH => 0,
|
||||
C_ERROR_INJECTION_TYPE_AXIS => 0,
|
||||
C_DIN_WIDTH_WACH => 1,
|
||||
C_DIN_WIDTH_WDCH => 64,
|
||||
C_DIN_WIDTH_WRCH => 2,
|
||||
C_DIN_WIDTH_RACH => 32,
|
||||
C_DIN_WIDTH_RDCH => 64,
|
||||
C_DIN_WIDTH_AXIS => 1,
|
||||
C_WR_DEPTH_WACH => 16,
|
||||
C_WR_DEPTH_WDCH => 1024,
|
||||
C_WR_DEPTH_WRCH => 16,
|
||||
C_WR_DEPTH_RACH => 16,
|
||||
C_WR_DEPTH_RDCH => 1024,
|
||||
C_WR_DEPTH_AXIS => 1024,
|
||||
C_WR_PNTR_WIDTH_WACH => 4,
|
||||
C_WR_PNTR_WIDTH_WDCH => 10,
|
||||
C_WR_PNTR_WIDTH_WRCH => 4,
|
||||
C_WR_PNTR_WIDTH_RACH => 4,
|
||||
C_WR_PNTR_WIDTH_RDCH => 10,
|
||||
C_WR_PNTR_WIDTH_AXIS => 10,
|
||||
C_HAS_DATA_COUNTS_WACH => 0,
|
||||
C_HAS_DATA_COUNTS_WDCH => 0,
|
||||
C_HAS_DATA_COUNTS_WRCH => 0,
|
||||
C_HAS_DATA_COUNTS_RACH => 0,
|
||||
C_HAS_DATA_COUNTS_RDCH => 0,
|
||||
C_HAS_DATA_COUNTS_AXIS => 0,
|
||||
C_HAS_PROG_FLAGS_WACH => 0,
|
||||
C_HAS_PROG_FLAGS_WDCH => 0,
|
||||
C_HAS_PROG_FLAGS_WRCH => 0,
|
||||
C_HAS_PROG_FLAGS_RACH => 0,
|
||||
C_HAS_PROG_FLAGS_RDCH => 0,
|
||||
C_HAS_PROG_FLAGS_AXIS => 0,
|
||||
C_PROG_FULL_TYPE_WACH => 0,
|
||||
C_PROG_FULL_TYPE_WDCH => 0,
|
||||
C_PROG_FULL_TYPE_WRCH => 0,
|
||||
C_PROG_FULL_TYPE_RACH => 0,
|
||||
C_PROG_FULL_TYPE_RDCH => 0,
|
||||
C_PROG_FULL_TYPE_AXIS => 0,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
|
||||
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
|
||||
C_PROG_EMPTY_TYPE_WACH => 0,
|
||||
C_PROG_EMPTY_TYPE_WDCH => 0,
|
||||
C_PROG_EMPTY_TYPE_WRCH => 0,
|
||||
C_PROG_EMPTY_TYPE_RACH => 0,
|
||||
C_PROG_EMPTY_TYPE_RDCH => 0,
|
||||
C_PROG_EMPTY_TYPE_AXIS => 0,
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
|
||||
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
|
||||
C_REG_SLICE_MODE_WACH => 0,
|
||||
C_REG_SLICE_MODE_WDCH => 0,
|
||||
C_REG_SLICE_MODE_WRCH => 0,
|
||||
C_REG_SLICE_MODE_RACH => 0,
|
||||
C_REG_SLICE_MODE_RDCH => 0,
|
||||
C_REG_SLICE_MODE_AXIS => 0
|
||||
)
|
||||
PORT MAP (
|
||||
backup => '0',
|
||||
backup_marker => '0',
|
||||
clk => '0',
|
||||
rst => rst,
|
||||
srst => '0',
|
||||
wr_clk => wr_clk,
|
||||
wr_rst => '0',
|
||||
rd_clk => rd_clk,
|
||||
rd_rst => '0',
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
int_clk => '0',
|
||||
injectdbiterr => '0',
|
||||
injectsbiterr => '0',
|
||||
sleep => '0',
|
||||
dout => dout,
|
||||
full => full,
|
||||
empty => empty,
|
||||
wr_rst_busy => wr_rst_busy,
|
||||
rd_rst_busy => rd_rst_busy,
|
||||
m_aclk => '0',
|
||||
s_aclk => '0',
|
||||
s_aresetn => '0',
|
||||
m_aclk_en => '0',
|
||||
s_aclk_en => '0',
|
||||
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awvalid => '0',
|
||||
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
|
||||
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi_wlast => '0',
|
||||
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_wvalid => '0',
|
||||
s_axi_bready => '0',
|
||||
m_axi_awready => '0',
|
||||
m_axi_wready => '0',
|
||||
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axi_bvalid => '0',
|
||||
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_arvalid => '0',
|
||||
s_axi_rready => '0',
|
||||
m_axi_arready => '0',
|
||||
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
|
||||
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_rlast => '0',
|
||||
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axi_rvalid => '0',
|
||||
s_axis_tvalid => '0',
|
||||
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_tlast => '0',
|
||||
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
m_axis_tready => '0',
|
||||
axi_aw_injectsbiterr => '0',
|
||||
axi_aw_injectdbiterr => '0',
|
||||
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_w_injectsbiterr => '0',
|
||||
axi_w_injectdbiterr => '0',
|
||||
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
axi_b_injectsbiterr => '0',
|
||||
axi_b_injectdbiterr => '0',
|
||||
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_ar_injectsbiterr => '0',
|
||||
axi_ar_injectdbiterr => '0',
|
||||
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_r_injectsbiterr => '0',
|
||||
axi_r_injectdbiterr => '0',
|
||||
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
axis_injectsbiterr => '0',
|
||||
axis_injectdbiterr => '0',
|
||||
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
|
||||
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
|
||||
);
|
||||
END fifo_generator_3_arch;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,104 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2011 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2011/04/26
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* General functions used by other Labtools IP cores. Functions will
|
||||
* be added as needed.
|
||||
*
|
||||
*Notes:
|
||||
* Include the file inside the Verilog module after the module and port
|
||||
* section. Do not include at the top of the module.
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
`include "ltlib_v1_0_0_ver.vh"
|
||||
|
||||
function integer clogb2;
|
||||
input integer depth;
|
||||
integer d;
|
||||
begin
|
||||
if (depth == 0)
|
||||
clogb2 = 1;
|
||||
else
|
||||
begin
|
||||
d = depth;
|
||||
for (clogb2=0; d > 0; clogb2 = clogb2+1)
|
||||
d = d >> 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function string_contains;
|
||||
input [`FAMILY_NAME_LENGTH*8-1:0] familyName;
|
||||
input [`FAMILY_NAME_LENGTH*8-1:0] expectedName;
|
||||
input integer expectedLength;
|
||||
integer i;
|
||||
integer j;
|
||||
reg temp_contain;
|
||||
begin
|
||||
string_contains = 1;
|
||||
temp_contain = 0;
|
||||
for (i=0; i<`FAMILY_NAME_LENGTH; i=i+1)
|
||||
begin
|
||||
if (familyName[(8*i)+:8] == expectedName[0+:8])
|
||||
begin
|
||||
temp_contain = 1;
|
||||
for (j=0; j<expectedLength; j=j+1)
|
||||
begin
|
||||
if (familyName[((8*i)+(8*j))+:8] != expectedName[(8*j)+:8])
|
||||
begin
|
||||
temp_contain = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
if (temp_contain == 1)
|
||||
begin
|
||||
string_contains = 1;
|
||||
i = `FAMILY_NAME_LENGTH;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer supports_bscane2;
|
||||
input [`FAMILY_NAME_LENGTH-1:0] familyName;
|
||||
begin
|
||||
if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
|
||||
supports_bscane2 = 1;
|
||||
else
|
||||
supports_bscane2 = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer supports_series7_bufr;
|
||||
input [`FAMILY_NAME_LENGTH-1:0] familyName;
|
||||
begin
|
||||
if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
|
||||
supports_series7_bufr = 1;
|
||||
else
|
||||
supports_series7_bufr = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer supports_series7_startup;
|
||||
input [`FAMILY_NAME_LENGTH-1:0] familyName;
|
||||
begin
|
||||
if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
|
||||
supports_series7_startup = 1;
|
||||
else
|
||||
supports_series7_startup = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
@@ -0,0 +1,106 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define values for Verilog instatiation of labtools ip
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_MFG_ID 0
|
||||
`define XILINX_MFG_ID 1
|
||||
`define XILINX_AND_AGILENT_MFG_ID 2
|
||||
`define GC_XILINX_MFG_ID `XILINX_MFG_ID
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_CORE_TYPE 0
|
||||
`define ICON_CORE_TYPE 1
|
||||
`define ILA_CORE_TYPE 2
|
||||
`define IBA_GENERIC_CORE_TYPE 3
|
||||
`define IBA_OPB_CORE_TYPE 4
|
||||
`define IBA_PLB_CORE_TYPE 5
|
||||
`define ILA_ATC_CORE_TYPE 6
|
||||
`define IBA_OPB_ATC_CORE_TYPE 7
|
||||
`define IBA_PLB_ATC_CORE_TYPE 8
|
||||
`define VIO_CORE_TYPE 9
|
||||
`define ATC2_CORE_TYPE 10
|
||||
`define ATC3_CORE_TYPE 11
|
||||
`define GC_RESERVED_CORE_TYPE2 12
|
||||
`define IBERT_CORE_TYPE 13
|
||||
`define GC_XSDB_MASTER_V1_0 14
|
||||
`define GC_ICON_NULL_CORE_TYPE 15
|
||||
|
||||
//
|
||||
// Width of the ChipScope Pro Core CONTROL port
|
||||
//
|
||||
`define CONTROL_WIDTH 36
|
||||
|
||||
// Match unit type
|
||||
`define MATCH_UNIT_TYPEA_ALLX 0
|
||||
//`define MATCH_UNIT_TYPE_GANDOR 2
|
||||
//`define MATCH_UNIT_TYPE_GANDORX 3
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Device family constants
|
||||
//
|
||||
`define FAMILY_NAME_LENGTH 15 //leave room for radhard/automotive and low power part names
|
||||
`define FAMILY_VIRTEX7 "virtex7"
|
||||
`define FAMILY_VIRTEX7_LENGTH 7
|
||||
`define FAMILY_KINTEX7 "kintex7"
|
||||
`define FAMILY_KINTEX7_LENGTH 7
|
||||
`define FAMILY_ARTIX7 "artix7"
|
||||
`define FAMILY_ARTIX7_LENGTH 6
|
||||
`define FAMILY_ZYNQ "zynq"
|
||||
`define FAMILY_ZYNQ_LENGTH 4
|
||||
|
||||
//
|
||||
// Architecture match type constants, start at 100 so that code can't incorrectly mix up family and match unit type
|
||||
//
|
||||
`define ARCH_MATCH_TYPE_A 100
|
||||
|
||||
//
|
||||
// Device JTAG Stuff
|
||||
//
|
||||
`define GC_SBT_IR_W 10;
|
||||
`define GC_SBT_IR_ID_INSTR 10'b1111001001
|
||||
`define GC_SBT_IR_USER1_INSTR 10'b11_1100_0010
|
||||
`define GC_CHIP_ID_CHIPSCOPE_SBT 32'b0000_1010_0000_0000_0011_0000_1001_0011
|
||||
// 0a00_3093
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Virtex7
|
||||
//
|
||||
// IR Info
|
||||
`define GC_V7_IR_W 6
|
||||
`define GC_V7_IR_ID_INSTR 6'b00_1001
|
||||
`define GC_V7_IR_USER1_INSTR 6'b00_0010
|
||||
`define GC_V7_IR_USER2_INSTR 6'b00_0011
|
||||
`define GC_V7_IR_USER3_INSTR 6'b10_0010
|
||||
`define GC_V7_IR_USER4_INSTR 6'b10_0011
|
||||
// Chip IDs
|
||||
`define GC_CHIP_ID_XC7V285T 32'b0000_0011_1010_0110_0100_0000_1001_0011
|
||||
// 0424a093
|
||||
|
||||
|
||||
@@ -0,0 +1,50 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define Values for Verilog instatiation of icn2xsdb_mstrbr_ver
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
`define GC_XSDB_MSI_SL_SEL_WIDTH 8 /* Slave Select Width */
|
||||
`define GC_XSDB_MSI_ADDR_WIDTH 17 /* Address Width */
|
||||
`define GC_XSDB_MSI_BRST_WD_LEN_WIDTH 17
|
||||
`define GC_XSDB_MSI_DATA_WIDTH 16 /* Data Width */
|
||||
`define GC_XSDB_MSI_BRST_CNT_WIDTH 16 /* Burst Count Width */
|
||||
`define GC_XSDB_S_IPORT_WIDTH 37 /* Slave Port input interface width */
|
||||
|
||||
`define GC_XSDB_S_OPORT_WIDTH 17 /* Slave Port output interface width */
|
||||
|
||||
`define GC_XSDB_S_ADDR_WIDTH `GC_XSDB_MSI_ADDR_WIDTH /* Slave Addr width */
|
||||
`define GC_XSDB_S_DATA_WIDTH `GC_XSDB_MSI_DATA_WIDTH /* Slave Data width */
|
||||
|
||||
`define GC_IPORT_RST_IDX 0
|
||||
`define GC_IPORT_DCLK_IDX 1
|
||||
`define GC_IPORT_DEN_IDX 2
|
||||
`define GC_IPORT_DWE_IDX 3
|
||||
`define GC_IPORT_DADDR_IDX 4
|
||||
`define GC_IPORT_DI_IDX `GC_IPORT_DADDR_IDX+`GC_XSDB_S_ADDR_WIDTH
|
||||
`define GC_OPORT_RDY_IDX 0
|
||||
`define GC_OPORT_DO_IDX 1
|
||||
|
||||
`define GC_ICN_CTL_WIDTH 36
|
||||
`define GC_ICN_CMD4_WIDTH 3 + `GC_XSDB_MSI_SL_SEL_WIDTH+ `GC_XSDB_MSI_BRST_WD_LEN_WIDTH
|
||||
`define GC_ICN_CMD5_WIDTH 1 + `GC_XSDB_MSI_ADDR_WIDTH
|
||||
`define GC_ICN_CMD6_WIDTH `GC_XSDB_MSI_DATA_WIDTH
|
||||
|
||||
@@ -0,0 +1,107 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define values for Verilog instatiation of labtools ip
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_MFG_ID 0
|
||||
`define XILINX_MFG_ID 1
|
||||
`define XILINX_AND_AGILENT_MFG_ID 2
|
||||
`define GC_XILINX_MFG_ID `XILINX_MFG_ID
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_CORE_TYPE 0
|
||||
`define ICON_CORE_TYPE 1
|
||||
`define ILA_CORE_TYPE 2
|
||||
`define IBA_GENERIC_CORE_TYPE 3
|
||||
`define IBA_OPB_CORE_TYPE 4
|
||||
`define IBA_PLB_CORE_TYPE 5
|
||||
`define ILA_ATC_CORE_TYPE 6
|
||||
`define IBA_OPB_ATC_CORE_TYPE 7
|
||||
`define IBA_PLB_ATC_CORE_TYPE 8
|
||||
`define VIO_CORE_TYPE 9
|
||||
`define ATC2_CORE_TYPE 10
|
||||
`define ATC3_CORE_TYPE 11
|
||||
`define GC_RESERVED_CORE_TYPE2 12
|
||||
`define IBERT_CORE_TYPE 13
|
||||
`define GC_XSDB_MASTER_V1_0 14
|
||||
`define GC_ICON_NULL_CORE_TYPE 15
|
||||
|
||||
//
|
||||
// Width of the ChipScope Pro Core CONTROL port
|
||||
//
|
||||
`define CONTROL_WIDTH 36
|
||||
|
||||
// Match unit type
|
||||
`define MATCH_UNIT_TYPEA_ALLX 0
|
||||
//`define MATCH_UNIT_TYPE_GANDOR 2
|
||||
//`define MATCH_UNIT_TYPE_GANDORX 3
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Device family constants
|
||||
//
|
||||
`define FAMILY_NAME_LENGTH 15 //leave room for radhard/automotive and low power part names
|
||||
`define FAMILY_VIRTEX6 "virtex6"
|
||||
`define FAMILY_VIRTEX7 "virtex7"
|
||||
`define FAMILY_VIRTEX7_LENGTH 7
|
||||
`define FAMILY_KINTEX7 "kintex7"
|
||||
`define FAMILY_KINTEX7_LENGTH 7
|
||||
`define FAMILY_ARTIX7 "artix7"
|
||||
`define FAMILY_ARTIX7_LENGTH 6
|
||||
`define FAMILY_ZYNQ "zynq"
|
||||
`define FAMILY_ZYNQ_LENGTH 4
|
||||
|
||||
//
|
||||
// Architecture match type constants, start at 100 so that code can't incorrectly mix up family and match unit type
|
||||
//
|
||||
`define ARCH_MATCH_TYPE_A 100
|
||||
|
||||
//
|
||||
// Device JTAG Stuff
|
||||
//
|
||||
`define GC_SBT_IR_W 10;
|
||||
`define GC_SBT_IR_ID_INSTR 10'b1111001001
|
||||
`define GC_SBT_IR_USER1_INSTR 10'b11_1100_0010
|
||||
`define GC_CHIP_ID_CHIPSCOPE_SBT 32'b0000_1010_0000_0000_0011_0000_1001_0011
|
||||
// 0a00_3093
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Virtex7
|
||||
//
|
||||
// IR Info
|
||||
`define GC_V7_IR_W 6
|
||||
`define GC_V7_IR_ID_INSTR 6'b00_1001
|
||||
`define GC_V7_IR_USER1_INSTR 6'b00_0010
|
||||
`define GC_V7_IR_USER2_INSTR 6'b00_0011
|
||||
`define GC_V7_IR_USER3_INSTR 6'b10_0010
|
||||
`define GC_V7_IR_USER4_INSTR 6'b10_0011
|
||||
// Chip IDs
|
||||
`define GC_CHIP_ID_XC7V285T 32'b0000_0011_1010_0110_0100_0000_1001_0011
|
||||
// 0424a093
|
||||
|
||||
|
||||
@@ -0,0 +1,306 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
fBSLeFFl0UIhg6NZDTfu7ypZinWtFMVad2IjoPHu9PrVtpF4/iEXr2hclNyyVNtSK3rS9o808/xh
|
||||
evP8t1tgHgzJc3pTiFf0SCFxdYysUbHTzqb2Z0VVNXjG6ST6EQnS1fBhaPWANsocZE42WPKH4pGq
|
||||
UaD8nMt6HnNQKl7fxto=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
MzvL1RI48mMiPx2gD+ylGViLUm2JpiOsPJad/U8l6wZV6xJqCaUhbsCT8sXuqTEVwbfdYK7lGSGA
|
||||
plZkU3Sj1wlnVq+yGS5P6TJJ5Mm7GPgOnU5wRg5nZgPxSZGuLTXJHOGhfjhH/mghs3AlxNS7GmAw
|
||||
qbHfuT7p7pz9Oah2xfjLXaW7HvKd9N92D0qeoICr6xjLSOPHL8Ly+zaMWXZAWiLyLa//riF4XRv3
|
||||
N7K0SA53BIEuPfBcI9Czrf/6D6b2cKA9iGJOmxUeTZyuJ45SAxjkVHkB7CcUSmTr4UKfTvb9zACi
|
||||
Mtu8Wg6Q/3OVETaak2qbYD9zZwumSz5HBm03zw==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
dD3LMSW2XQlBMBTTRMwSXOa/RCG+OACGmaO+611u/OleDoum5VpmkxkWvR/TeLAPQ4wXRJaAc/PV
|
||||
WwCnpEMayBqjs9/L7J8noaf+DAM/987+jDKn42Q3SUEdxvG50/fSYnVeomOXb9J9WU1oj3wYWwT2
|
||||
K/pY3JWsKJg7il3eUhA=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
NNyiGV2bFhwQQaTXD/hUgqeVVtPXmF5bimKcAE1K5fYgWe3v/ohvwvbHKzJyBYjleCOHh7uhppzQ
|
||||
2MdP5iqFRBK77jDvMnDZ9Tqz+U3SR2pblq6YhxdY6Zc0I9CNZKTMg1PrHtcRm8e6HgoGuop7FQgr
|
||||
KevxWNszAVgF+yHmYjd6+zZ0T9jIgGvBEg5YpE1DcjfPvmaK0INQ/P/B47Pk+KaFUi5v5DXERY8h
|
||||
3tAhOQOj/RbNPan5ew8ENTlu5WxzC3NyEwtoNkLqji9d58n5B4dPG3qf4zJ3JjUPiThvGZHKsnop
|
||||
+hXSgUzBMxJ9crNwmvFJsQq1Y6awavFZJmm/LQ==
|
||||
|
||||
`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
U/vjLHyaDciMldHogERJWxUQ1cwvzDb/eeYwkJWlKW0/8/ErSJnXXqjRRA9fd5fBJMLUwA6FnN5A
|
||||
nWNCfY1GXtvgVMTEOqnYYlipg98l03QKGYORoU1cGdJ8y9BNfiF0chn4xAD49otAM4UXWF6mKsat
|
||||
8iV58/eSpV//gTN/V6kf+1ZhoBbZRcNmGyCGZ0KhthR8iOm6EmItNXMa+n2TnK5MyA6NaOnndema
|
||||
soyuLvVMRREeonlSJRUvX0DAggLT6lX8TYM6KoNaPqKOE8Ix1l4vQ4gcYKnMxXDr7mlmHKHwUbG7
|
||||
5AmbNufL4nSzQPn9U3thkrGAxzRFj7MNyr/Uxg==
|
||||
|
||||
`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
ECB5/2ZeTEb6P2U9faQYLdHquYo50rHrUiQGnMSiFUVo3CE+IMhTUnBoQ5MbsMTTvV+/vpWHa3/R
|
||||
j7RXAP6ebEYwxH1rc7se7u+C9JPEHkkqtUf5c8fAGrrTgFH9sX2yegDqCVVnRIlJUMEqphyRoZc8
|
||||
WUQbxiXDl8OzqDoV6oFx3KzxNYOO2MFeRSZ9qnTd7GJBJUPnvI/K+k0gtWojuKfU9r15mSTYkrwR
|
||||
TQcNVMnOW0p2RzW9zCAs0FZT/CYJeK3jUNcH+Hh2gWjufVZ+NB/eOVbAYNIEXduhBg/t6XciaWkB
|
||||
P+bpaXZ3CKcOtXU+DjLyI13M8BFtPQD0CRHKKw==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2022_10", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
wUJwzPBXQ7Yal7NTH2UzEraIeE9khcHISyeUMPFVTwDR4vYiF3ckZxAfoksF7Ct7rtGoFtGCWGhr
|
||||
FDnjBlnuyTVk9kU7tIzW+nfqiSF4kAPznjq4E7dZSRwZIPTDO7swLv2Ef+F1OfLjtOYUMLxZZfzB
|
||||
2hwYVUYuVyPO0ojtIjJdI9k4F2jlU3eB0qUVkbJuJm8NgyZCXKMUobnaMH8np6jLTG1sxP68EiDW
|
||||
2HRiycXorMu8HBioOX7ihCO3FNmdT2corKVjGNJ/S2AGkC+j8E1p0WI5ovZSWJOjbvA+rsHAdqAf
|
||||
EWEg+xzp8et2lSys5iJ9qxzK/t/M6Nz22Qjwog==
|
||||
|
||||
`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`pragma protect key_block
|
||||
XKuLPDu2Sna+99vSkwOlXk5wVQ8rXEakmNmlTzc2i4lI3bkhJ0PYuAMO7noI4LqVqU4m7AiMXh0f
|
||||
y4OwjMjsUfLfkDzbEfSy1QJulNHWjPdGx6jXqwBK3P0zhZQcGYcBrWJ8yocMMPZvbJIErFtKUOcf
|
||||
zQwp5GQoPokTptPUZ8eafvi4KUxFMFb0uIrmrhs9Adwhtllwtk2RJRDFJ/kpUunyfKjel8RXMDLw
|
||||
wNboQJpIxdDhm9XgEgX62woedKuwvEhS/59CLrscqKM0F6hBBlI7gZfkkQlokcN0G6susykZdRw8
|
||||
lcZiKtBiETCbWUh/jmxThK/fr4+hmQ/ENCzUx2ypMcNbfU5n0l4+zyXFvNIK1fL9U5EO4w5YsIS3
|
||||
q9cXQUaUndYeGnEaO3rSgAWt6gNyOXBN9dbTOr6BXb5CtPqjTronBDqidnETS3XsymEub2lw3fcg
|
||||
MnuxCLUz3oTahFu4+M2pylRrWEJiD/MD8h0L030+O4f2qVGfEOoZ0POw
|
||||
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
WjyQLOg5wK6cekU23+JoX6YPd2aa6aEyPnJ0CizxS5391+IhI2aCDB+mqjCZCCmDQmHYDs45HoT3
|
||||
BW1GhBA1gMVvX3JpIaCmoje2Qbu1BbKJfnuvdvg+yDPRmpVSj5cRcMMICIigl18KKNCWnzkP6I1S
|
||||
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|
||||
ZERRqV2IEQiMv58pknr2bwlZllYTk4CnWHHAXKOkSyriZH1cBT0N2G7YgSa4Gp6qJHZaDGPuzNKU
|
||||
afjRNaIkY7GY9Jfvf38DCYTmAR+Mv+j12JdN3w==
|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
|
||||
`pragma protect data_block
|
||||
0XFi6v65kwH2rIOng3NuAFuxA+e5PCjXoqLWEFf+sYRd/EHRK/HJbfrZaaaid65gnhjQYv1wl+/K
|
||||
KzLr35cYzya9ORpKy2iS0GuAZf2L/bV9i1XREuFYuswdVQyZQY+sSgg6pHKy06S8cfktw1cBmnXT
|
||||
oygdcbHFFFpSMueczEJTSaQqMBf9Kx08xb3KkgEdHFZaMd1EdC64Qlrxv85UJut7cBhGMCHfVVag
|
||||
5NSe9G2T/2ByZ+F63hxlRwBDKwaGVNn8kOP4OuDriARZhcMzlkXV1Bpm9kgVMqCzS6KsNU6LeIDn
|
||||
GU7fNrjozfhxpiR8OVHPS3KNYWbPUiX691COEy6Hxz8X4TcpKFGnJsN+1dJN2KVMrJunlomvCvOj
|
||||
eUTUEXLD4FuANSBXwX9m+0L3mHiysMOiG8wnn9Aw2SDnrZdLh6DYO8q4cUoB7ZODWDaOxPEYFNCm
|
||||
8EhkrNQJr2t209mtJJwp7xGNIOGCHtlkWx+apnpu8E08q5mEYzc582C2uQr7tGC3XSkUP7yo7UGI
|
||||
K+QXlwgKM4X123hwYWHD5WzlcDUhjdioZpmzl+AQJwWhXaJEKZl78o/mq1HVV8X0+/Ld8ic1Il/T
|
||||
60StZr82OfcPeMKDK/uUa/3/tKnx5yjaGkY6b9Pvb9C3DHhQlK3L6B/i0+eJF2ctAYqczE0PaX+5
|
||||
g+U7F1jOibGAxYpNEWDV3CiuZivb1F7n8sczCoF25umB/XnhgEfUb4Psjq2WFPhsRVI5C/gbplaX
|
||||
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|
||||
St6qXncV9vXo68kGVriPLOSEnpww6dXYQuGi2Q0xvqrlLrxPeA0Bh5P7k50eJD5iI289WUGXoKdi
|
||||
OKemdkjuN2B+JwG61q+0YrFkC8moaibEocZYfgDcZTtHOxMOC9lKQpIcK3JsURgJ8NY74ihSOq3c
|
||||
PwBc6ozG+JiKgNXNpHIfIy4BUwvJTGStS9iyDeX+YbBx8b5VWv1sxgjCk0jLR5/M7MH2Qc1pRqf/
|
||||
eqaEcPurVyLbvG2c26//HMKOm4i6AfQ7nJv5jB/fs+16ob7lPP0gPOSsaFw8wLsWRFa/7SbibBP5
|
||||
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|
||||
nhoDiHw0QcUPxDkXhx2VjisqptR20lkL+iPWtlQ8ld1v88bx17KNAqWx/LGObQeuojp2B8tuQX+9
|
||||
JYoeBq5JFM37Pdb/Fh15bjLzHD9+W8eNFoihB1x/7K8ALtoB0KOf7Or6oDZIoMyBKMcpMwWSaB/m
|
||||
FcpBj9rJRdk1MagZeJBY4k5Qdc0RQ+wltJnn2wPKYj4SMJdszImoo8luOjSW1h/f6hTE4thAFtfu
|
||||
swHsUE9BQ/sTd+dZOaon2AV3NQjRCSw3cUEj9zP8PgW8SaYNUwoQLmA/jmeKnJDJgLdQBXK3FnBk
|
||||
Z2iHMYbIsC04S+twWgGcuXB5OONj9TA9dnfl3WBYYe5rnxfuZGMVNywp10Jo3sndy5EC51uDfo7o
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
4bqRpCY3luCbVnoHWdAyjskgLcwBSyF8J0EPZ5BGylZcOTU60/0=
|
||||
`pragma protect end_protected
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,552 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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||||
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|
||||
eehGCOlFNzztUpCCBuo=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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||||
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||||
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||||
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|
||||
Lzp5Bj6tb7kmD+A/qe86yLb4GbJzLTehOjcfdg==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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||||
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|
||||
v0IjKU+PjNN3ZYIXCkA=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
IHl8aYzdxpc89jXiMIYfoqN06f8LwbIAKe3Z+w==
|
||||
|
||||
`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
mywjCvcVbMSrJkkJ6lHrazZzzBU8tJ9SXhvc1A==
|
||||
|
||||
`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
r20FpLJcMjFy8H4kZ7SMF51dIlCCySUMitZhBw==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2022_10", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
ahGj9cu5vw+TGhDRETTpUmguNUrGkzj4c4HpfbBQWexaOi1CnxDewq4mIuyo2pPRt9bsxMyxinAi
|
||||
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|
||||
kg96Xfcnb3hsRdNnyl3s8r1r/GO6lcYCfWw2HtuVB73JqZOdMK5WQnRs2nCzyarDak52q8w92CuR
|
||||
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|
||||
2COb8mAkB/0fC26SxfxSy30x8trX0jLDnfntAQ==
|
||||
|
||||
`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0Zjf5PrRbObEBaQt8a9CnelDkWVdP3uTr1rSFz+syFbYPJ/3XU2G/yLmk16QYP9kCQo9CAcIjwxh
|
||||
g41o91RxGZj8PwCpcnZrAoW7se6+/H5h2JrNvoOz8Yr09ZkOhWM0r75h8Rx3OyutUqeqr3BQ1b9B
|
||||
lvB/+l6p6intfTshH8BsTtE0j292jiNGV5cvexC4cczkPuzrIeMxa/xJ
|
||||
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Synplicity", key_keyname = "SYNP15_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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||||
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||||
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||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-PREC-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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||||
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||||
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||||
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|
||||
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|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25472)
|
||||
`pragma protect data_block
|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
`pragma protect end_protected
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -0,0 +1,67 @@
|
||||
# file: vio_cur_flt_state.xdc
|
||||
#////////////////////////////////////////////////////////////////////////////
|
||||
#/$Date: 2012/02/06 10:34:16 $
|
||||
#/$RCSfile: $
|
||||
#/$Revision: 1.2 $
|
||||
#//////////////////////////////////////////////////////////////////////////////
|
||||
#/ ____ ____
|
||||
#/ / /\/ /
|
||||
#/ /___/ \ / Vendor: Xilinx
|
||||
#/ \ \ \/ Version : 2.00
|
||||
#/ \ \ Application : VIO V2.00a
|
||||
#/ / / Filename : vio_cur_flt_state.xdc
|
||||
#/ /___/ /\
|
||||
#/ \ \ / \
|
||||
#/ \___\/\___\
|
||||
#/
|
||||
#/ (c) Copyright 2010 Xilinx, Inc. All rights reserved.
|
||||
#/
|
||||
#/ This file contains confidential and proprietary information
|
||||
#/ of Xilinx, Inc. and is protected under U.S. and
|
||||
#/ international copyright and other intellectual property
|
||||
#/ laws.
|
||||
#/
|
||||
#/ DISCLAIMER
|
||||
#/ This disclaimer is not a license and does not grant any
|
||||
#/ rights to the materials distributed herewith. Except as
|
||||
#/ otherwise provided in a valid license issued to you by
|
||||
#/ Xilinx, and to the maximum extent permitted by applicable
|
||||
#/ law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
#/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
#/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
#/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
#/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
#/ (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
#/ including negligence, or under any other theory of
|
||||
#/ liability) for any loss or damage of any kind or nature
|
||||
#/ related to, arising under or in connection with these
|
||||
#/ materials, including for any direct, or any indirect,
|
||||
#/ special, incidental, or consequential loss or damage
|
||||
#/ (including loss of data, profits, goodwill, or any type of
|
||||
#/ loss or damage suffered as a result of any action brought
|
||||
#/ by a third party) even if such damage or loss was
|
||||
#/ reasonably foreseeable or Xilinx had been advised of the
|
||||
#/ possibility of the same.
|
||||
#/
|
||||
#/ CRITICAL APPLICATIONS
|
||||
#/ Xilinx products are not designed or intended to be fail-
|
||||
#/ safe, or for use in any application requiring fail-safe
|
||||
#/ performance, such as life-support or safety devices or
|
||||
#/ systems, Class III medical devices, nuclear facilities,
|
||||
#/ applications related to the deployment of airbags, or any
|
||||
#/ other applications that could lead to death, personal
|
||||
#/ injury, or severe property or environmental damage
|
||||
#/ (individually and collectively, "Critical
|
||||
#/ Applications"). Customer assumes the sole risk and
|
||||
#/ liability of any use of Xilinx products in Critical
|
||||
#/ Applications, subject only to applicable laws and
|
||||
#/ regulations governing limitations on product liability.
|
||||
#/
|
||||
#/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
#/ PART OF THIS FILE AT ALL TIMES.
|
||||
#Created by Constraints Editor
|
||||
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*Hold_probe_in*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*PROBE_IN_INST/probe_in_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*PROBE_IN_INST/probe_in_reg*" && IS_SEQUENTIAL} ] -to [get_cells -hierarchical -filter { NAME =~ "*data_int_sync1*" && IS_SEQUENTIAL } ]
|
||||
create_waiver -type CDC -id CDC-4 -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter {NAME =~ "*probe_in_reg_reg*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*data_int_sync1_reg*"}]] -user "vio" -description {The path has combinational circuit. But from hardware prospective the design works perfectly and the signals crossing happen after a very long time from the source has the value.} -tags "1050886" -scope -internal
|
||||
create_waiver -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*Hold_probe_in*" && IS_SEQUENTIAL } ]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter { NAME =~ "*PROBE_IN_INST/probe_in_reg*" && IS_SEQUENTIAL} ]] -user "vio" -description {The path has combinational circuit. But from hardware prospective the design works perfectly and the signals crossing happen after a very long time from the source has the value.} -tags "1050886" -scope -internal
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 10 -name clk [get_ports clk]
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jun 24 13:53:39 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.v
|
||||
// Design : vio_cur_flt_state
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2023.1" *)
|
||||
module vio_cur_flt_state(clk, probe_in0, probe_in1, probe_in2)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe_in0[0:0],probe_in1[31:0],probe_in2[63:0]" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [0:0]probe_in0;
|
||||
input [31:0]probe_in1;
|
||||
input [63:0]probe_in2;
|
||||
endmodule
|
||||
@@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jun 24 13:53:39 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_stub.vhdl
|
||||
-- Design : vio_cur_flt_state
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_cur_flt_state is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in2 : in STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
|
||||
end vio_cur_flt_state;
|
||||
|
||||
architecture stub of vio_cur_flt_state is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[31:0],probe_in2[63:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
Reference in New Issue
Block a user