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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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||||
// Date : Tue Oct 28 21:01:41 2025
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||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_ZCHECK_SPI_0_stub.v
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// Design : design_a9_1_ZCHECK_SPI_0
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z020clg400-2
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||||
// --------------------------------------------------------------------------------
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||||
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||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "axi_quad_spi,Vivado 2023.1" *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(ext_spi_clk, s_axi_aclk, s_axi_aresetn,
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s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
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s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
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||||
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, io0_i, io0_o, io0_t, io1_i,
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io1_o, io1_t, sck_i, sck_o, sck_t, ss_i, ss_o, ss_t, ip2intc_irpt)
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/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt" */
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/* synthesis syn_force_seq_prim="ext_spi_clk" */
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/* synthesis syn_force_seq_prim="s_axi_aclk" */;
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input ext_spi_clk /* synthesis syn_isclock = 1 */;
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input s_axi_aclk /* synthesis syn_isclock = 1 */;
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input s_axi_aresetn;
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input [6:0]s_axi_awaddr;
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input s_axi_awvalid;
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output s_axi_awready;
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||||
input [31:0]s_axi_wdata;
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input [3:0]s_axi_wstrb;
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||||
input s_axi_wvalid;
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output s_axi_wready;
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output [1:0]s_axi_bresp;
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output s_axi_bvalid;
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input s_axi_bready;
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input [6:0]s_axi_araddr;
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input s_axi_arvalid;
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output s_axi_arready;
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output [31:0]s_axi_rdata;
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output [1:0]s_axi_rresp;
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||||
output s_axi_rvalid;
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input s_axi_rready;
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input io0_i;
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output io0_o;
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output io0_t;
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||||
input io1_i;
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output io1_o;
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||||
output io1_t;
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||||
input sck_i;
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output sck_o;
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||||
output sck_t;
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input [0:0]ss_i;
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output [0:0]ss_o;
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output ss_t;
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output ip2intc_irpt;
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endmodule
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||||
@@ -0,0 +1,63 @@
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||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Oct 28 21:01:41 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_ZCHECK_SPI_0_stub.vhdl
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||||
-- Design : design_a9_1_ZCHECK_SPI_0
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||||
-- Purpose : Stub declaration of top-level module interface
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||||
-- Device : xc7z020clg400-2
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||||
-- --------------------------------------------------------------------------------
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||||
library IEEE;
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||||
use IEEE.STD_LOGIC_1164.ALL;
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||||
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||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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||||
Port (
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||||
ext_spi_clk : in STD_LOGIC;
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||||
s_axi_aclk : in STD_LOGIC;
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||||
s_axi_aresetn : in STD_LOGIC;
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||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
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||||
s_axi_awvalid : in STD_LOGIC;
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||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
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||||
s_axi_wready : out STD_LOGIC;
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||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
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||||
s_axi_bvalid : out STD_LOGIC;
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||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
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||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
io0_i : in STD_LOGIC;
|
||||
io0_o : out STD_LOGIC;
|
||||
io0_t : out STD_LOGIC;
|
||||
io1_i : in STD_LOGIC;
|
||||
io1_o : out STD_LOGIC;
|
||||
io1_t : out STD_LOGIC;
|
||||
sck_i : in STD_LOGIC;
|
||||
sck_o : out STD_LOGIC;
|
||||
sck_t : out STD_LOGIC;
|
||||
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ss_t : out STD_LOGIC;
|
||||
ip2intc_irpt : out STD_LOGIC
|
||||
);
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||||
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||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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||||
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||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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||||
attribute syn_black_box : boolean;
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||||
attribute black_box_pad_pin : string;
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||||
attribute syn_black_box of stub : architecture is true;
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||||
attribute black_box_pad_pin of stub : architecture is "ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt";
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||||
attribute x_core_info : string;
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||||
attribute x_core_info of stub : architecture is "axi_quad_spi,Vivado 2023.1";
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||||
begin
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||||
end;
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||||
@@ -0,0 +1,2 @@
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||||
NumberHits:2
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||||
Timestamp: Tue Oct 28 13:02:03 UTC 2025
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||||
@@ -0,0 +1,140 @@
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.MAX_BURST_LENGTH">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_OUTSTANDING">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.READ_WRITE_MODE">READ_ONLY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.HAS_CACHE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.MAX_BURST_LENGTH">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.NUM_WRITE_OUTSTANDING">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.READ_WRITE_MODE">WRITE_ONLY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S01_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADVANCED_PROPERTIES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_smartconnect_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_CLKS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_MI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_SI">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEELABORATESCRC">580d1a4f</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">d70b13f52cdee599</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">design_a9_1_smartconnect_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">9a15d5e9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">225</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
+76194
File diff suppressed because one or more lines are too long
+90264
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,102 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Oct 28 21:03:11 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_smartconnect_0_0_stub.v
|
||||
// Design : design_a9_1_smartconnect_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "bd_962a,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, S00_AXI_araddr, S00_AXI_arlen,
|
||||
S00_AXI_arsize, S00_AXI_arburst, S00_AXI_arlock, S00_AXI_arcache, S00_AXI_arprot,
|
||||
S00_AXI_arqos, S00_AXI_arvalid, S00_AXI_arready, S00_AXI_rdata, S00_AXI_rresp,
|
||||
S00_AXI_rlast, S00_AXI_rvalid, S00_AXI_rready, S01_AXI_awaddr, S01_AXI_awlen,
|
||||
S01_AXI_awsize, S01_AXI_awburst, S01_AXI_awlock, S01_AXI_awcache, S01_AXI_awprot,
|
||||
S01_AXI_awqos, S01_AXI_awvalid, S01_AXI_awready, S01_AXI_wdata, S01_AXI_wstrb,
|
||||
S01_AXI_wlast, S01_AXI_wvalid, S01_AXI_wready, S01_AXI_bresp, S01_AXI_bvalid,
|
||||
S01_AXI_bready, M00_AXI_awaddr, M00_AXI_awlen, M00_AXI_awsize, M00_AXI_awburst,
|
||||
M00_AXI_awlock, M00_AXI_awcache, M00_AXI_awprot, M00_AXI_awqos, M00_AXI_awvalid,
|
||||
M00_AXI_awready, M00_AXI_wdata, M00_AXI_wstrb, M00_AXI_wlast, M00_AXI_wvalid,
|
||||
M00_AXI_wready, M00_AXI_bresp, M00_AXI_bvalid, M00_AXI_bready, M00_AXI_araddr,
|
||||
M00_AXI_arlen, M00_AXI_arsize, M00_AXI_arburst, M00_AXI_arlock, M00_AXI_arcache,
|
||||
M00_AXI_arprot, M00_AXI_arqos, M00_AXI_arvalid, M00_AXI_arready, M00_AXI_rdata,
|
||||
M00_AXI_rresp, M00_AXI_rlast, M00_AXI_rvalid, M00_AXI_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aresetn,S00_AXI_araddr[31:0],S00_AXI_arlen[7:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[0:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rdata[31:0],S00_AXI_rresp[1:0],S00_AXI_rlast,S00_AXI_rvalid,S00_AXI_rready,S01_AXI_awaddr[31:0],S01_AXI_awlen[7:0],S01_AXI_awsize[2:0],S01_AXI_awburst[1:0],S01_AXI_awlock[0:0],S01_AXI_awcache[3:0],S01_AXI_awprot[2:0],S01_AXI_awqos[3:0],S01_AXI_awvalid,S01_AXI_awready,S01_AXI_wdata[31:0],S01_AXI_wstrb[3:0],S01_AXI_wlast,S01_AXI_wvalid,S01_AXI_wready,S01_AXI_bresp[1:0],S01_AXI_bvalid,S01_AXI_bready,M00_AXI_awaddr[31:0],M00_AXI_awlen[3:0],M00_AXI_awsize[2:0],M00_AXI_awburst[1:0],M00_AXI_awlock[1:0],M00_AXI_awcache[3:0],M00_AXI_awprot[2:0],M00_AXI_awqos[3:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wlast,M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[31:0],M00_AXI_arlen[3:0],M00_AXI_arsize[2:0],M00_AXI_arburst[1:0],M00_AXI_arlock[1:0],M00_AXI_arcache[3:0],M00_AXI_arprot[2:0],M00_AXI_arqos[3:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rlast,M00_AXI_rvalid,M00_AXI_rready" */
|
||||
/* synthesis syn_force_seq_prim="aclk" */;
|
||||
input aclk /* synthesis syn_isclock = 1 */;
|
||||
input aresetn;
|
||||
input [31:0]S00_AXI_araddr;
|
||||
input [7:0]S00_AXI_arlen;
|
||||
input [2:0]S00_AXI_arsize;
|
||||
input [1:0]S00_AXI_arburst;
|
||||
input [0:0]S00_AXI_arlock;
|
||||
input [3:0]S00_AXI_arcache;
|
||||
input [2:0]S00_AXI_arprot;
|
||||
input [3:0]S00_AXI_arqos;
|
||||
input S00_AXI_arvalid;
|
||||
output S00_AXI_arready;
|
||||
output [31:0]S00_AXI_rdata;
|
||||
output [1:0]S00_AXI_rresp;
|
||||
output S00_AXI_rlast;
|
||||
output S00_AXI_rvalid;
|
||||
input S00_AXI_rready;
|
||||
input [31:0]S01_AXI_awaddr;
|
||||
input [7:0]S01_AXI_awlen;
|
||||
input [2:0]S01_AXI_awsize;
|
||||
input [1:0]S01_AXI_awburst;
|
||||
input [0:0]S01_AXI_awlock;
|
||||
input [3:0]S01_AXI_awcache;
|
||||
input [2:0]S01_AXI_awprot;
|
||||
input [3:0]S01_AXI_awqos;
|
||||
input S01_AXI_awvalid;
|
||||
output S01_AXI_awready;
|
||||
input [31:0]S01_AXI_wdata;
|
||||
input [3:0]S01_AXI_wstrb;
|
||||
input S01_AXI_wlast;
|
||||
input S01_AXI_wvalid;
|
||||
output S01_AXI_wready;
|
||||
output [1:0]S01_AXI_bresp;
|
||||
output S01_AXI_bvalid;
|
||||
input S01_AXI_bready;
|
||||
output [31:0]M00_AXI_awaddr;
|
||||
output [3:0]M00_AXI_awlen;
|
||||
output [2:0]M00_AXI_awsize;
|
||||
output [1:0]M00_AXI_awburst;
|
||||
output [1:0]M00_AXI_awlock;
|
||||
output [3:0]M00_AXI_awcache;
|
||||
output [2:0]M00_AXI_awprot;
|
||||
output [3:0]M00_AXI_awqos;
|
||||
output M00_AXI_awvalid;
|
||||
input M00_AXI_awready;
|
||||
output [31:0]M00_AXI_wdata;
|
||||
output [3:0]M00_AXI_wstrb;
|
||||
output M00_AXI_wlast;
|
||||
output M00_AXI_wvalid;
|
||||
input M00_AXI_wready;
|
||||
input [1:0]M00_AXI_bresp;
|
||||
input M00_AXI_bvalid;
|
||||
output M00_AXI_bready;
|
||||
output [31:0]M00_AXI_araddr;
|
||||
output [3:0]M00_AXI_arlen;
|
||||
output [2:0]M00_AXI_arsize;
|
||||
output [1:0]M00_AXI_arburst;
|
||||
output [1:0]M00_AXI_arlock;
|
||||
output [3:0]M00_AXI_arcache;
|
||||
output [2:0]M00_AXI_arprot;
|
||||
output [3:0]M00_AXI_arqos;
|
||||
output M00_AXI_arvalid;
|
||||
input M00_AXI_arready;
|
||||
input [31:0]M00_AXI_rdata;
|
||||
input [1:0]M00_AXI_rresp;
|
||||
input M00_AXI_rlast;
|
||||
input M00_AXI_rvalid;
|
||||
output M00_AXI_rready;
|
||||
endmodule
|
||||
@@ -0,0 +1,98 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Oct 28 21:03:11 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_smartconnect_0_0_stub.vhdl
|
||||
-- Design : design_a9_1_smartconnect_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_arvalid : in STD_LOGIC;
|
||||
S00_AXI_arready : out STD_LOGIC;
|
||||
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_rlast : out STD_LOGIC;
|
||||
S00_AXI_rvalid : out STD_LOGIC;
|
||||
S00_AXI_rready : in STD_LOGIC;
|
||||
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S01_AXI_awvalid : in STD_LOGIC;
|
||||
S01_AXI_awready : out STD_LOGIC;
|
||||
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S01_AXI_wlast : in STD_LOGIC;
|
||||
S01_AXI_wvalid : in STD_LOGIC;
|
||||
S01_AXI_wready : out STD_LOGIC;
|
||||
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S01_AXI_bvalid : out STD_LOGIC;
|
||||
S01_AXI_bready : in STD_LOGIC;
|
||||
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_awvalid : out STD_LOGIC;
|
||||
M00_AXI_awready : in STD_LOGIC;
|
||||
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_wlast : out STD_LOGIC;
|
||||
M00_AXI_wvalid : out STD_LOGIC;
|
||||
M00_AXI_wready : in STD_LOGIC;
|
||||
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_bvalid : in STD_LOGIC;
|
||||
M00_AXI_bready : out STD_LOGIC;
|
||||
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_arvalid : out STD_LOGIC;
|
||||
M00_AXI_arready : in STD_LOGIC;
|
||||
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_rlast : in STD_LOGIC;
|
||||
M00_AXI_rvalid : in STD_LOGIC;
|
||||
M00_AXI_rready : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,S00_AXI_araddr[31:0],S00_AXI_arlen[7:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[0:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rdata[31:0],S00_AXI_rresp[1:0],S00_AXI_rlast,S00_AXI_rvalid,S00_AXI_rready,S01_AXI_awaddr[31:0],S01_AXI_awlen[7:0],S01_AXI_awsize[2:0],S01_AXI_awburst[1:0],S01_AXI_awlock[0:0],S01_AXI_awcache[3:0],S01_AXI_awprot[2:0],S01_AXI_awqos[3:0],S01_AXI_awvalid,S01_AXI_awready,S01_AXI_wdata[31:0],S01_AXI_wstrb[3:0],S01_AXI_wlast,S01_AXI_wvalid,S01_AXI_wready,S01_AXI_bresp[1:0],S01_AXI_bvalid,S01_AXI_bready,M00_AXI_awaddr[31:0],M00_AXI_awlen[3:0],M00_AXI_awsize[2:0],M00_AXI_awburst[1:0],M00_AXI_awlock[1:0],M00_AXI_awcache[3:0],M00_AXI_awprot[2:0],M00_AXI_awqos[3:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wlast,M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[31:0],M00_AXI_arlen[3:0],M00_AXI_arsize[2:0],M00_AXI_arburst[1:0],M00_AXI_arlock[1:0],M00_AXI_arcache[3:0],M00_AXI_arprot[2:0],M00_AXI_arqos[3:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rlast,M00_AXI_rvalid,M00_AXI_rready";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "bd_962a,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:2
|
||||
Timestamp: Wed Oct 29 05:47:57 UTC 2025
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@@ -0,0 +1,92 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Aug 31 11:19:05 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
|
||||
// Design : u_ila_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
|
||||
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
|
||||
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
|
||||
probe51, probe52, probe53, probe54, probe55, probe56, probe57, probe58, probe59, probe60, probe61,
|
||||
probe62, probe63)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[31:0],probe1[12:0],probe2[3:0],probe3[7:0],probe4[15:0],probe5[15:0],probe6[7:0],probe7[8:0],probe8[15:0],probe9[1:0],probe10[7:0],probe11[15:0],probe12[15:0],probe13[7:0],probe14[15:0],probe15[7:0],probe16[7:0],probe17[8:0],probe18[7:0],probe19[31:0],probe20[1:0],probe21[7:0],probe22[31:0],probe23[0:0],probe24[31:0],probe25[7:0],probe26[7:0],probe27[15:0],probe28[15:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [31:0]probe0;
|
||||
input [12:0]probe1;
|
||||
input [3:0]probe2;
|
||||
input [7:0]probe3;
|
||||
input [15:0]probe4;
|
||||
input [15:0]probe5;
|
||||
input [7:0]probe6;
|
||||
input [8:0]probe7;
|
||||
input [15:0]probe8;
|
||||
input [1:0]probe9;
|
||||
input [7:0]probe10;
|
||||
input [15:0]probe11;
|
||||
input [15:0]probe12;
|
||||
input [7:0]probe13;
|
||||
input [15:0]probe14;
|
||||
input [7:0]probe15;
|
||||
input [7:0]probe16;
|
||||
input [8:0]probe17;
|
||||
input [7:0]probe18;
|
||||
input [31:0]probe19;
|
||||
input [1:0]probe20;
|
||||
input [7:0]probe21;
|
||||
input [31:0]probe22;
|
||||
input [0:0]probe23;
|
||||
input [31:0]probe24;
|
||||
input [7:0]probe25;
|
||||
input [7:0]probe26;
|
||||
input [15:0]probe27;
|
||||
input [15:0]probe28;
|
||||
input [0:0]probe29;
|
||||
input [0:0]probe30;
|
||||
input [0:0]probe31;
|
||||
input [0:0]probe32;
|
||||
input [0:0]probe33;
|
||||
input [0:0]probe34;
|
||||
input [0:0]probe35;
|
||||
input [0:0]probe36;
|
||||
input [0:0]probe37;
|
||||
input [0:0]probe38;
|
||||
input [0:0]probe39;
|
||||
input [0:0]probe40;
|
||||
input [0:0]probe41;
|
||||
input [0:0]probe42;
|
||||
input [0:0]probe43;
|
||||
input [0:0]probe44;
|
||||
input [0:0]probe45;
|
||||
input [0:0]probe46;
|
||||
input [0:0]probe47;
|
||||
input [0:0]probe48;
|
||||
input [0:0]probe49;
|
||||
input [0:0]probe50;
|
||||
input [0:0]probe51;
|
||||
input [0:0]probe52;
|
||||
input [0:0]probe53;
|
||||
input [0:0]probe54;
|
||||
input [0:0]probe55;
|
||||
input [0:0]probe56;
|
||||
input [0:0]probe57;
|
||||
input [0:0]probe58;
|
||||
input [0:0]probe59;
|
||||
input [0:0]probe60;
|
||||
input [0:0]probe61;
|
||||
input [0:0]probe62;
|
||||
input [0:0]probe63;
|
||||
endmodule
|
||||
@@ -0,0 +1,95 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Aug 31 11:19:05 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
|
||||
-- Design : u_ila_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe55 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe56 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe57 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe58 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe59 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe60 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe61 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe62 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe63 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[31:0],probe1[12:0],probe2[3:0],probe3[7:0],probe4[15:0],probe5[15:0],probe6[7:0],probe7[8:0],probe8[15:0],probe9[1:0],probe10[7:0],probe11[15:0],probe12[15:0],probe13[7:0],probe14[15:0],probe15[7:0],probe16[7:0],probe17[8:0],probe18[7:0],probe19[31:0],probe20[1:0],probe21[7:0],probe22[31:0],probe23[0:0],probe24[31:0],probe25[7:0],probe26[7:0],probe27[15:0],probe28[15:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@@ -0,0 +1,95 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jan 28 11:50:10 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
|
||||
// Design : u_ila_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
|
||||
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
|
||||
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
|
||||
probe51, probe52, probe53, probe54, probe55, probe56, probe57, probe58, probe59, probe60, probe61,
|
||||
probe62, probe63, probe64, probe65, probe66)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[1:0],probe1[15:0],probe2[15:0],probe3[0:0],probe4[7:0],probe5[7:0],probe6[7:0],probe7[31:0],probe8[31:0],probe9[31:0],probe10[31:0],probe11[15:0],probe12[7:0],probe13[15:0],probe14[7:0],probe15[15:0],probe16[8:0],probe17[7:0],probe18[7:0],probe19[7:0],probe20[8:0],probe21[15:0],probe22[31:0],probe23[12:0],probe24[3:0],probe25[3:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0],probe64[0:0],probe65[0:0],probe66[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [1:0]probe0;
|
||||
input [15:0]probe1;
|
||||
input [15:0]probe2;
|
||||
input [0:0]probe3;
|
||||
input [7:0]probe4;
|
||||
input [7:0]probe5;
|
||||
input [7:0]probe6;
|
||||
input [31:0]probe7;
|
||||
input [31:0]probe8;
|
||||
input [31:0]probe9;
|
||||
input [31:0]probe10;
|
||||
input [15:0]probe11;
|
||||
input [7:0]probe12;
|
||||
input [15:0]probe13;
|
||||
input [7:0]probe14;
|
||||
input [15:0]probe15;
|
||||
input [8:0]probe16;
|
||||
input [7:0]probe17;
|
||||
input [7:0]probe18;
|
||||
input [7:0]probe19;
|
||||
input [8:0]probe20;
|
||||
input [15:0]probe21;
|
||||
input [31:0]probe22;
|
||||
input [12:0]probe23;
|
||||
input [3:0]probe24;
|
||||
input [3:0]probe25;
|
||||
input [0:0]probe26;
|
||||
input [0:0]probe27;
|
||||
input [0:0]probe28;
|
||||
input [0:0]probe29;
|
||||
input [0:0]probe30;
|
||||
input [0:0]probe31;
|
||||
input [0:0]probe32;
|
||||
input [0:0]probe33;
|
||||
input [0:0]probe34;
|
||||
input [0:0]probe35;
|
||||
input [0:0]probe36;
|
||||
input [0:0]probe37;
|
||||
input [0:0]probe38;
|
||||
input [0:0]probe39;
|
||||
input [0:0]probe40;
|
||||
input [0:0]probe41;
|
||||
input [0:0]probe42;
|
||||
input [0:0]probe43;
|
||||
input [0:0]probe44;
|
||||
input [0:0]probe45;
|
||||
input [0:0]probe46;
|
||||
input [0:0]probe47;
|
||||
input [0:0]probe48;
|
||||
input [0:0]probe49;
|
||||
input [0:0]probe50;
|
||||
input [0:0]probe51;
|
||||
input [0:0]probe52;
|
||||
input [0:0]probe53;
|
||||
input [0:0]probe54;
|
||||
input [0:0]probe55;
|
||||
input [0:0]probe56;
|
||||
input [0:0]probe57;
|
||||
input [0:0]probe58;
|
||||
input [0:0]probe59;
|
||||
input [0:0]probe60;
|
||||
input [0:0]probe61;
|
||||
input [0:0]probe62;
|
||||
input [0:0]probe63;
|
||||
input [0:0]probe64;
|
||||
input [0:0]probe65;
|
||||
input [0:0]probe66;
|
||||
endmodule
|
||||
@@ -0,0 +1,98 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jan 28 11:50:10 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
|
||||
-- Design : u_ila_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe55 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe56 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe57 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe58 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe59 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe60 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe61 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe62 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe63 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe64 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe65 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe66 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[1:0],probe1[15:0],probe2[15:0],probe3[0:0],probe4[7:0],probe5[7:0],probe6[7:0],probe7[31:0],probe8[31:0],probe9[31:0],probe10[31:0],probe11[15:0],probe12[7:0],probe13[15:0],probe14[7:0],probe15[15:0],probe16[8:0],probe17[7:0],probe18[7:0],probe19[7:0],probe20[8:0],probe21[15:0],probe22[31:0],probe23[12:0],probe24[3:0],probe25[3:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0],probe64[0:0],probe65[0:0],probe66[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,53 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>dbb1f0b16391a9be</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_a9_1_axi_gpio_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_gpio" spirit:version="2.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS_2">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO2_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTERRUPT_PRESENT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IS_DUAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_axi_gpio_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">dbb1f0b16391a9be</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">6d038ed3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">99</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">30</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
+5970
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,46 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Oct 28 21:01:08 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_gpio_0_0_stub.v
|
||||
// Design : design_a9_1_axi_gpio_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_gpio,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i, gpio2_io_o)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[7:0],gpio2_io_o[31:0]" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [8:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [8:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output ip2intc_irpt;
|
||||
input [7:0]gpio_io_i;
|
||||
output [31:0]gpio2_io_o;
|
||||
endmodule
|
||||
@@ -0,0 +1,52 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Oct 28 21:01:08 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_gpio_0_0_stub.vhdl
|
||||
-- Design : design_a9_1_axi_gpio_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
ip2intc_irpt : out STD_LOGIC;
|
||||
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[7:0],gpio2_io_o[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:1
|
||||
Timestamp: Tue Nov 25 12:16:20 UTC 2025
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@@ -0,0 +1,82 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Nov 25 11:43:06 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
|
||||
// Design : u_ila_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
|
||||
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
|
||||
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
|
||||
probe51, probe52, probe53, probe54)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[7:0],probe1[7:0],probe2[15:0],probe3[8:0],probe4[7:0],probe5[15:0],probe6[15:0],probe7[15:0],probe8[7:0],probe9[8:0],probe10[7:0],probe11[31:0],probe12[31:0],probe13[31:0],probe14[31:0],probe15[15:0],probe16[23:0],probe17[7:0],probe18[15:0],probe19[0:0],probe20[1:0],probe21[7:0],probe22[7:0],probe23[23:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [7:0]probe0;
|
||||
input [7:0]probe1;
|
||||
input [15:0]probe2;
|
||||
input [8:0]probe3;
|
||||
input [7:0]probe4;
|
||||
input [15:0]probe5;
|
||||
input [15:0]probe6;
|
||||
input [15:0]probe7;
|
||||
input [7:0]probe8;
|
||||
input [8:0]probe9;
|
||||
input [7:0]probe10;
|
||||
input [31:0]probe11;
|
||||
input [31:0]probe12;
|
||||
input [31:0]probe13;
|
||||
input [31:0]probe14;
|
||||
input [15:0]probe15;
|
||||
input [23:0]probe16;
|
||||
input [7:0]probe17;
|
||||
input [15:0]probe18;
|
||||
input [0:0]probe19;
|
||||
input [1:0]probe20;
|
||||
input [7:0]probe21;
|
||||
input [7:0]probe22;
|
||||
input [23:0]probe23;
|
||||
input [0:0]probe24;
|
||||
input [0:0]probe25;
|
||||
input [0:0]probe26;
|
||||
input [0:0]probe27;
|
||||
input [0:0]probe28;
|
||||
input [0:0]probe29;
|
||||
input [0:0]probe30;
|
||||
input [0:0]probe31;
|
||||
input [0:0]probe32;
|
||||
input [0:0]probe33;
|
||||
input [0:0]probe34;
|
||||
input [0:0]probe35;
|
||||
input [0:0]probe36;
|
||||
input [0:0]probe37;
|
||||
input [0:0]probe38;
|
||||
input [0:0]probe39;
|
||||
input [0:0]probe40;
|
||||
input [0:0]probe41;
|
||||
input [0:0]probe42;
|
||||
input [0:0]probe43;
|
||||
input [0:0]probe44;
|
||||
input [0:0]probe45;
|
||||
input [0:0]probe46;
|
||||
input [0:0]probe47;
|
||||
input [0:0]probe48;
|
||||
input [0:0]probe49;
|
||||
input [0:0]probe50;
|
||||
input [0:0]probe51;
|
||||
input [0:0]probe52;
|
||||
input [0:0]probe53;
|
||||
input [0:0]probe54;
|
||||
endmodule
|
||||
@@ -0,0 +1,86 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Nov 25 11:43:06 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
|
||||
-- Design : u_ila_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 23 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 23 downto 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[7:0],probe1[7:0],probe2[15:0],probe3[8:0],probe4[7:0],probe5[15:0],probe6[15:0],probe7[15:0],probe8[7:0],probe9[8:0],probe10[7:0],probe11[31:0],probe12[31:0],probe13[31:0],probe14[31:0],probe15[15:0],probe16[23:0],probe17[7:0],probe18[15:0],probe19[0:0],probe20[1:0],probe21[7:0],probe22[7:0],probe23[23:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,680 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>dc739dca7a26760c</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_a9_1_axi_smc_0</spirit:instanceName>
|
||||
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M01_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M16_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M16_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.ADDR_WIDTH">13</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.HAS_BRESP">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.HAS_LOCK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.HAS_PROT">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.ID_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.PHASE">0.0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M17_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.ADDR_WIDTH">13</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.HAS_BRESP">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.HAS_BURST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.HAS_CACHE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.HAS_LOCK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.HAS_PROT">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.HAS_QOS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.HAS_REGION">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.HAS_RRESP">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.ID_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.PHASE">0.0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M18_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M19_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M19_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M19_AXI.HAS_LOCK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M19_AXI.HAS_QOS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M19_AXI.HAS_REGION">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M19_AXI.HAS_RRESP">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M19_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_QOS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_REGION">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">dc739dca7a26760c</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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|
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</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
Reference in New Issue
Block a user