上传PL工程
This commit is contained in:
chenmin
@@ -0,0 +1,213 @@
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`timescale 1 ns / 1 ps
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module upload_config#
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(
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parameter CHANNLE_QTY = 64 ,
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parameter PRE_MSG_LEN = 24
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)
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(
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input clk ,
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input rst_n ,
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input [13-1:0] bram_addr ,
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input bram_clk ,
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input [32-1:0] bram_din ,
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output reg [32-1:0] bram_dout ,
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input bram_en ,
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input bram_rst ,
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input [ 4-1:0] bram_we ,
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output reg eeg_sel ,
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output reg protocol_sel ,
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output [ 8*PRE_MSG_LEN-1:0] pre_message_array ,
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output [ 8*CHANNLE_QTY-1:0] ch_mapping2pc_array ,
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output [ CHANNLE_QTY-1:0] upload_ch_array ,
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output reg [32-1:0] upload_round_qty_set,
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output reg [ 8-1:0] pre_message_length ,
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output reg reset_package_id ,
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output reg [32-1:0] package_overtime_ms
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam BRAM_ADDR_TEST_RO = 13'h0000;
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localparam BRAM_ADDR_TEST_RW = 13'h0004;
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localparam BRAM_ADDR_SEL = 13'h0010;
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localparam BRAM_ADDR_ROUNDS_QTY = 13'h0014;
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localparam BRAM_ADDR_PRE_MSG_LTH = 13'h0018;
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localparam BRAM_ADDR_RESET_PACKAGE_ID = 13'h001C;
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localparam BRAM_ADDR_PACKAGE_OVERTIME = 13'h0020;
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localparam BRAM_ADDR_MESSAGE_END = 13'h0024;
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localparam BRAM_ADDR_PRE_MSG_START = 13'h0100;
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localparam BRAM_ADDR_PRE_MSG_MASK = 13'h1F00;
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localparam BRAM_ADDR_CH_MAP_START = 13'h0200;
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localparam BRAM_ADDR_CH_MAP_MASK = 13'h1F00;
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localparam BRAM_ADDR_UPLOAD_CH_START = 13'h0300;
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localparam BRAM_ADDR_UPLOAD_CH_MASK = 13'h1F00;
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localparam N = (CHANNLE_QTY+7)/8;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [32-1:0] test_data ;
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wire bram_wr_valid ;
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wire bram_rd_valid ;
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reg [ 8-1:0] pre_message[0:PRE_MSG_LEN-1] ;
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reg [ 8-1:0] ch_mapping2pc[0:CHANNLE_QTY-1] ;
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reg [ 8-1:0] upload_ch[0:N-1] ;
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wire [8*N-1:0] upload_ch_array_w ;
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integer n;
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genvar i;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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//*****************************************************************************
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// Procedural blocks
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//*****************************************************************************
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//write bram/Set config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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test_data <= 0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_TEST_RW ) )
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test_data <= bram_din;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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eeg_sel <= 1'b0;
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protocol_sel <= 1'b0;
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end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_SEL ) ) begin
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eeg_sel <= bram_din[0];
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protocol_sel <= bram_din[1];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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upload_round_qty_set <= 0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_ROUNDS_QTY ) )
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upload_round_qty_set <= bram_din;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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pre_message_length <= 0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_PRE_MSG_LTH ) )
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pre_message_length <= bram_din[7:0];
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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reset_package_id <= 1'b0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_RESET_PACKAGE_ID ) )
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reset_package_id <= 1'b1;
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else
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reset_package_id <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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package_overtime_ms <= 10;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_PACKAGE_OVERTIME ) )
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package_overtime_ms <= bram_din;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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for(n=0; n<PRE_MSG_LEN; n=n+1) begin
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pre_message[n] <= 0;
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end
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end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_PRE_MSG_MASK) == BRAM_ADDR_PRE_MSG_START ) ) begin
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pre_message[{bram_addr[7:2],2'b00}] <= (bram_we[0])? bram_din[ 7: 0]:pre_message[{bram_addr[7:2],2'b00}];
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pre_message[{bram_addr[7:2],2'b01}] <= (bram_we[1])? bram_din[15: 8]:pre_message[{bram_addr[7:2],2'b01}];
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pre_message[{bram_addr[7:2],2'b10}] <= (bram_we[2])? bram_din[23:16]:pre_message[{bram_addr[7:2],2'b10}];
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pre_message[{bram_addr[7:2],2'b11}] <= (bram_we[3])? bram_din[31:24]:pre_message[{bram_addr[7:2],2'b11}];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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for(n=0; n<CHANNLE_QTY; n=n+1) begin
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ch_mapping2pc[n] <= 0;
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end
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end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_CH_MAP_MASK) == BRAM_ADDR_CH_MAP_START ) ) begin
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ch_mapping2pc[{bram_addr[7:2],2'b00}] <= (bram_we[0])? bram_din[ 7: 0]:ch_mapping2pc[{bram_addr[7:2],2'b00}];
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ch_mapping2pc[{bram_addr[7:2],2'b01}] <= (bram_we[1])? bram_din[15: 8]:ch_mapping2pc[{bram_addr[7:2],2'b01}];
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ch_mapping2pc[{bram_addr[7:2],2'b10}] <= (bram_we[2])? bram_din[23:16]:ch_mapping2pc[{bram_addr[7:2],2'b10}];
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ch_mapping2pc[{bram_addr[7:2],2'b11}] <= (bram_we[3])? bram_din[31:24]:ch_mapping2pc[{bram_addr[7:2],2'b11}];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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for(n=0; n<N; n=n+1) begin
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upload_ch[n] <= 0;
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end
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end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_UPLOAD_CH_MASK) == BRAM_ADDR_UPLOAD_CH_START ) ) begin
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upload_ch[{bram_addr[7:2],2'b00}] <= (bram_we[0])? bram_din[ 7: 0]:upload_ch[{bram_addr[7:2],2'b00}];
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upload_ch[{bram_addr[7:2],2'b01}] <= (bram_we[1])? bram_din[15: 8]:upload_ch[{bram_addr[7:2],2'b01}];
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upload_ch[{bram_addr[7:2],2'b10}] <= (bram_we[2])? bram_din[23:16]:upload_ch[{bram_addr[7:2],2'b10}];
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upload_ch[{bram_addr[7:2],2'b11}] <= (bram_we[3])? bram_din[31:24]:upload_ch[{bram_addr[7:2],2'b11}];
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end
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end
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//read bram/Get config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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bram_dout <= 0;
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end else if ( bram_rd_valid ) begin
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if ( bram_addr == BRAM_ADDR_TEST_RO )
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bram_dout <= 32'h12340004;
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if ( bram_addr == BRAM_ADDR_TEST_RW )
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bram_dout <= test_data;
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end
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end
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//*****************************************************************************
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// Continuous assignments
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//*****************************************************************************
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assign bram_wr_valid = bram_en && (bram_we != 4'h0);
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assign bram_rd_valid = bram_en && (bram_we == 4'h0);
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generate
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for(i=0;i<PRE_MSG_LEN;i=i+1) begin : pack_pre_msg
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assign pre_message_array[8*i+7 : 8*i] = pre_message[i];
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end
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endgenerate
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generate
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for(i=0;i<CHANNLE_QTY;i=i+1) begin : pack_ch_mapping
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assign ch_mapping2pc_array[8*i+7 : 8*i] = ch_mapping2pc[i];
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end
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endgenerate
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generate
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for(i=0;i<N;i=i+1) begin : pack_upload_channel
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assign upload_ch_array_w[8*i+7 : 8*i] = upload_ch[i];
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end
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endgenerate
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generate
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for(i=0;i<CHANNLE_QTY;i=i+1) begin : link_upload_channel
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assign upload_ch_array[i] = upload_ch_array_w[i];
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end
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endgenerate
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endmodule
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@@ -0,0 +1,425 @@
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`timescale 1 ns / 1 ps
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module upload_protocol_intan#
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(
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parameter CLK_PERIOD = 10 ,
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parameter CHANNLE_QTY = 64
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)
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(
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input clk ,
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input rst_n ,
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input enable ,
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output interrupt ,
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input pulse_ms ,
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input [32-1:0] upload_round_qty_set ,
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input reset_package_id ,
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input [32-1:0] package_overtime_ms ,
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input [32-1:0] s_axis_trigger_tdata ,
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input s_axis_trigger_tvalid ,
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output reg s_axis_trigger_tready ,
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input [ 8-1:0] s_axis_eeg_tdata ,
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input s_axis_eeg_tlast ,
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output reg s_axis_eeg_tready ,
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input s_axis_eeg_tvalid ,
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input m_axis_record_tfull ,
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output reg [ 8-1:0] m_axis_record_tdata ,
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output reg [ 1-1:0] m_axis_record_tkeep ,
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output reg m_axis_record_tlast ,
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input m_axis_record_tready ,
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output reg m_axis_record_tvalid
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam ST_IDLE = 4'h0 ;
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localparam ST_WAIT = 4'h1 ;
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localparam ST_MSG_HEAD = 4'h2 ;
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localparam ST_MSG_DATA_H = 4'h3 ;
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localparam ST_MSG_RECORD = 4'h4 ;
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localparam ST_MSG_DATA_T = 4'h5 ;
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localparam ST_MSG_REG_VAL = 4'h6 ;
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localparam ST_MSG_DA_AD = 4'h7 ;
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localparam ST_MSG_TRIG_IN = 4'h8 ;
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localparam ST_MSG_TRIG_OUT = 4'h9 ;
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localparam ST_MSG_CRC = 4'hA ;
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localparam ST_ADDITIONAL = 4'hB ;
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localparam HEAD_LTH = 12 ;
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localparam REG_LTH = 32 ;
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localparam DA_AD_LTH = 32 ;
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localparam TRIG_IN_LTH = 2 ;
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localparam TRIG_OUT_LTH = 2 ;
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localparam ADDL_LTH = 12 ;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [ 4-1:0] cstate ;
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reg [ 4-1:0] nstate ;
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wire [ 8-1:0] msg_head[0:HEAD_LTH-1] ;
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reg [32-1:0] package_id ;
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reg [32-1:0] overtime_ms ;
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reg [32-1:0] trigger_word ;
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wire [ 8-1:0] trigger_in_byte[0:15] ;
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// wire [ 8-1:0] trigger_out_byte[0:15] ;
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wire [ 8-1:0] msg_crc[0:1] ;
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reg [32-1:0] upload_round_qty ;
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reg [32-1:0] upload_rounds_cnt ;
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reg [32-1:0] upload_bytes_cnt ;
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wire [32-1:0] upload_bytes_cnt_add1 ;
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reg [32-1:0] upload_record_bytes_cnt ;
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wire [16-1:0] crc16_out ;
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reg [16-1:0] crc16 ;
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wire [ 8-1:0] upload_addl[0:12-1] ;
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reg [ 8-1:0] byte_cnt ;
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reg upload_break ;
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reg upload_disable ;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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//*****************************************************************************
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// Function
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//*****************************************************************************
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function automatic [15:0] crc16_d8;
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input [15:0] crcIn;
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input [7:0] data;
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begin
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crc16_d8[0] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ crcIn[7] ^ crcIn[8] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7];
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crc16_d8[1] = crcIn[9];
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crc16_d8[2] = crcIn[10];
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crc16_d8[3] = crcIn[11];
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crc16_d8[4] = crcIn[12];
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crc16_d8[5] = crcIn[13];
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crc16_d8[6] = crcIn[0] ^ crcIn[14] ^ data[0];
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crc16_d8[7] = crcIn[0] ^ crcIn[1] ^ crcIn[15] ^ data[0] ^ data[1];
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crc16_d8[8] = crcIn[1] ^ crcIn[2] ^ data[1] ^ data[2];
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crc16_d8[9] = crcIn[2] ^ crcIn[3] ^ data[2] ^ data[3];
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crc16_d8[10] = crcIn[3] ^ crcIn[4] ^ data[3] ^ data[4];
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crc16_d8[11] = crcIn[4] ^ crcIn[5] ^ data[4] ^ data[5];
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crc16_d8[12] = crcIn[5] ^ crcIn[6] ^ data[5] ^ data[6];
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crc16_d8[13] = crcIn[6] ^ crcIn[7] ^ data[6] ^ data[7];
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crc16_d8[14] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6];
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crc16_d8[15] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ crcIn[7] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7];
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end
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endfunction
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//*****************************************************************************
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always@( posedge clk or negedge rst_n ) begin
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if( !rst_n ) cstate <= ST_IDLE;
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else cstate <= nstate;
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end
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always@( * ) begin
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case ( cstate )
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ST_IDLE:
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if ( enable && s_axis_eeg_tvalid )
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nstate <= ST_MSG_HEAD;
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else
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nstate <= ST_IDLE;
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ST_WAIT:
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if ( !enable || upload_rounds_cnt == upload_round_qty || overtime_ms == package_overtime_ms || m_axis_record_tfull )
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nstate <= ST_MSG_CRC;
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else if ( s_axis_eeg_tvalid )
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nstate <= ST_MSG_HEAD;
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else
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nstate <= ST_WAIT;
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ST_MSG_HEAD:
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if ( byte_cnt == HEAD_LTH-1 )
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nstate <= ST_MSG_DATA_H;
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else
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nstate <= ST_MSG_HEAD;
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ST_MSG_DATA_H:
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if ( byte_cnt == 48-1 )
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nstate <= ST_MSG_RECORD;
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else
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nstate <= ST_MSG_DATA_H;
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ST_MSG_RECORD:
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if ( s_axis_eeg_tready && s_axis_eeg_tvalid && s_axis_eeg_tlast )
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nstate <= ST_MSG_DATA_T;
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else
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nstate <= ST_MSG_RECORD;
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ST_MSG_DATA_T:
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if ( byte_cnt == 16-1 )
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nstate <= ST_MSG_REG_VAL;
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else
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nstate <= ST_MSG_DATA_T;
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ST_MSG_REG_VAL:
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if ( byte_cnt == REG_LTH-1 )
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nstate <= ST_MSG_DA_AD;
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else
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nstate <= ST_MSG_REG_VAL;
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ST_MSG_DA_AD:
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if ( byte_cnt == DA_AD_LTH-1 )
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nstate <= ST_MSG_TRIG_IN;
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else
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nstate <= ST_MSG_DA_AD;
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ST_MSG_TRIG_IN:
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if ( byte_cnt == TRIG_IN_LTH-1 )
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nstate <= ST_MSG_TRIG_OUT;
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else
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nstate <= ST_MSG_TRIG_IN;
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ST_MSG_TRIG_OUT:
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if ( byte_cnt == TRIG_OUT_LTH-1 )
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nstate <= ST_WAIT;
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else
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nstate <= ST_MSG_TRIG_OUT;
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ST_MSG_CRC:
|
||||
if ( byte_cnt == 2-1 )
|
||||
nstate <= ST_ADDITIONAL;
|
||||
else
|
||||
nstate <= ST_MSG_CRC;
|
||||
|
||||
ST_ADDITIONAL:
|
||||
if ( byte_cnt == ADDL_LTH-1 )
|
||||
nstate <= upload_break? ST_WAIT:ST_IDLE;
|
||||
else
|
||||
nstate <= ST_ADDITIONAL;
|
||||
|
||||
default:
|
||||
nstate <= ST_IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_disable <= 1'b0;
|
||||
else if ( cstate == ST_ADDITIONAL && nstate != ST_ADDITIONAL )
|
||||
upload_disable <= m_axis_record_tfull;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_break <= 1'b0;
|
||||
else if ( cstate == ST_WAIT && (upload_rounds_cnt != upload_round_qty && overtime_ms != package_overtime_ms) && m_axis_record_tfull && !upload_disable )
|
||||
upload_break <= 1'b1;
|
||||
else if ( cstate == ST_ADDITIONAL && nstate != ST_ADDITIONAL )
|
||||
upload_break <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
package_id <= 0;
|
||||
else if ( reset_package_id )
|
||||
package_id <= 0;
|
||||
else if ( cstate == ST_MSG_TRIG_OUT && nstate == ST_WAIT )
|
||||
package_id <= package_id + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_round_qty <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
upload_round_qty <= upload_round_qty_set;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
s_axis_trigger_tready <= 1'b0;
|
||||
else if ( cstate == ST_MSG_DA_AD && nstate == ST_MSG_TRIG_IN )
|
||||
s_axis_trigger_tready <= 1'b1;
|
||||
else
|
||||
s_axis_trigger_tready <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
trigger_word <= 0;
|
||||
else if ( s_axis_trigger_tvalid && s_axis_trigger_tready )
|
||||
trigger_word <= s_axis_trigger_tdata;
|
||||
else if ( nstate == ST_WAIT )
|
||||
trigger_word <= 0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
s_axis_eeg_tready <= 1'b0;
|
||||
else if ( cstate == ST_MSG_RECORD || nstate == ST_MSG_RECORD )
|
||||
s_axis_eeg_tready <= 1'b1;
|
||||
else
|
||||
s_axis_eeg_tready <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
overtime_ms <= 0;
|
||||
else if ( s_axis_eeg_tvalid )
|
||||
overtime_ms <= 0;
|
||||
else if ( pulse_ms )
|
||||
overtime_ms <= overtime_ms + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk ) begin
|
||||
if ( cstate == ST_IDLE )
|
||||
crc16 <= 16'hFFFF;
|
||||
else if ( cstate != ST_MSG_CRC && m_axis_record_tvalid && m_axis_record_tready )
|
||||
crc16 <= crc16_out;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
byte_cnt <= 0;
|
||||
else if ( cstate != nstate )
|
||||
byte_cnt <= 0;
|
||||
else
|
||||
byte_cnt <= byte_cnt + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n ) begin
|
||||
m_axis_record_tdata <= 0;
|
||||
m_axis_record_tkeep <= 1'b1;
|
||||
m_axis_record_tvalid <= 1'b0;
|
||||
end else if ( cstate == ST_MSG_HEAD ) begin
|
||||
m_axis_record_tdata <= msg_head[byte_cnt];
|
||||
m_axis_record_tvalid <= 1'b1;
|
||||
end else if ( cstate == ST_MSG_DATA_H ) begin
|
||||
m_axis_record_tdata <= 8'd0;
|
||||
m_axis_record_tvalid <= 1'b1;
|
||||
end else if ( cstate == ST_MSG_RECORD && s_axis_eeg_tvalid && s_axis_eeg_tready ) begin
|
||||
m_axis_record_tdata <= s_axis_eeg_tdata;
|
||||
m_axis_record_tvalid <= 1'b1;
|
||||
end else if ( cstate == ST_MSG_DATA_T ) begin
|
||||
m_axis_record_tdata <= 8'd0;
|
||||
m_axis_record_tvalid <= 1'b1;
|
||||
end else if ( cstate == ST_MSG_REG_VAL ) begin
|
||||
m_axis_record_tdata <= 8'd0;
|
||||
m_axis_record_tvalid <= 1'b1;
|
||||
end else if ( cstate == ST_MSG_DA_AD ) begin
|
||||
m_axis_record_tdata <= 8'd0;
|
||||
m_axis_record_tvalid <= 1'b1;
|
||||
end else if ( cstate == ST_MSG_TRIG_IN ) begin
|
||||
m_axis_record_tdata <= trigger_in_byte[byte_cnt];
|
||||
m_axis_record_tvalid <= 1'b1;
|
||||
end else if ( cstate == ST_MSG_TRIG_OUT ) begin
|
||||
m_axis_record_tdata <= 8'd0;
|
||||
m_axis_record_tvalid <= 1'b1;
|
||||
end else if ( cstate == ST_MSG_CRC ) begin
|
||||
m_axis_record_tdata <= msg_crc[byte_cnt];
|
||||
m_axis_record_tvalid <= 1'b1;
|
||||
end else if ( cstate == ST_ADDITIONAL ) begin
|
||||
m_axis_record_tdata <= upload_addl[byte_cnt];
|
||||
m_axis_record_tvalid <= 1'b1;
|
||||
end else
|
||||
m_axis_record_tvalid <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n ) begin
|
||||
m_axis_record_tlast <= 1'b0;
|
||||
end else if ( cstate == ST_ADDITIONAL && (byte_cnt == ADDL_LTH-1) ) begin
|
||||
m_axis_record_tlast <= 1'b1;
|
||||
end else
|
||||
m_axis_record_tlast <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_rounds_cnt <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
upload_rounds_cnt <= 0;
|
||||
else if ( s_axis_eeg_tready && s_axis_eeg_tvalid && s_axis_eeg_tlast )
|
||||
upload_rounds_cnt <= upload_rounds_cnt + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_bytes_cnt <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
upload_bytes_cnt <= 0;
|
||||
else if ( (cstate != ST_ADDITIONAL) && m_axis_record_tvalid && m_axis_record_tready )
|
||||
upload_bytes_cnt <= upload_bytes_cnt + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_record_bytes_cnt <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
upload_record_bytes_cnt <= 0;
|
||||
else if ( cstate == ST_MSG_RECORD && s_axis_eeg_tvalid && s_axis_eeg_tready )
|
||||
upload_record_bytes_cnt <= upload_record_bytes_cnt + 1'b1;
|
||||
end
|
||||
|
||||
//*****************************************************************************
|
||||
// Wire assignment
|
||||
//*****************************************************************************
|
||||
assign msg_head[ 0] = 8'h0b;
|
||||
assign msg_head[ 1] = 8'h2f;
|
||||
assign msg_head[ 2] = 8'h71;
|
||||
assign msg_head[ 3] = 8'h49;
|
||||
assign msg_head[ 4] = 8'h8a;
|
||||
assign msg_head[ 5] = 8'h2c;
|
||||
assign msg_head[ 6] = 8'h54;
|
||||
assign msg_head[ 7] = 8'h8d;
|
||||
assign msg_head[ 8] = package_id[ 7: 0];
|
||||
assign msg_head[ 9] = package_id[15: 8];
|
||||
assign msg_head[10] = package_id[23:16];
|
||||
assign msg_head[11] = package_id[31:24];
|
||||
|
||||
assign trigger_in_byte[ 0] = trigger_word[ 7: 0];
|
||||
assign trigger_in_byte[ 1] = trigger_word[15: 8];
|
||||
assign trigger_in_byte[ 2] = trigger_word[23:16];
|
||||
assign trigger_in_byte[ 3] = trigger_word[31:24];
|
||||
assign trigger_in_byte[ 4] = 8'd0;
|
||||
assign trigger_in_byte[ 5] = 8'd0;
|
||||
assign trigger_in_byte[ 6] = 8'd0;
|
||||
assign trigger_in_byte[ 7] = 8'd0;
|
||||
assign trigger_in_byte[ 8] = 8'd0;
|
||||
assign trigger_in_byte[ 9] = 8'd0;
|
||||
assign trigger_in_byte[10] = 8'd0;
|
||||
assign trigger_in_byte[11] = 8'd0;
|
||||
assign trigger_in_byte[12] = 8'd0;
|
||||
assign trigger_in_byte[13] = 8'd0;
|
||||
assign trigger_in_byte[14] = 8'd0;
|
||||
assign trigger_in_byte[15] = 8'd0;
|
||||
|
||||
assign crc16_out = crc16_d8(crc16, m_axis_record_tdata);
|
||||
|
||||
assign msg_crc[0] = crc16[15: 8];
|
||||
assign msg_crc[1] = crc16[ 7: 0];
|
||||
|
||||
assign upload_bytes_cnt_add1 = upload_bytes_cnt + 1'b1;
|
||||
|
||||
assign upload_addl[ 0] = upload_bytes_cnt_add1[ 7: 0];
|
||||
assign upload_addl[ 1] = upload_bytes_cnt_add1[15: 8];
|
||||
assign upload_addl[ 2] = upload_bytes_cnt_add1[23:16];
|
||||
assign upload_addl[ 3] = upload_bytes_cnt_add1[31:24];
|
||||
assign upload_addl[ 4] = upload_rounds_cnt[ 7: 0];
|
||||
assign upload_addl[ 5] = upload_rounds_cnt[15: 8];
|
||||
assign upload_addl[ 6] = upload_rounds_cnt[23:16];
|
||||
assign upload_addl[ 7] = upload_rounds_cnt[31:24];
|
||||
assign upload_addl[ 8] = upload_record_bytes_cnt[ 7: 0];
|
||||
assign upload_addl[ 9] = upload_record_bytes_cnt[15: 8];
|
||||
assign upload_addl[10] = upload_record_bytes_cnt[23:16];
|
||||
assign upload_addl[11] = upload_record_bytes_cnt[31:24];
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,365 @@
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module upload_protocol_ql#
|
||||
(
|
||||
parameter CLK_PERIOD = 10 ,
|
||||
parameter CHANNLE_QTY = 64 ,
|
||||
parameter PRE_MSG_LEN = 128
|
||||
)
|
||||
(
|
||||
input clk ,
|
||||
input rst_n ,
|
||||
|
||||
input enable ,
|
||||
output interrupt ,
|
||||
|
||||
input pulse_ms ,
|
||||
input [64-1:0] run_time_ms ,
|
||||
|
||||
input [ 8*PRE_MSG_LEN-1:0]pre_message_array ,
|
||||
input [ 8-1:0] pre_message_length ,
|
||||
input [32-1:0] upload_round_qty_set ,
|
||||
input reset_package_id ,
|
||||
input [32-1:0] package_overtime_ms ,
|
||||
|
||||
input [32-1:0] s_axis_trigger_tdata ,
|
||||
input s_axis_trigger_tvalid ,
|
||||
output reg s_axis_trigger_tready ,
|
||||
|
||||
input [ 8-1:0] s_axis_eeg_tdata ,
|
||||
input s_axis_eeg_tlast ,
|
||||
output reg s_axis_eeg_tready ,
|
||||
input s_axis_eeg_tvalid ,
|
||||
|
||||
input [48-1:0] accel_data ,
|
||||
|
||||
input m_axis_record_tfull ,
|
||||
output reg [ 8-1:0] m_axis_record_tdata ,
|
||||
output reg [ 1-1:0] m_axis_record_tkeep ,
|
||||
output reg m_axis_record_tlast ,
|
||||
input m_axis_record_tready ,
|
||||
output reg m_axis_record_tvalid
|
||||
);
|
||||
|
||||
//*****************************************************************************
|
||||
// localparam definition
|
||||
//*****************************************************************************
|
||||
localparam ST_IDLE = 4'd0 ;
|
||||
localparam ST_MSG_HEAD = 4'd1 ;
|
||||
localparam ST_WAIT = 4'd2 ;
|
||||
localparam ST_READ_TRIGGER = 4'd3 ;
|
||||
localparam ST_MSG_TRIGGER = 4'd4 ;
|
||||
localparam ST_MSG_RECORD = 4'd5 ;
|
||||
localparam ST_MSG_CRC = 4'd6 ;
|
||||
localparam ST_ADDITIONAL = 4'd7 ;
|
||||
|
||||
localparam ADDL_NUM = 12 ;
|
||||
|
||||
//*****************************************************************************
|
||||
// Internal register and wire declarations
|
||||
//*****************************************************************************
|
||||
reg [ 4-1:0] cstate ;
|
||||
reg [ 4-1:0] nstate ;
|
||||
|
||||
reg [32-1:0] overtime_ms ;
|
||||
reg [32-1:0] package_id ;
|
||||
|
||||
wire [ 8-1:0] pre_message[0:PRE_MSG_LEN-1];
|
||||
|
||||
reg [32-1:0] trigger_word ;
|
||||
wire [ 8-1:0] trigger_byte[0:3] ;
|
||||
|
||||
wire [ 8-1:0] msg_crc[0:1] ;
|
||||
|
||||
reg [32-1:0] upload_round_qty ;
|
||||
|
||||
reg [32-1:0] upload_bytes_cnt ;
|
||||
wire [32-1:0] upload_bytes_cnt_add1 ;
|
||||
reg [32-1:0] upload_rounds_cnt ;
|
||||
reg [32-1:0] upload_record_bytes_cnt ;
|
||||
|
||||
wire [16-1:0] crc16_out ;
|
||||
reg [16-1:0] crc16 ;
|
||||
|
||||
wire [ 8-1:0] upload_addl[0:ADDL_NUM-1] ;
|
||||
|
||||
reg [ 8-1:0] byte_cnt ;
|
||||
|
||||
|
||||
reg upload_break ;
|
||||
reg upload_disable ;
|
||||
|
||||
wire [ 4-1:0] debug_sig_sort ;
|
||||
|
||||
genvar i;
|
||||
|
||||
//*****************************************************************************
|
||||
// Instantiation
|
||||
//*****************************************************************************
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// Function
|
||||
//*****************************************************************************
|
||||
function automatic [15:0] crc16_d8;
|
||||
input [15:0] crcIn;
|
||||
input [7:0] data;
|
||||
begin
|
||||
crc16_d8[0] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ crcIn[7] ^ crcIn[8] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7];
|
||||
crc16_d8[1] = crcIn[9];
|
||||
crc16_d8[2] = crcIn[10];
|
||||
crc16_d8[3] = crcIn[11];
|
||||
crc16_d8[4] = crcIn[12];
|
||||
crc16_d8[5] = crcIn[13];
|
||||
crc16_d8[6] = crcIn[0] ^ crcIn[14] ^ data[0];
|
||||
crc16_d8[7] = crcIn[0] ^ crcIn[1] ^ crcIn[15] ^ data[0] ^ data[1];
|
||||
crc16_d8[8] = crcIn[1] ^ crcIn[2] ^ data[1] ^ data[2];
|
||||
crc16_d8[9] = crcIn[2] ^ crcIn[3] ^ data[2] ^ data[3];
|
||||
crc16_d8[10] = crcIn[3] ^ crcIn[4] ^ data[3] ^ data[4];
|
||||
crc16_d8[11] = crcIn[4] ^ crcIn[5] ^ data[4] ^ data[5];
|
||||
crc16_d8[12] = crcIn[5] ^ crcIn[6] ^ data[5] ^ data[6];
|
||||
crc16_d8[13] = crcIn[6] ^ crcIn[7] ^ data[6] ^ data[7];
|
||||
crc16_d8[14] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6];
|
||||
crc16_d8[15] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ crcIn[7] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7];
|
||||
end
|
||||
endfunction
|
||||
|
||||
//*****************************************************************************
|
||||
always@( posedge clk or negedge rst_n ) begin
|
||||
if( !rst_n ) cstate <= ST_IDLE;
|
||||
else cstate <= nstate;
|
||||
end
|
||||
|
||||
always@( * ) begin
|
||||
case ( cstate )
|
||||
ST_IDLE:
|
||||
if ( enable && s_axis_eeg_tvalid )
|
||||
nstate <= ST_MSG_HEAD;
|
||||
else
|
||||
nstate <= ST_IDLE;
|
||||
ST_MSG_HEAD:
|
||||
if ( byte_cnt == pre_message_length - 1 )
|
||||
nstate <= ST_WAIT;
|
||||
else
|
||||
nstate <= ST_MSG_HEAD;
|
||||
ST_WAIT:
|
||||
if ( !enable || upload_rounds_cnt == upload_round_qty || overtime_ms == package_overtime_ms || (m_axis_record_tfull && !upload_disable) )
|
||||
nstate <= ST_MSG_CRC;
|
||||
else if ( s_axis_eeg_tvalid )
|
||||
nstate <= ST_READ_TRIGGER;
|
||||
else
|
||||
nstate <= ST_WAIT;
|
||||
ST_READ_TRIGGER:
|
||||
nstate <= ST_MSG_TRIGGER;
|
||||
ST_MSG_TRIGGER:
|
||||
if ( byte_cnt == 4-1 )
|
||||
nstate <= ST_MSG_RECORD;
|
||||
else
|
||||
nstate <= ST_MSG_TRIGGER;
|
||||
ST_MSG_RECORD:
|
||||
if ( s_axis_eeg_tready && s_axis_eeg_tvalid && s_axis_eeg_tlast )
|
||||
nstate <= ST_WAIT;
|
||||
else
|
||||
nstate <= ST_MSG_RECORD;
|
||||
ST_MSG_CRC:
|
||||
if ( byte_cnt == 2-1 )
|
||||
nstate <= ST_ADDITIONAL;
|
||||
else
|
||||
nstate <= ST_MSG_CRC;
|
||||
ST_ADDITIONAL:
|
||||
if ( byte_cnt == ADDL_NUM-1 )
|
||||
nstate <= upload_break? ST_WAIT:ST_IDLE;
|
||||
else
|
||||
nstate <= ST_ADDITIONAL;
|
||||
default:
|
||||
nstate <= ST_IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_break <= 1'b0;
|
||||
else if ( cstate == ST_WAIT && (upload_rounds_cnt != upload_round_qty && overtime_ms != package_overtime_ms) && m_axis_record_tfull && !upload_disable )
|
||||
upload_break <= 1'b1;
|
||||
else if ( cstate == ST_ADDITIONAL && nstate != ST_ADDITIONAL )
|
||||
upload_break <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_disable <= 1'b0;
|
||||
else if ( cstate == ST_ADDITIONAL && nstate != ST_ADDITIONAL )
|
||||
upload_disable <= m_axis_record_tfull;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
package_id <= 0;
|
||||
else if ( reset_package_id )
|
||||
package_id <= 0;
|
||||
else if ( cstate == ST_MSG_CRC && nstate == ST_ADDITIONAL )
|
||||
package_id <= package_id + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_round_qty <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
upload_round_qty <= upload_round_qty_set;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
s_axis_trigger_tready <= 1'b0;
|
||||
else if ( nstate == ST_READ_TRIGGER )
|
||||
s_axis_trigger_tready <= 1'b1;
|
||||
else
|
||||
s_axis_trigger_tready <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
trigger_word <= 0;
|
||||
else if ( s_axis_trigger_tvalid && s_axis_trigger_tready )
|
||||
trigger_word <= s_axis_trigger_tdata;
|
||||
else if ( cstate != ST_MSG_TRIGGER )
|
||||
trigger_word <= 0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
s_axis_eeg_tready <= 1'b0;
|
||||
else if ( cstate == ST_MSG_RECORD || nstate == ST_MSG_RECORD )
|
||||
s_axis_eeg_tready <= 1'b1;
|
||||
else
|
||||
s_axis_eeg_tready <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_rounds_cnt <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
upload_rounds_cnt <= 0;
|
||||
else if ( s_axis_eeg_tready && s_axis_eeg_tvalid && s_axis_eeg_tlast )
|
||||
upload_rounds_cnt <= upload_rounds_cnt + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
overtime_ms <= 0;
|
||||
else if ( s_axis_eeg_tvalid )
|
||||
overtime_ms <= 0;
|
||||
else if ( pulse_ms )
|
||||
overtime_ms <= overtime_ms + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
byte_cnt <= 0;
|
||||
else if ( cstate != nstate )
|
||||
byte_cnt <= 0;
|
||||
else
|
||||
byte_cnt <= byte_cnt + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n ) begin
|
||||
m_axis_record_tdata <= 0;
|
||||
m_axis_record_tkeep <= 1'b1;
|
||||
m_axis_record_tvalid <= 1'b0;
|
||||
end else if ( cstate == ST_MSG_HEAD ) begin
|
||||
m_axis_record_tdata <= pre_message[byte_cnt];
|
||||
m_axis_record_tvalid <= upload_disable? 1'b0:1'b1;
|
||||
end else if ( cstate == ST_MSG_TRIGGER ) begin
|
||||
m_axis_record_tdata <= trigger_byte[byte_cnt];
|
||||
m_axis_record_tvalid <= upload_disable? 1'b0:1'b1;
|
||||
end else if ( cstate == ST_MSG_RECORD && s_axis_eeg_tvalid && s_axis_eeg_tready ) begin
|
||||
m_axis_record_tdata <= s_axis_eeg_tdata;
|
||||
m_axis_record_tvalid <= upload_disable? 1'b0:1'b1;
|
||||
end else if ( cstate == ST_MSG_CRC ) begin
|
||||
m_axis_record_tdata <= msg_crc[byte_cnt];
|
||||
m_axis_record_tvalid <= upload_disable? 1'b0:1'b1;
|
||||
end else if ( cstate == ST_ADDITIONAL ) begin
|
||||
m_axis_record_tdata <= upload_addl[byte_cnt];
|
||||
m_axis_record_tvalid <= upload_disable? 1'b0:1'b1;
|
||||
end else
|
||||
m_axis_record_tvalid <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk ) begin
|
||||
if ( cstate == ST_IDLE )
|
||||
crc16 <= 16'hFFFF;
|
||||
else if ( cstate != ST_MSG_CRC && m_axis_record_tvalid && m_axis_record_tready )
|
||||
crc16 <= crc16_out;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n ) begin
|
||||
m_axis_record_tlast <= 1'b0;
|
||||
end else if ( cstate == ST_ADDITIONAL && (byte_cnt == ADDL_NUM-1) ) begin
|
||||
m_axis_record_tlast <= 1'b1;
|
||||
end else
|
||||
m_axis_record_tlast <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_bytes_cnt <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
upload_bytes_cnt <= 0;
|
||||
else if ( (cstate != ST_ADDITIONAL) && m_axis_record_tvalid && m_axis_record_tready )
|
||||
upload_bytes_cnt <= upload_bytes_cnt + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_record_bytes_cnt <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
upload_record_bytes_cnt <= 0;
|
||||
else if ( cstate == ST_MSG_RECORD && s_axis_eeg_tvalid && s_axis_eeg_tready )
|
||||
upload_record_bytes_cnt <= upload_record_bytes_cnt + 1'b1;
|
||||
end
|
||||
|
||||
//*****************************************************************************
|
||||
// Wire assignment
|
||||
//*****************************************************************************
|
||||
//pre_message[21:14] is run_time_ms
|
||||
//pre_message[26:23] is package_id
|
||||
generate
|
||||
for(i=0;i<PRE_MSG_LEN;i=i+1) begin : pre_msg
|
||||
if ( i > 13 && i < 22 )
|
||||
assign pre_message[i] = run_time_ms[8*(i-14)+7 : 8*(i-14)];
|
||||
else if ( i > 22 && i < 27 )
|
||||
assign pre_message[i] = package_id[8*(i-23)+7 : 8*(i-23)];
|
||||
else
|
||||
assign pre_message[i] = pre_message_array[8*i+7 : 8*i];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign trigger_byte[0] = trigger_word[ 7: 0];
|
||||
assign trigger_byte[1] = trigger_word[15: 8];
|
||||
assign trigger_byte[2] = trigger_word[23:16];
|
||||
assign trigger_byte[3] = trigger_word[31:24];
|
||||
|
||||
assign crc16_out = crc16_d8(crc16, m_axis_record_tdata);
|
||||
|
||||
assign msg_crc[0] = crc16[15: 8];
|
||||
assign msg_crc[1] = crc16[ 7: 0];
|
||||
|
||||
assign upload_bytes_cnt_add1 = upload_bytes_cnt + 1'b1;
|
||||
|
||||
assign upload_addl[ 0] = upload_bytes_cnt_add1[ 7: 0];
|
||||
assign upload_addl[ 1] = upload_bytes_cnt_add1[15: 8];
|
||||
assign upload_addl[ 2] = upload_bytes_cnt_add1[23:16];
|
||||
assign upload_addl[ 3] = upload_bytes_cnt_add1[31:24];
|
||||
assign upload_addl[ 4] = upload_rounds_cnt[ 7: 0];
|
||||
assign upload_addl[ 5] = upload_rounds_cnt[15: 8];
|
||||
assign upload_addl[ 6] = upload_rounds_cnt[23:16];
|
||||
assign upload_addl[ 7] = upload_rounds_cnt[31:24];
|
||||
assign upload_addl[ 8] = upload_record_bytes_cnt[ 7: 0];
|
||||
assign upload_addl[ 9] = upload_record_bytes_cnt[15: 8];
|
||||
assign upload_addl[10] = upload_record_bytes_cnt[23:16];
|
||||
assign upload_addl[11] = upload_record_bytes_cnt[31:24];
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,293 @@
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module upload_sort#
|
||||
(
|
||||
parameter CLK_PERIOD = 10 ,
|
||||
parameter CHANNLE_QTY = 64
|
||||
)
|
||||
(
|
||||
input clk ,
|
||||
input rst_n ,
|
||||
|
||||
input eeg_sel ,
|
||||
input protocol_sel ,
|
||||
input [8*CHANNLE_QTY-1:0] ch_mapping2pc_array ,
|
||||
input [CHANNLE_QTY-1:0] upload_ch_array ,
|
||||
|
||||
//------------------------------------------ PL logic
|
||||
input [32-1:0] s_axis_eeg16_tdata ,
|
||||
input s_axis_eeg16_tlast ,
|
||||
output s_axis_eeg16_tready ,
|
||||
input s_axis_eeg16_tvalid ,
|
||||
|
||||
input [32-1:0] s_axis_eeg24_tdata ,
|
||||
input s_axis_eeg24_tlast ,
|
||||
output s_axis_eeg24_tready ,
|
||||
input s_axis_eeg24_tvalid ,
|
||||
|
||||
//------------------------------------------ PC logic
|
||||
output [ 8-1:0] m_axis_eeg_tdata ,
|
||||
output m_axis_eeg_tlast ,
|
||||
input m_axis_eeg_tready ,
|
||||
output m_axis_eeg_tvalid ,
|
||||
|
||||
output [ 4-1:0] debug_sig_sort
|
||||
);
|
||||
|
||||
//*****************************************************************************
|
||||
// localparam definition
|
||||
//*****************************************************************************
|
||||
localparam ST_IDLE = 4'd0 ;
|
||||
localparam ST_RX = 4'd1 ;
|
||||
localparam ST_SCAN = 4'd2 ;
|
||||
localparam ST_TX = 4'd3 ;
|
||||
|
||||
//*****************************************************************************
|
||||
// Internal register and wire declarations
|
||||
//*****************************************************************************
|
||||
wire [32-1:0] s_axis_eegX_tdata ;
|
||||
wire s_axis_eegX_tlast ;
|
||||
wire s_axis_eegX_tready ;
|
||||
wire s_axis_eegX_tvalid ;
|
||||
|
||||
wire [ 8-1:0] ch_map2pc[0:CHANNLE_QTY-1] ;
|
||||
wire [ 8-1:0] ch_map2intan[0:CHANNLE_QTY-1];
|
||||
|
||||
wire [ 8-1:0] ch_pl ;
|
||||
wire [ 8-1:0] ch_pc ;
|
||||
|
||||
reg [ 4-1:0] cstate ;
|
||||
reg [ 4-1:0] nstate ;
|
||||
|
||||
reg [32-1:0] record_rx[0:CHANNLE_QTY-1] ;
|
||||
reg [32-1:0] record_tx ;
|
||||
wire [ 8-1:0] byte_tx[0:3] ;
|
||||
reg [CHANNLE_QTY-1:0] ch_list ;
|
||||
reg [16-1:0] ch ;
|
||||
wire [ 4-1:0] bytes ;
|
||||
reg [ 4-1:0] byte_cnt ;
|
||||
|
||||
reg [ 8-1:0] m_axis_eegY_tdata ;
|
||||
reg m_axis_eegY_tlast ;
|
||||
wire m_axis_eegY_tready ;
|
||||
reg m_axis_eegY_tvalid ;
|
||||
|
||||
genvar i;
|
||||
integer j;
|
||||
|
||||
//*****************************************************************************
|
||||
// Instantiation
|
||||
//*****************************************************************************
|
||||
axis_data_fifo_w8_d128 u_axis_data_fifo_w8_d128
|
||||
(
|
||||
.s_axis_aresetn ( rst_n ),
|
||||
.s_axis_aclk ( clk ),
|
||||
|
||||
.s_axis_tvalid ( m_axis_eegY_tvalid ),
|
||||
.s_axis_tready ( m_axis_eegY_tready ),
|
||||
.s_axis_tdata ( m_axis_eegY_tdata ),
|
||||
.s_axis_tlast ( m_axis_eegY_tlast ),
|
||||
|
||||
.m_axis_tvalid ( m_axis_eeg_tvalid ),
|
||||
.m_axis_tready ( m_axis_eeg_tready ),
|
||||
.m_axis_tdata ( m_axis_eeg_tdata ),
|
||||
.m_axis_tlast ( m_axis_eeg_tlast )
|
||||
);
|
||||
|
||||
//*****************************************************************************
|
||||
always@( posedge clk or negedge rst_n ) begin
|
||||
if( !rst_n ) cstate <= ST_IDLE;
|
||||
else cstate <= nstate;
|
||||
end
|
||||
|
||||
always@( * ) begin
|
||||
case ( cstate )
|
||||
ST_IDLE:
|
||||
if ( s_axis_eegX_tvalid )
|
||||
nstate <= ST_RX;
|
||||
else
|
||||
nstate <= ST_IDLE;
|
||||
ST_RX:
|
||||
if ( s_axis_eegX_tvalid && s_axis_eegX_tlast )
|
||||
nstate <= ST_SCAN;
|
||||
else
|
||||
nstate <= ST_RX;
|
||||
ST_SCAN:
|
||||
if ( ch == CHANNLE_QTY || ch_list == 0 )
|
||||
nstate <= ST_IDLE;
|
||||
else if ( upload_ch_array[ch] )
|
||||
nstate <= ST_TX;
|
||||
else
|
||||
nstate <= ST_SCAN;
|
||||
ST_TX:
|
||||
if ( byte_cnt == bytes - 1 )
|
||||
nstate <= ST_SCAN;
|
||||
else
|
||||
nstate <= ST_TX;
|
||||
default:
|
||||
nstate <= ST_IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
ch_list <= 0;
|
||||
else if ( nstate == ST_RX )
|
||||
ch_list <= upload_ch_array;
|
||||
else if ( cstate == ST_SCAN )
|
||||
ch_list <= {1'b0, ch_list[CHANNLE_QTY-1:1]};
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n ) begin
|
||||
for (j=0; j<CHANNLE_QTY; j=j+1) begin
|
||||
record_rx[j] <= 0;
|
||||
end
|
||||
end else if ( (nstate == ST_RX || cstate == ST_RX) && s_axis_eegX_tvalid ) begin
|
||||
record_rx[ch_pc] <= s_axis_eegX_tdata;
|
||||
end
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
ch <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
ch <= 0;
|
||||
else if ( cstate == ST_SCAN )
|
||||
ch <= ch + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
record_tx <= 0;
|
||||
else if ( cstate == ST_SCAN && nstate == ST_TX )
|
||||
record_tx <= record_rx[ch];
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
byte_cnt <= 0;
|
||||
else if ( cstate == ST_TX )
|
||||
byte_cnt <= byte_cnt + 1'b1;
|
||||
else
|
||||
byte_cnt <= 0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n ) begin
|
||||
m_axis_eegY_tvalid <= 1'b0;
|
||||
m_axis_eegY_tdata <= 0;
|
||||
end else if ( cstate == ST_TX ) begin
|
||||
m_axis_eegY_tvalid <= 1'b1;
|
||||
m_axis_eegY_tdata <= byte_tx[byte_cnt];
|
||||
end else
|
||||
m_axis_eegY_tvalid <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
m_axis_eegY_tlast <= 1'b0;
|
||||
else if ( cstate == ST_TX && (byte_cnt == bytes - 1) && ch_list == 0 )
|
||||
m_axis_eegY_tlast <= 1'b1;
|
||||
else
|
||||
m_axis_eegY_tlast <= 1'b0;
|
||||
end
|
||||
|
||||
//*****************************************************************************
|
||||
// Wire assignment
|
||||
//*****************************************************************************
|
||||
assign s_axis_eegX_tready = 1'b1;
|
||||
assign s_axis_eegX_tdata = (!eeg_sel)? s_axis_eeg16_tdata : s_axis_eeg24_tdata;
|
||||
assign s_axis_eegX_tlast = (!eeg_sel)? s_axis_eeg16_tlast : s_axis_eeg24_tlast;
|
||||
assign s_axis_eegX_tvalid = (!eeg_sel)? s_axis_eeg16_tvalid : s_axis_eeg24_tvalid;
|
||||
assign s_axis_eeg24_tready = s_axis_eegX_tready;
|
||||
assign s_axis_eeg16_tready = s_axis_eegX_tready;
|
||||
|
||||
assign ch_pl = (!eeg_sel)? s_axis_eegX_tdata[15:10]:s_axis_eegX_tdata[31:24];
|
||||
assign ch_pc = (!protocol_sel)? ch_map2intan[ch_pl]:ch_map2pc[ch_pl];
|
||||
|
||||
//TODO: Unify PL and PS foramt, then protocol_sel==1 and eeg_sel==0
|
||||
assign byte_tx[0] = (!protocol_sel)? 8'h00 : ( (!eeg_sel)? record_tx[23:16] : record_tx[23:16] );
|
||||
assign byte_tx[1] = (!protocol_sel)? 8'h00 : ( (!eeg_sel)? record_tx[31:24] : record_tx[15: 8] );
|
||||
assign byte_tx[2] = (!protocol_sel)? ( (!eeg_sel)? record_tx[23:16]:record_tx[12: 5] ) : ( (!eeg_sel)? record_tx[23:16] : record_tx[ 7: 0] );
|
||||
assign byte_tx[3] = (!protocol_sel)? ( (!eeg_sel)? record_tx[31:24]:{record_tx[23], record_tx[19:13]} ) : ( (!eeg_sel)? record_tx[31:24] : record_tx[31:24] );
|
||||
|
||||
assign bytes = (!protocol_sel)? 4:((!eeg_sel)? 2:3);
|
||||
|
||||
generate
|
||||
for(i=0;i<CHANNLE_QTY;i=i+1) begin : unpack
|
||||
assign ch_map2pc[i] = ch_mapping2pc_array[8*i+7 : 8*i];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign ch_map2intan[ 0] = 43;
|
||||
assign ch_map2intan[ 1] = 47;
|
||||
assign ch_map2intan[ 2] = 19;
|
||||
assign ch_map2intan[ 3] = 7;
|
||||
assign ch_map2intan[ 4] = 11;
|
||||
assign ch_map2intan[ 5] = 63;
|
||||
assign ch_map2intan[ 6] = 3;
|
||||
assign ch_map2intan[ 7] = 59;
|
||||
assign ch_map2intan[ 8] = 29;
|
||||
assign ch_map2intan[ 9] = 52;
|
||||
assign ch_map2intan[10] = 36;
|
||||
assign ch_map2intan[11] = 40;
|
||||
assign ch_map2intan[12] = 35;
|
||||
assign ch_map2intan[13] = 60;
|
||||
assign ch_map2intan[14] = 27;
|
||||
assign ch_map2intan[15] = 56;
|
||||
assign ch_map2intan[16] = 30;
|
||||
assign ch_map2intan[17] = 18;
|
||||
assign ch_map2intan[18] = 6;
|
||||
assign ch_map2intan[19] = 5;
|
||||
assign ch_map2intan[20] = 58;
|
||||
assign ch_map2intan[21] = 62;
|
||||
assign ch_map2intan[22] = 42;
|
||||
assign ch_map2intan[23] = 54;
|
||||
assign ch_map2intan[24] = 34;
|
||||
assign ch_map2intan[25] = 38;
|
||||
assign ch_map2intan[26] = 26;
|
||||
assign ch_map2intan[27] = 14;
|
||||
assign ch_map2intan[28] = 2;
|
||||
assign ch_map2intan[29] = 10;
|
||||
assign ch_map2intan[30] = 1;
|
||||
assign ch_map2intan[31] = 22;
|
||||
assign ch_map2intan[32] = 24;
|
||||
assign ch_map2intan[33] = 41;
|
||||
assign ch_map2intan[34] = 16;
|
||||
assign ch_map2intan[35] = 20;
|
||||
assign ch_map2intan[36] = 33;
|
||||
assign ch_map2intan[37] = 21;
|
||||
assign ch_map2intan[38] = 32;
|
||||
assign ch_map2intan[39] = 57;
|
||||
assign ch_map2intan[40] = 31;
|
||||
assign ch_map2intan[41] = 39;
|
||||
assign ch_map2intan[42] = 23;
|
||||
assign ch_map2intan[43] = 15;
|
||||
assign ch_map2intan[44] = 50;
|
||||
assign ch_map2intan[45] = 55;
|
||||
assign ch_map2intan[46] = 46;
|
||||
assign ch_map2intan[47] = 51;
|
||||
assign ch_map2intan[48] = 9;
|
||||
assign ch_map2intan[49] = 17;
|
||||
assign ch_map2intan[50] = 61;
|
||||
assign ch_map2intan[51] = 49;
|
||||
assign ch_map2intan[52] = 28;
|
||||
assign ch_map2intan[53] = 37;
|
||||
assign ch_map2intan[54] = 8;
|
||||
assign ch_map2intan[55] = 0;
|
||||
assign ch_map2intan[56] = 4;
|
||||
assign ch_map2intan[57] = 12;
|
||||
assign ch_map2intan[58] = 44;
|
||||
assign ch_map2intan[59] = 48;
|
||||
assign ch_map2intan[60] = 25;
|
||||
assign ch_map2intan[61] = 13;
|
||||
assign ch_map2intan[62] = 53;
|
||||
assign ch_map2intan[63] = 45;
|
||||
|
||||
assign debug_sig_sort[0] = m_axis_eegY_tvalid; //yellow
|
||||
assign debug_sig_sort[1] = m_axis_eegY_tready; //blue
|
||||
assign debug_sig_sort[2] = m_axis_eegY_tlast;
|
||||
assign debug_sig_sort[3] = 1'b0;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,284 @@
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module upload_top#
|
||||
(
|
||||
parameter CLK_PERIOD = 10 ,
|
||||
parameter CHANNLE_QTY = 64 ,
|
||||
parameter PRE_MSG_LEN = 128
|
||||
)
|
||||
(
|
||||
input clk ,
|
||||
input rst_n ,
|
||||
|
||||
input [13-1:0] bram_addr ,
|
||||
input bram_clk ,
|
||||
input [32-1:0] bram_din ,
|
||||
output [32-1:0] bram_dout ,
|
||||
input bram_en ,
|
||||
input bram_rst ,
|
||||
input [ 4-1:0] bram_we ,
|
||||
|
||||
output interrupt ,
|
||||
|
||||
input [32-1:0] s_axis_trigger_tdata ,
|
||||
input s_axis_trigger_tvalid ,
|
||||
output s_axis_trigger_tready ,
|
||||
|
||||
input [32-1:0] s_axis_eeg16_tdata ,
|
||||
input s_axis_eeg16_tlast ,
|
||||
output s_axis_eeg16_tready ,
|
||||
input s_axis_eeg16_tvalid ,
|
||||
|
||||
input [32-1:0] s_axis_eeg24_tdata ,
|
||||
input s_axis_eeg24_tlast ,
|
||||
output s_axis_eeg24_tready ,
|
||||
input s_axis_eeg24_tvalid ,
|
||||
|
||||
input [32-1:0] s_axis_emg_tdata ,
|
||||
input s_axis_emg_tlast ,
|
||||
output s_axis_emg_tready ,
|
||||
input s_axis_emg_tvalid ,
|
||||
|
||||
input [48-1:0] accel_data ,
|
||||
|
||||
input m_axis_record_tfull ,
|
||||
output [ 8-1:0] m_axis_record_tdata ,
|
||||
output [ 1-1:0] m_axis_record_tkeep ,
|
||||
output m_axis_record_tlast ,
|
||||
input m_axis_record_tready ,
|
||||
output m_axis_record_tvalid ,
|
||||
|
||||
output [ 4-1:0] debug_sig
|
||||
);
|
||||
|
||||
//*****************************************************************************
|
||||
// localparam definition
|
||||
//*****************************************************************************
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// Internal register and wire declarations
|
||||
//*****************************************************************************
|
||||
wire pulse_ms ;
|
||||
wire [64-1:0] run_time_ms ;
|
||||
|
||||
wire eeg_sel ;
|
||||
wire protocol_sel ;
|
||||
wire reset_package_id ;
|
||||
wire [32-1:0] overtime_ms ;
|
||||
wire [ 8*PRE_MSG_LEN-1:0] pre_message_array ;
|
||||
wire [ 8-1:0] pre_message_length ;
|
||||
wire [ 8*CHANNLE_QTY-1:0] ch_mapping2pc_array ;
|
||||
wire [ CHANNLE_QTY-1:0] upload_ch_array ;
|
||||
wire [32-1:0] upload_round_qty_set ;
|
||||
|
||||
wire [32-1:0] s_axis_trig_ql_tdata ;
|
||||
wire s_axis_trig_ql_tvalid ;
|
||||
wire s_axis_trig_ql_tready ;
|
||||
|
||||
wire [32-1:0] s_axis_trig_intan_tdata ;
|
||||
wire s_axis_trig_intan_tvalid ;
|
||||
wire s_axis_trig_intan_tready ;
|
||||
|
||||
wire [ 8-1:0] m_axis_eeg_tdata ;
|
||||
wire m_axis_eeg_tlast ;
|
||||
wire m_axis_eeg_tready ;
|
||||
wire m_axis_eeg_tvalid ;
|
||||
|
||||
wire m_axis_eeg_ql_tready ;
|
||||
wire m_axis_eeg_intan_tready ;
|
||||
|
||||
wire m_axis_ql_tfull ;
|
||||
wire [ 8-1:0] m_axis_ql_tdata ;
|
||||
wire [ 1-1:0] m_axis_ql_tkeep ;
|
||||
wire m_axis_ql_tlast ;
|
||||
wire m_axis_ql_tready ;
|
||||
wire m_axis_ql_tvalid ;
|
||||
|
||||
wire m_axis_intan_tfull ;
|
||||
wire [ 8-1:0] m_axis_intan_tdata ;
|
||||
wire [ 1-1:0] m_axis_intan_tkeep ;
|
||||
wire m_axis_intan_tlast ;
|
||||
wire m_axis_intan_tready ;
|
||||
wire m_axis_intan_tvalid ;
|
||||
|
||||
wire [ 4-1:0] debug_sig_sort ;
|
||||
|
||||
genvar i;
|
||||
|
||||
//*****************************************************************************
|
||||
// Instantiation
|
||||
//*****************************************************************************
|
||||
run_time#
|
||||
(
|
||||
.CLK_PERIOD ( CLK_PERIOD )
|
||||
)
|
||||
u_run_time
|
||||
(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
|
||||
.pulse_ms ( pulse_ms ),
|
||||
.run_time_ms ( run_time_ms )
|
||||
);
|
||||
|
||||
upload_config#
|
||||
(
|
||||
.CHANNLE_QTY ( CHANNLE_QTY ),
|
||||
.PRE_MSG_LEN ( PRE_MSG_LEN )
|
||||
)
|
||||
u_upload_config
|
||||
(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
|
||||
.bram_addr ( bram_addr ),
|
||||
.bram_clk ( bram_clk ),
|
||||
.bram_din ( bram_din ),
|
||||
.bram_dout ( bram_dout ),
|
||||
.bram_en ( bram_en ),
|
||||
.bram_rst ( bram_rst ),
|
||||
.bram_we ( bram_we ),
|
||||
|
||||
.eeg_sel ( eeg_sel ),
|
||||
.protocol_sel ( protocol_sel ),
|
||||
|
||||
.pre_message_array ( pre_message_array ),
|
||||
.pre_message_length ( pre_message_length ),
|
||||
.upload_round_qty_set ( upload_round_qty_set ),
|
||||
.ch_mapping2pc_array ( ch_mapping2pc_array ),
|
||||
.upload_ch_array ( upload_ch_array ),
|
||||
.reset_package_id ( reset_package_id ),
|
||||
.package_overtime_ms ( overtime_ms )
|
||||
);
|
||||
|
||||
upload_sort#
|
||||
(
|
||||
.CLK_PERIOD ( CLK_PERIOD ),
|
||||
.CHANNLE_QTY ( CHANNLE_QTY )
|
||||
)
|
||||
u_upload_sort
|
||||
(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
|
||||
.eeg_sel ( eeg_sel ),
|
||||
.protocol_sel ( protocol_sel ),
|
||||
.ch_mapping2pc_array ( ch_mapping2pc_array ),
|
||||
.upload_ch_array ( upload_ch_array ),
|
||||
|
||||
//------------------------------------------ PL logic
|
||||
.s_axis_eeg16_tdata ( s_axis_eeg16_tdata ),
|
||||
.s_axis_eeg16_tlast ( s_axis_eeg16_tlast ),
|
||||
.s_axis_eeg16_tready ( s_axis_eeg16_tready ),
|
||||
.s_axis_eeg16_tvalid ( s_axis_eeg16_tvalid ),
|
||||
|
||||
.s_axis_eeg24_tdata ( s_axis_eeg24_tdata ),
|
||||
.s_axis_eeg24_tlast ( s_axis_eeg24_tlast ),
|
||||
.s_axis_eeg24_tready ( s_axis_eeg24_tready ),
|
||||
.s_axis_eeg24_tvalid ( s_axis_eeg24_tvalid ),
|
||||
|
||||
//------------------------------------------ PC logic
|
||||
.m_axis_eeg_tdata ( m_axis_eeg_tdata ),
|
||||
.m_axis_eeg_tlast ( m_axis_eeg_tlast ),
|
||||
.m_axis_eeg_tready ( m_axis_eeg_tready ),
|
||||
.m_axis_eeg_tvalid ( m_axis_eeg_tvalid ),
|
||||
|
||||
.debug_sig_sort ( debug_sig_sort )
|
||||
);
|
||||
|
||||
upload_protocol_ql#
|
||||
(
|
||||
.CLK_PERIOD ( CLK_PERIOD ),
|
||||
.PRE_MSG_LEN ( PRE_MSG_LEN )
|
||||
)
|
||||
u_upload_protocol_ql
|
||||
(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
|
||||
.enable ( protocol_sel ),
|
||||
.pulse_ms ( pulse_ms ),
|
||||
.run_time_ms ( run_time_ms ),
|
||||
|
||||
.pre_message_array ( pre_message_array ),
|
||||
.pre_message_length ( pre_message_length ),
|
||||
.upload_round_qty_set ( upload_round_qty_set ),
|
||||
.reset_package_id ( reset_package_id ),
|
||||
.package_overtime_ms ( overtime_ms ),
|
||||
|
||||
.s_axis_trigger_tdata ( s_axis_trig_ql_tdata ),
|
||||
.s_axis_trigger_tvalid ( s_axis_trig_ql_tvalid ),
|
||||
.s_axis_trigger_tready ( s_axis_trig_ql_tready ),
|
||||
|
||||
.s_axis_eeg_tdata ( m_axis_eeg_tdata ),
|
||||
.s_axis_eeg_tlast ( m_axis_eeg_tlast ),
|
||||
.s_axis_eeg_tready ( m_axis_eeg_ql_tready ),
|
||||
.s_axis_eeg_tvalid ( m_axis_eeg_tvalid ),
|
||||
|
||||
.accel_data ( accel_data ),
|
||||
|
||||
.m_axis_record_tfull ( m_axis_ql_tfull ),
|
||||
.m_axis_record_tdata ( m_axis_ql_tdata ),
|
||||
.m_axis_record_tkeep ( m_axis_ql_tkeep ),
|
||||
.m_axis_record_tlast ( m_axis_ql_tlast ),
|
||||
.m_axis_record_tready ( m_axis_ql_tready ),
|
||||
.m_axis_record_tvalid ( m_axis_ql_tvalid )
|
||||
);
|
||||
|
||||
upload_protocol_intan#
|
||||
(
|
||||
.CLK_PERIOD ( CLK_PERIOD )
|
||||
)
|
||||
u_upload_protocol_intan
|
||||
(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
|
||||
.enable ( !protocol_sel ),
|
||||
.interrupt ( ),
|
||||
.pulse_ms ( pulse_ms ),
|
||||
|
||||
.upload_round_qty_set ( upload_round_qty_set ),
|
||||
.reset_package_id ( reset_package_id ),
|
||||
.package_overtime_ms ( overtime_ms ),
|
||||
|
||||
.s_axis_trigger_tdata ( s_axis_trig_intan_tdata ),
|
||||
.s_axis_trigger_tvalid ( s_axis_trig_intan_tvalid ),
|
||||
.s_axis_trigger_tready ( s_axis_trig_intan_tready ),
|
||||
|
||||
.s_axis_eeg_tdata ( m_axis_eeg_tdata ),
|
||||
.s_axis_eeg_tlast ( m_axis_eeg_tlast ),
|
||||
.s_axis_eeg_tready ( m_axis_eeg_intan_tready),
|
||||
.s_axis_eeg_tvalid ( m_axis_eeg_tvalid ),
|
||||
|
||||
.m_axis_record_tfull ( m_axis_intan_tfull ),
|
||||
.m_axis_record_tdata ( m_axis_intan_tdata ),
|
||||
.m_axis_record_tkeep ( m_axis_intan_tkeep ),
|
||||
.m_axis_record_tlast ( m_axis_intan_tlast ),
|
||||
.m_axis_record_tready ( m_axis_intan_tready ),
|
||||
.m_axis_record_tvalid ( m_axis_intan_tvalid )
|
||||
);
|
||||
|
||||
//*****************************************************************************
|
||||
// Wire assignment
|
||||
//*****************************************************************************
|
||||
assign s_axis_trig_ql_tdata = s_axis_trigger_tdata;
|
||||
assign s_axis_trig_ql_tvalid = s_axis_trigger_tvalid;
|
||||
assign s_axis_trig_intan_tdata = s_axis_trigger_tdata;
|
||||
assign s_axis_trig_intan_tvalid = s_axis_trigger_tvalid;
|
||||
assign s_axis_trigger_tready = s_axis_trig_ql_tready || s_axis_trig_intan_tready;
|
||||
|
||||
assign m_axis_eeg_tready = m_axis_eeg_ql_tready || m_axis_eeg_intan_tready;
|
||||
|
||||
assign m_axis_record_tdata = (protocol_sel)? m_axis_ql_tdata : m_axis_intan_tdata;
|
||||
assign m_axis_record_tkeep = (protocol_sel)? m_axis_ql_tkeep : m_axis_intan_tkeep;
|
||||
assign m_axis_record_tlast = (protocol_sel)? m_axis_ql_tlast : m_axis_intan_tlast;
|
||||
assign m_axis_record_tvalid = (protocol_sel)? m_axis_ql_tvalid: m_axis_intan_tvalid;
|
||||
assign m_axis_ql_tfull = m_axis_record_tfull;
|
||||
assign m_axis_intan_tfull = m_axis_record_tfull;
|
||||
assign m_axis_ql_tready = m_axis_record_tready;
|
||||
assign m_axis_intan_tready = m_axis_record_tready;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,471 @@
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module upload_top#
|
||||
(
|
||||
parameter CLK_PERIOD = 10 ,
|
||||
parameter CHANNLE_QTY = 64 ,
|
||||
parameter PRE_MSG_LEN = 128
|
||||
)
|
||||
(
|
||||
input clk ,
|
||||
input rst_n ,
|
||||
|
||||
input [13-1:0] bram_addr ,
|
||||
input bram_clk ,
|
||||
input [32-1:0] bram_din ,
|
||||
output [32-1:0] bram_dout ,
|
||||
input bram_en ,
|
||||
input bram_rst ,
|
||||
input [ 4-1:0] bram_we ,
|
||||
|
||||
output interrupt ,
|
||||
|
||||
input [32-1:0] s_axis_trigger_tdata ,
|
||||
input s_axis_trigger_tvalid ,
|
||||
output reg s_axis_trigger_tready ,
|
||||
|
||||
input [32-1:0] s_axis_eeg16_tdata ,
|
||||
input s_axis_eeg16_tlast ,
|
||||
output s_axis_eeg16_tready ,
|
||||
input s_axis_eeg16_tvalid ,
|
||||
|
||||
input [32-1:0] s_axis_eeg24_tdata ,
|
||||
input s_axis_eeg24_tlast ,
|
||||
output s_axis_eeg24_tready ,
|
||||
input s_axis_eeg24_tvalid ,
|
||||
|
||||
input [32-1:0] s_axis_emg_tdata ,
|
||||
input s_axis_emg_tlast ,
|
||||
output s_axis_emg_tready ,
|
||||
input s_axis_emg_tvalid ,
|
||||
|
||||
input [48-1:0] accel_data ,
|
||||
|
||||
input m_axis_record_tfull ,
|
||||
output reg [ 8-1:0] m_axis_record_tdata ,
|
||||
output reg [ 1-1:0] m_axis_record_tkeep ,
|
||||
output reg m_axis_record_tlast ,
|
||||
input m_axis_record_tready ,
|
||||
output reg m_axis_record_tvalid ,
|
||||
|
||||
output [ 4-1:0] debug_sig
|
||||
);
|
||||
|
||||
//*****************************************************************************
|
||||
// localparam definition
|
||||
//*****************************************************************************
|
||||
localparam ST_IDLE = 4'd0 ;
|
||||
localparam ST_MSG_HEAD = 4'd1 ;
|
||||
localparam ST_WAIT = 4'd2 ;
|
||||
localparam ST_READ_TRIGGER = 4'd3 ;
|
||||
localparam ST_MSG_TRIGGER = 4'd4 ;
|
||||
localparam ST_MSG_RECORD = 4'd5 ;
|
||||
localparam ST_MSG_END = 4'd6 ;
|
||||
localparam ST_ADDITIONAL = 4'd7 ;
|
||||
|
||||
localparam ADDL_NUM = 12 ;
|
||||
|
||||
//*****************************************************************************
|
||||
// Internal register and wire declarations
|
||||
//*****************************************************************************
|
||||
wire pulse_ms ;
|
||||
wire [64-1:0] run_time_ms ;
|
||||
wire reset_package_id ;
|
||||
wire [32-1:0] package_overtime_ms ;
|
||||
reg [32-1:0] overtime_ms ;
|
||||
reg [32-1:0] package_id ;
|
||||
|
||||
wire [ 8*PRE_MSG_LEN-1:0] pre_message_array ;
|
||||
wire [ 8-1:0] pre_message[0:PRE_MSG_LEN-1];
|
||||
wire [ 8-1:0] pre_message_length ;
|
||||
|
||||
reg [ 4-1:0] cstate ;
|
||||
reg [ 4-1:0] nstate ;
|
||||
|
||||
wire [ 8*CHANNLE_QTY-1:0] ch_mapping2pc_array ;
|
||||
wire [ CHANNLE_QTY-1:0] upload_ch_array ;
|
||||
wire select_eeg24 ;
|
||||
wire [16-1:0] message_end ;
|
||||
|
||||
reg [32-1:0] trigger_word ;
|
||||
wire [ 8-1:0] trigger_byte[0:3] ;
|
||||
|
||||
wire [ 8-1:0] msg_end[0:1] ;
|
||||
|
||||
wire [32-1:0] upload_round_qty_set ;
|
||||
reg [32-1:0] upload_round_qty ;
|
||||
|
||||
reg [32-1:0] upload_bytes_cnt ;
|
||||
wire [32-1:0] upload_bytes_cnt_add1 ;
|
||||
reg [32-1:0] upload_rounds_cnt ;
|
||||
reg [32-1:0] upload_record_bytes_cnt ;
|
||||
|
||||
wire [16-1:0] crc16_out ;
|
||||
reg [16-1:0] crc16 ;
|
||||
|
||||
wire [ 8-1:0] upload_addl[0:ADDL_NUM-1] ;
|
||||
|
||||
reg [ 8-1:0] byte_cnt ;
|
||||
|
||||
wire [ 8-1:0] m_axis_eeg_tdata ;
|
||||
wire m_axis_eeg_tlast ;
|
||||
reg m_axis_eeg_tready ;
|
||||
wire m_axis_eeg_tvalid ;
|
||||
|
||||
reg upload_break ;
|
||||
reg upload_disable ;
|
||||
|
||||
wire [ 4-1:0] debug_sig_sort ;
|
||||
|
||||
genvar i;
|
||||
|
||||
//*****************************************************************************
|
||||
// Instantiation
|
||||
//*****************************************************************************
|
||||
upload_config#
|
||||
(
|
||||
.CHANNLE_QTY ( CHANNLE_QTY ),
|
||||
.PRE_MSG_LEN ( PRE_MSG_LEN )
|
||||
)
|
||||
u_upload_config
|
||||
(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
|
||||
.bram_addr ( bram_addr ),
|
||||
.bram_clk ( bram_clk ),
|
||||
.bram_din ( bram_din ),
|
||||
.bram_dout ( bram_dout ),
|
||||
.bram_en ( bram_en ),
|
||||
.bram_rst ( bram_rst ),
|
||||
.bram_we ( bram_we ),
|
||||
|
||||
.pre_message_array ( pre_message_array ),
|
||||
.pre_message_length ( pre_message_length ),
|
||||
.upload_round_qty_set ( upload_round_qty_set ),
|
||||
.ch_mapping2pc_array ( ch_mapping2pc_array ),
|
||||
.upload_ch_array ( upload_ch_array ),
|
||||
.select_eeg24 ( select_eeg24 ),
|
||||
.reset_package_id ( reset_package_id ),
|
||||
.package_overtime_ms ( package_overtime_ms ),
|
||||
.message_end ( message_end ) //TODO: unused
|
||||
);
|
||||
|
||||
upload_sort#
|
||||
(
|
||||
.CLK_PERIOD ( CLK_PERIOD ),
|
||||
.CHANNLE_QTY ( CHANNLE_QTY )
|
||||
)
|
||||
u_upload_sort
|
||||
(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
|
||||
.ch_mapping2pc_array ( ch_mapping2pc_array ),
|
||||
.upload_ch_array ( upload_ch_array ),
|
||||
.select_eeg24 ( 1'b1 ),
|
||||
|
||||
//------------------------------------------ PL logic
|
||||
.s_axis_eeg16_tdata ( s_axis_eeg16_tdata ),
|
||||
.s_axis_eeg16_tlast ( s_axis_eeg16_tlast ),
|
||||
.s_axis_eeg16_tready ( s_axis_eeg16_tready ),
|
||||
.s_axis_eeg16_tvalid ( s_axis_eeg16_tvalid ),
|
||||
|
||||
.s_axis_eeg24_tdata ( s_axis_eeg24_tdata ),
|
||||
.s_axis_eeg24_tlast ( s_axis_eeg24_tlast ),
|
||||
.s_axis_eeg24_tready ( s_axis_eeg24_tready ),
|
||||
.s_axis_eeg24_tvalid ( s_axis_eeg24_tvalid ),
|
||||
|
||||
//------------------------------------------ PC logic
|
||||
.m_axis_eeg_tdata ( m_axis_eeg_tdata ),
|
||||
.m_axis_eeg_tlast ( m_axis_eeg_tlast ),
|
||||
.m_axis_eeg_tready ( m_axis_eeg_tready ),
|
||||
.m_axis_eeg_tvalid ( m_axis_eeg_tvalid ),
|
||||
|
||||
.debug_sig_sort ( debug_sig_sort )
|
||||
);
|
||||
|
||||
run_time#
|
||||
(
|
||||
.CLK_PERIOD ( CLK_PERIOD )
|
||||
)
|
||||
u_run_time
|
||||
(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
|
||||
.pulse_ms ( pulse_ms ),
|
||||
.run_time_ms ( run_time_ms )
|
||||
);
|
||||
|
||||
//*****************************************************************************
|
||||
// Function
|
||||
//*****************************************************************************
|
||||
function automatic [15:0] crc16_d8;
|
||||
input [15:0] crcIn;
|
||||
input [7:0] data;
|
||||
begin
|
||||
crc16_d8[0] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ crcIn[7] ^ crcIn[8] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7];
|
||||
crc16_d8[1] = crcIn[9];
|
||||
crc16_d8[2] = crcIn[10];
|
||||
crc16_d8[3] = crcIn[11];
|
||||
crc16_d8[4] = crcIn[12];
|
||||
crc16_d8[5] = crcIn[13];
|
||||
crc16_d8[6] = crcIn[0] ^ crcIn[14] ^ data[0];
|
||||
crc16_d8[7] = crcIn[0] ^ crcIn[1] ^ crcIn[15] ^ data[0] ^ data[1];
|
||||
crc16_d8[8] = crcIn[1] ^ crcIn[2] ^ data[1] ^ data[2];
|
||||
crc16_d8[9] = crcIn[2] ^ crcIn[3] ^ data[2] ^ data[3];
|
||||
crc16_d8[10] = crcIn[3] ^ crcIn[4] ^ data[3] ^ data[4];
|
||||
crc16_d8[11] = crcIn[4] ^ crcIn[5] ^ data[4] ^ data[5];
|
||||
crc16_d8[12] = crcIn[5] ^ crcIn[6] ^ data[5] ^ data[6];
|
||||
crc16_d8[13] = crcIn[6] ^ crcIn[7] ^ data[6] ^ data[7];
|
||||
crc16_d8[14] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6];
|
||||
crc16_d8[15] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ crcIn[7] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7];
|
||||
end
|
||||
endfunction
|
||||
|
||||
//*****************************************************************************
|
||||
always@( posedge clk or negedge rst_n ) begin
|
||||
if( !rst_n ) cstate <= ST_IDLE;
|
||||
else cstate <= nstate;
|
||||
end
|
||||
|
||||
always@( * ) begin
|
||||
case ( cstate )
|
||||
ST_IDLE:
|
||||
if ( m_axis_eeg_tvalid )
|
||||
nstate <= ST_MSG_HEAD;
|
||||
else
|
||||
nstate <= ST_IDLE;
|
||||
ST_MSG_HEAD:
|
||||
if ( byte_cnt == pre_message_length - 1 )
|
||||
nstate <= ST_WAIT;
|
||||
else
|
||||
nstate <= ST_MSG_HEAD;
|
||||
ST_WAIT:
|
||||
if ( upload_rounds_cnt == upload_round_qty || overtime_ms == package_overtime_ms )
|
||||
nstate <= ST_MSG_END;
|
||||
else if ( m_axis_record_tfull && !upload_disable )
|
||||
nstate <= ST_MSG_END;
|
||||
else if ( m_axis_eeg_tvalid )
|
||||
nstate <= ST_READ_TRIGGER;
|
||||
else
|
||||
nstate <= ST_WAIT;
|
||||
ST_READ_TRIGGER:
|
||||
nstate <= ST_MSG_TRIGGER;
|
||||
ST_MSG_TRIGGER:
|
||||
if ( byte_cnt == 4-1 )
|
||||
nstate <= ST_MSG_RECORD;
|
||||
else
|
||||
nstate <= ST_MSG_TRIGGER;
|
||||
ST_MSG_RECORD:
|
||||
if ( m_axis_eeg_tready && m_axis_eeg_tvalid && m_axis_eeg_tlast )
|
||||
nstate <= ST_WAIT;
|
||||
else
|
||||
nstate <= ST_MSG_RECORD;
|
||||
ST_MSG_END:
|
||||
if ( byte_cnt == 2-1 )
|
||||
nstate <= ST_ADDITIONAL;
|
||||
else
|
||||
nstate <= ST_MSG_END;
|
||||
ST_ADDITIONAL:
|
||||
if ( byte_cnt == ADDL_NUM-1 )
|
||||
nstate <= upload_break? ST_WAIT:ST_IDLE;
|
||||
else
|
||||
nstate <= ST_ADDITIONAL;
|
||||
default:
|
||||
nstate <= ST_IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_break <= 1'b0;
|
||||
else if ( cstate == ST_WAIT && (upload_rounds_cnt != upload_round_qty && overtime_ms != package_overtime_ms) && m_axis_record_tfull && !upload_disable )
|
||||
upload_break <= 1'b1;
|
||||
else if ( cstate == ST_ADDITIONAL && nstate != ST_ADDITIONAL )
|
||||
upload_break <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_disable <= 1'b0;
|
||||
else if ( cstate == ST_ADDITIONAL && nstate != ST_ADDITIONAL )
|
||||
upload_disable <= m_axis_record_tfull;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
package_id <= 0;
|
||||
else if ( reset_package_id )
|
||||
package_id <= 0;
|
||||
else if ( cstate == ST_MSG_END && nstate == ST_ADDITIONAL )
|
||||
package_id <= package_id + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_round_qty <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
upload_round_qty <= upload_round_qty_set;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
s_axis_trigger_tready <= 1'b0;
|
||||
else if ( nstate == ST_READ_TRIGGER )
|
||||
s_axis_trigger_tready <= 1'b1;
|
||||
else
|
||||
s_axis_trigger_tready <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
trigger_word <= 0;
|
||||
else if ( s_axis_trigger_tvalid && s_axis_trigger_tready )
|
||||
trigger_word <= s_axis_trigger_tdata;
|
||||
else if ( cstate != ST_MSG_TRIGGER )
|
||||
trigger_word <= 0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
m_axis_eeg_tready <= 1'b0;
|
||||
else if ( cstate == ST_MSG_RECORD || nstate == ST_MSG_RECORD )
|
||||
m_axis_eeg_tready <= 1'b1;
|
||||
else
|
||||
m_axis_eeg_tready <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_rounds_cnt <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
upload_rounds_cnt <= 0;
|
||||
else if ( m_axis_eeg_tready && m_axis_eeg_tvalid && m_axis_eeg_tlast )
|
||||
upload_rounds_cnt <= upload_rounds_cnt + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
overtime_ms <= 0;
|
||||
else if ( m_axis_eeg_tvalid )
|
||||
overtime_ms <= 0;
|
||||
else if ( pulse_ms )
|
||||
overtime_ms <= overtime_ms + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
byte_cnt <= 0;
|
||||
else if ( cstate != nstate )
|
||||
byte_cnt <= 0;
|
||||
else
|
||||
byte_cnt <= byte_cnt + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n ) begin
|
||||
m_axis_record_tdata <= 0;
|
||||
m_axis_record_tkeep <= 1'b1;
|
||||
m_axis_record_tvalid <= 1'b0;
|
||||
end else if ( cstate == ST_MSG_HEAD ) begin
|
||||
m_axis_record_tdata <= pre_message[byte_cnt];
|
||||
m_axis_record_tvalid <= upload_disable? 1'b0:1;
|
||||
end else if ( cstate == ST_MSG_TRIGGER ) begin
|
||||
m_axis_record_tdata <= trigger_byte[byte_cnt];
|
||||
m_axis_record_tvalid <= upload_disable? 1'b0:1;
|
||||
end else if ( cstate == ST_MSG_RECORD && m_axis_eeg_tvalid && m_axis_eeg_tready ) begin
|
||||
m_axis_record_tdata <= m_axis_eeg_tdata;
|
||||
m_axis_record_tvalid <= upload_disable? 1'b0:1;
|
||||
end else if ( cstate == ST_MSG_END ) begin
|
||||
m_axis_record_tdata <= msg_end[byte_cnt];
|
||||
m_axis_record_tvalid <= upload_disable? 1'b0:1;
|
||||
end else if ( cstate == ST_ADDITIONAL ) begin
|
||||
m_axis_record_tdata <= upload_addl[byte_cnt];
|
||||
m_axis_record_tvalid <= upload_disable? 1'b0:1;
|
||||
end else
|
||||
m_axis_record_tvalid <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk ) begin
|
||||
if ( cstate == ST_IDLE )
|
||||
crc16 <= 16'hFFFF;
|
||||
else if ( cstate != ST_MSG_END && m_axis_record_tvalid && m_axis_record_tready )
|
||||
crc16 <= crc16_out;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n ) begin
|
||||
m_axis_record_tlast <= 1'b0;
|
||||
end else if ( cstate == ST_ADDITIONAL && (byte_cnt == ADDL_NUM-1) ) begin
|
||||
m_axis_record_tlast <= 1'b1;
|
||||
end else
|
||||
m_axis_record_tlast <= 1'b0;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_bytes_cnt <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
upload_bytes_cnt <= 0;
|
||||
else if ( (cstate != ST_ADDITIONAL) && m_axis_record_tvalid && m_axis_record_tready )
|
||||
upload_bytes_cnt <= upload_bytes_cnt + 1'b1;
|
||||
end
|
||||
|
||||
always @ ( posedge clk or negedge rst_n ) begin
|
||||
if ( !rst_n )
|
||||
upload_record_bytes_cnt <= 0;
|
||||
else if ( cstate == ST_IDLE )
|
||||
upload_record_bytes_cnt <= 0;
|
||||
else if ( cstate == ST_MSG_RECORD && m_axis_eeg_tvalid && m_axis_eeg_tready )
|
||||
upload_record_bytes_cnt <= upload_record_bytes_cnt + 1'b1;
|
||||
end
|
||||
|
||||
//*****************************************************************************
|
||||
// Wire assignment
|
||||
//*****************************************************************************
|
||||
//pre_message[21:14] is run_time_ms
|
||||
//pre_message[26:23] is package_id
|
||||
generate
|
||||
for(i=0;i<PRE_MSG_LEN;i=i+1) begin : pre_msg
|
||||
if ( i > 13 && i < 22 )
|
||||
assign pre_message[i] = run_time_ms[8*(i-14)+7 : 8*(i-14)];
|
||||
else if ( i > 22 && i < 27 )
|
||||
assign pre_message[i] = package_id[8*(i-23)+7 : 8*(i-23)];
|
||||
else
|
||||
assign pre_message[i] = pre_message_array[8*i+7 : 8*i];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign trigger_byte[0] = trigger_word[ 7: 0];
|
||||
assign trigger_byte[1] = trigger_word[15: 8];
|
||||
assign trigger_byte[2] = trigger_word[23:16];
|
||||
assign trigger_byte[3] = trigger_word[31:24];
|
||||
|
||||
assign crc16_out = crc16_d8(crc16, m_axis_record_tdata);
|
||||
|
||||
assign msg_end[0] = crc16[15: 8];
|
||||
assign msg_end[1] = crc16[ 7: 0];
|
||||
|
||||
assign upload_bytes_cnt_add1 = upload_bytes_cnt + 1'b1;
|
||||
|
||||
assign upload_addl[ 0] = upload_bytes_cnt_add1[ 7: 0];
|
||||
assign upload_addl[ 1] = upload_bytes_cnt_add1[15: 8];
|
||||
assign upload_addl[ 2] = upload_bytes_cnt_add1[23:16];
|
||||
assign upload_addl[ 3] = upload_bytes_cnt_add1[31:24];
|
||||
assign upload_addl[ 4] = upload_rounds_cnt[ 7: 0];
|
||||
assign upload_addl[ 5] = upload_rounds_cnt[15: 8];
|
||||
assign upload_addl[ 6] = upload_rounds_cnt[23:16];
|
||||
assign upload_addl[ 7] = upload_rounds_cnt[31:24];
|
||||
assign upload_addl[ 8] = upload_record_bytes_cnt[ 7: 0];
|
||||
assign upload_addl[ 9] = upload_record_bytes_cnt[15: 8];
|
||||
assign upload_addl[10] = upload_record_bytes_cnt[23:16];
|
||||
assign upload_addl[11] = upload_record_bytes_cnt[31:24];
|
||||
|
||||
assign debug_sig[0] = m_axis_record_tvalid;
|
||||
assign debug_sig[1] = m_axis_record_tready;
|
||||
assign debug_sig[2] = m_axis_record_tfull;
|
||||
assign debug_sig[3] = 1'b0;
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user