上传PL工程
This commit is contained in:
@@ -0,0 +1,76 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module trigger_top_tb();
|
||||
|
||||
//*****************************************************************************
|
||||
// Parameter definition
|
||||
//*****************************************************************************
|
||||
localparam T_CLK = 10 ; //ns
|
||||
|
||||
localparam DATA_WIDTH = 64 ;
|
||||
|
||||
//*****************************************************************************
|
||||
// Internal register and wire declarations
|
||||
//*****************************************************************************
|
||||
reg clk ;
|
||||
reg rst_n ;
|
||||
|
||||
reg [32-1:0] trigger_in_int ;
|
||||
reg [32-1:0] trigger_in_ext ;
|
||||
|
||||
wire [32-1:0] trigger_tdata ;
|
||||
wire trigger_tvalid ;
|
||||
|
||||
//*****************************************************************************
|
||||
// Instantiation
|
||||
//*****************************************************************************
|
||||
trigger_top#
|
||||
(
|
||||
.CLK_PERIOD ( T_CLK )
|
||||
)
|
||||
DUT
|
||||
(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
|
||||
.trigger_in_int ( trigger_in_int ),
|
||||
.trigger_in_ext ( trigger_in_ext ),
|
||||
|
||||
.trigger_tdata ( trigger_tdata ),
|
||||
.trigger_tvalid ( trigger_tvalid )
|
||||
);
|
||||
|
||||
//*****************************************************************************
|
||||
// Wire assignment
|
||||
//*****************************************************************************
|
||||
always #( T_CLK/2.0 ) clk = !clk;
|
||||
|
||||
initial begin
|
||||
Initial();
|
||||
#100 rst_n = 0;
|
||||
#100 rst_n = 1;
|
||||
#100
|
||||
|
||||
while (1) begin
|
||||
trigger_in_ext <= trigger_in_ext + 1'b1;
|
||||
#80_060;
|
||||
trigger_in_int <= trigger_in_int + 1'b1;
|
||||
#20_000;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
//*****************************************************************************
|
||||
// Task
|
||||
//*****************************************************************************
|
||||
task Initial;
|
||||
begin
|
||||
clk <= 1'b0 ;
|
||||
rst_n <= 1'b0 ;
|
||||
|
||||
trigger_in_int <= 32'h123;
|
||||
trigger_in_ext <= 0;
|
||||
end
|
||||
endtask
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user