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This commit is contained in:
chenmin
2024-10-28 13:14:49 +08:00
parent d9ea3b1c85
commit 25cdd3c44c
3437 changed files with 10334573 additions and 0 deletions
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c64_pro.srcs/sources_1/rtl/switch/adg1414_if.v
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`timescale 1 ns / 1 ps
module adg1414_if#
(
parameter CLK_PERIOD = 10 ,
parameter CLK_DIV = 4 , // max: 255
parameter DATA_WIDTH = 64 ,
parameter T_SYNC_MIN = 100 // Unit: ns
)
(
input clk ,
input rst_n ,
output reg s_tready ,
input s_tvalid ,
input [DATA_WIDTH-1:0] s_tdata ,
output sync ,
output reg sclk ,
output sdin
);
//*****************************************************************************
// Parameter definition
//*****************************************************************************
localparam CNT_POS = CLK_DIV/2 ;
localparam CNT_NEG = 0 ;
localparam IDLE = 8'd0 ;
localparam TRANS_ST = 8'd1 ;
localparam END_ST = 8'd2 ;
localparam T_DELAY = T_SYNC_MIN/CLK_PERIOD ;
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
reg [ 4-1:0] cstate ;
reg [ 4-1:0] nstate ;
reg [DATA_WIDTH-1:0] tx_data ;
reg clk_en ;
reg [ 8-1:0] cnt ;
reg sck_pos ;
reg sck_neg ;
reg [ 8-1:0] trans_cnt ;
reg [ 8-1:0] t_cnt ;
//*****************************************************************************
// Instantiation
//*****************************************************************************
//*****************************************************************************
always@( posedge clk or negedge rst_n ) begin
if( !rst_n ) cstate <= IDLE;
else cstate <= nstate;
end
always@( * ) begin
case ( cstate )
IDLE:
if ( s_tvalid )
nstate <= TRANS_ST;
else
nstate <= IDLE;
TRANS_ST:
if( (trans_cnt == 0) && sck_pos )
nstate <= END_ST;
else
nstate <= TRANS_ST;
END_ST:
if (t_cnt == T_DELAY-1)
nstate <= IDLE;
else
nstate <= END_ST;
default:
nstate <= IDLE;
endcase
end
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n )
s_tready <= 1'b0;
else if ( nstate == IDLE )
s_tready <= 1'b1;
else if ( cstate == IDLE && nstate == IDLE )
s_tready <= 1'b1;
else
s_tready <= 1'b0;
end
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n ) begin
tx_data <= 0;
end else if ( s_tready && s_tvalid ) begin
tx_data <= s_tdata;
end
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n )
clk_en <= 0;
else if ( ((cstate == IDLE) && (nstate == TRANS_ST)) || ((cstate == TRANS_ST) && (nstate != END_ST)) )
clk_en <= 1'b1;
else if ( nstate == END_ST )
clk_en <= 1'b0;
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n )
cnt <= 0;
else if ( !clk_en )
cnt <= 0;
else if ( cnt == CLK_DIV-1 )
cnt <= 0;
else
cnt <= cnt + 1;
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n )
sck_pos <= 0;
else if ( clk_en && (cnt == CNT_POS) )
sck_pos <= 1;
else
sck_pos <= 0;
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n )
sck_neg <= 0;
else if ( clk_en && (cnt == CNT_NEG) )
sck_neg <= 1;
else
sck_neg <= 0;
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n )
sclk <= 1'b1;
else if ( sck_pos && nstate == TRANS_ST || cstate == END_ST )
sclk <= 1'b1;
else if ( sck_neg )
sclk <= 1'b0;
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n )
trans_cnt <= DATA_WIDTH - 1;
else if ( cstate == IDLE )
trans_cnt <= DATA_WIDTH - 1;
else if ( sck_pos && (trans_cnt != 0) )
trans_cnt <= trans_cnt - 1'b1;
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n )
t_cnt <= 0;
else if ( cstate != END_ST )
t_cnt <= 0;
else
t_cnt <= t_cnt + 1'b1;
end
//*****************************************************************************
// Wire assignment
//*****************************************************************************
assign sync = (cstate == IDLE || cstate == END_ST)? 1'b1 : 1'b0;
assign sdin = tx_data[trans_cnt];
endmodule
c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v
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`timescale 1ns/1ps
module adg1414_if_tb();
//*****************************************************************************
// Parameter definition
//*****************************************************************************
localparam T_CLK = 10 ; //ns
localparam DATA_WIDTH = 64 ;
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
reg clk ;
reg rst_n ;
wire s_tready ;
reg [DATA_WIDTH - 1:0] s_tdata ;
reg s_tvalid ;
wire sync ;
wire sclk ;
wire sdin ;
reg tx_data ;
//*****************************************************************************
// Wire assignment
//*****************************************************************************
always #( T_CLK/2.0 ) clk = !clk;
initial begin
Initial();
#100 rst_n = 0;
#100 rst_n = 1;
while (1) begin
#3_000
@ ( posedge clk );
s_tdata <= s_tdata + 1'b1;
s_tvalid <= 1'b1;
wait ( s_tready );
@ ( posedge clk );
s_tvalid <= 1'b0;
@ ( posedge clk );
end
end
//*****************************************************************************
// Task
//*****************************************************************************
task Initial;
begin
clk <= 1'b0 ;
rst_n <= 1'b0 ;
s_tvalid <= 1'b0 ;
s_tdata <= {DATA_WIDTH{1'b1}} ;
s_tdata[0] <= 1'b0 ;
end
endtask
//*****************************************************************************
// Instantiation
//*****************************************************************************
adg1414_if#
(
.CLK_PERIOD ( 10 ),
.CLK_DIV ( 4 ),
.DATA_WIDTH ( DATA_WIDTH )
)
DUT
(
.clk ( clk ),
.rst_n ( rst_n ),
.s_tready ( s_tready ),
.s_tvalid ( s_tvalid ),
.s_tdata ( s_tdata ),
.sync ( sync ),
.sclk ( sclk ),
.sdin ( sdin )
);
endmodule
c64_pro.srcs/sources_1/rtl/switch/channel_switch.v
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`timescale 1 ns / 1 ps
module channel_switch#
(
parameter CLK_PERIOD = 10
)
(
input clk ,
input rst_n ,
input enable ,
input data_sel ,
input [64-1:0] data_0 ,
input [64-1:0] data_1 ,
output [64-1:0] state ,
output sync ,
output sclk ,
output sdin ,
input sdo
);
//*****************************************************************************
// Parameter definition
//*****************************************************************************
localparam IDLE = 4'b0000 ;
localparam MON_ST = 4'd0001 ;
localparam CFG_ST = 4'd0011 ;
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
reg [64-1:0] new_data ;
wire [64-1:0] new_data_map ;
reg [64-1:0] new_data_r ;
reg [64-1:0] cur_data ;
reg [ 4-1:0] cstate ;
wire s_tready ;
reg s_tvalid ;
reg [64-1:0] s_tdata ;
// wire [64-1:0] probe_out0 ;
//*****************************************************************************
// Instantiation
//*****************************************************************************
adg1414_if#
(
.CLK_PERIOD ( CLK_PERIOD ),
.CLK_DIV ( 20 ),
.DATA_WIDTH ( 64 )
)
u_adg1414_if
(
.clk ( clk ),
.rst_n ( rst_n ),
.s_tready ( s_tready ),
.s_tvalid ( s_tvalid ),
.s_tdata ( s_tdata ),
.sync ( sync ),
.sclk ( sclk ),
.sdin ( sdin )
);
// vio_0 vio_0_switch
// (
// .clk ( clk ), // input wire clk
// .probe_in0 ( enable ), // input wire [0 : 0] probe_in0
// .probe_in1 ( data_sel ), // input wire [0 : 0] probe_in1
// .probe_in2 ( data_0 ), // input wire [63 : 0] probe_in2
// .probe_in3 ( data_1 ), // input wire [63 : 0] probe_in3
// .probe_in4 ( new_data ), // input wire [63 : 0] probe_in4
// .probe_in5 ( state ), // input wire [63 : 0] probe_in5
// .probe_out0 ( probe_out0 ) // output wire [63 : 0] probe_out0
// );
//*****************************************************************************
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n )
new_data <= 0;
else if (!data_sel)
new_data = data_0;//probe_out0;//
else
new_data = data_1;
end
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n ) begin
cstate <= 4'd0;
end else begin
case (cstate)
IDLE:
if ( enable )
cstate <= MON_ST;
else
cstate <= IDLE;
MON_ST:
if ( !enable )
cstate <= IDLE;
else if (cur_data != new_data_map)
cstate <= CFG_ST;
else
cstate <= MON_ST;
CFG_ST:
if ( s_tvalid && s_tready )
cstate <= IDLE;
default:
cstate <= IDLE;
endcase
end
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n )
new_data_r <= 0;
else if (enable && cstate == MON_ST)
new_data_r <= new_data_map;
end
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n ) begin
s_tvalid <= 1'b0;
s_tdata <= 0;
end else if ( s_tvalid && s_tready ) begin
s_tvalid <= 1'b0;
end else if ( cstate == CFG_ST ) begin
s_tvalid <= 1'b1;
s_tdata <= new_data_r;
end
end
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n ) begin
cur_data <= 0;
end else if ( s_tvalid && s_tready ) begin
cur_data <= s_tdata;
end
end
//*****************************************************************************
// Wire assignment
//*****************************************************************************
assign state = cur_data;
assign new_data_map[ 6] = new_data[ 0];
assign new_data_map[ 7] = new_data[ 1];
assign new_data_map[ 5] = new_data[ 2];
assign new_data_map[ 4] = new_data[ 3];
assign new_data_map[ 3] = new_data[ 4];
assign new_data_map[ 2] = new_data[ 5];
assign new_data_map[ 1] = new_data[ 6];
assign new_data_map[ 0] = new_data[ 7];
assign new_data_map[14] = new_data[ 8];
assign new_data_map[15] = new_data[ 9];
assign new_data_map[13] = new_data[10];
assign new_data_map[11] = new_data[11];
assign new_data_map[ 8] = new_data[12];
assign new_data_map[10] = new_data[13];
assign new_data_map[ 9] = new_data[14];
assign new_data_map[12] = new_data[15];
assign new_data_map[38] = new_data[16];
assign new_data_map[39] = new_data[17];
assign new_data_map[37] = new_data[18];
assign new_data_map[36] = new_data[19];
assign new_data_map[35] = new_data[20];
assign new_data_map[34] = new_data[21];
assign new_data_map[33] = new_data[22];
assign new_data_map[32] = new_data[23];
assign new_data_map[46] = new_data[24];
assign new_data_map[47] = new_data[25];
assign new_data_map[45] = new_data[26];
assign new_data_map[43] = new_data[27];
assign new_data_map[40] = new_data[28];
assign new_data_map[42] = new_data[29];
assign new_data_map[41] = new_data[30];
assign new_data_map[44] = new_data[31];
assign new_data_map[22] = new_data[32];
assign new_data_map[23] = new_data[33];
assign new_data_map[21] = new_data[34];
assign new_data_map[20] = new_data[35];
assign new_data_map[19] = new_data[36];
assign new_data_map[18] = new_data[37];
assign new_data_map[17] = new_data[38];
assign new_data_map[16] = new_data[39];
assign new_data_map[30] = new_data[40];
assign new_data_map[31] = new_data[41];
assign new_data_map[29] = new_data[42];
assign new_data_map[27] = new_data[43];
assign new_data_map[24] = new_data[44];
assign new_data_map[26] = new_data[45];
assign new_data_map[25] = new_data[46];
assign new_data_map[28] = new_data[47];
assign new_data_map[54] = new_data[48];
assign new_data_map[55] = new_data[49];
assign new_data_map[53] = new_data[50];
assign new_data_map[52] = new_data[51];
assign new_data_map[50] = new_data[52];
assign new_data_map[51] = new_data[53];
assign new_data_map[49] = new_data[54];
assign new_data_map[48] = new_data[55];
assign new_data_map[62] = new_data[56];
assign new_data_map[63] = new_data[57];
assign new_data_map[61] = new_data[58];
assign new_data_map[59] = new_data[59];
assign new_data_map[56] = new_data[60];
assign new_data_map[58] = new_data[61];
assign new_data_map[57] = new_data[62];
assign new_data_map[60] = new_data[63];
endmodule
c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v
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`timescale 1ns/1ps
module channel_switch_tb();
//*****************************************************************************
// Parameter definition
//*****************************************************************************
localparam T_CLK = 10 ; //ns
localparam DATA_WIDTH = 64 ;
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
reg clk ;
reg rst_n ;
reg [64-1:0] data_0 ;
reg [64-1:0] data_1 ;
wire [64-1:0] state ;
wire adg1414_spi_cs ;
wire adg1414_spi_sclk ;
wire adg1414_spi_mosi ;
//*****************************************************************************
// Wire assignment
//*****************************************************************************
always #( T_CLK/2.0 ) clk = !clk;
initial begin
Initial();
#100 rst_n = 0;
#100 rst_n = 1;
#100;
@ ( posedge clk );
data_0 <= 64'h8000000000000002;
while (1) begin
@ ( posedge clk );
// data_0 <= data_0 + 1'b1;
#5_000;
end
end
//*****************************************************************************
// Task
//*****************************************************************************
task Initial;
begin
clk <= 1'b0 ;
rst_n <= 1'b0 ;
data_0 <= 64'h0000000000000000;
data_1 <= 64'hFFFFFFFFFFFFFFFF;
end
endtask
//*****************************************************************************
// Instantiation
//*****************************************************************************
channel_switch#
(
.CLK_PERIOD ( T_CLK )
)
DUT
(
.clk ( clk ),
.rst_n ( rst_n ),
.enable ( 1'b1 ),
.data_sel ( 1'b0 ),
.data_0 ( data_0 ),
.data_1 ( data_1 ),
.state ( state ),
.sync ( adg1414_spi_cs ),
.sclk ( adg1414_spi_sclk ),
.sdin ( adg1414_spi_mosi ),
.sdo ( 1'b0 )
);
endmodule