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chenmin
2024-10-28 13:14:49 +08:00
parent d9ea3b1c85
commit 25cdd3c44c
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c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v
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`timescale 1ns/1ps
module transmit_config_tb();
//*****************************************************************************
// Parameter definition
//*****************************************************************************
parameter T_CLK = 20; //ns
parameter CHIPSET_QTY = 4;
localparam BRAM_ADDR_TEST_RW = 13'h0000;
localparam BRAM_ADDR_TEST_RO_DATA = 13'h0004;
localparam BRAM_ADDR_TEST_VERSION = 13'h0008;
localparam BRAM_ADDR_UPDATE_PERIOD = 13'h0020;
localparam BRAM_ADDR_CONVER_DIVISOR = 13'h0024;
localparam BRAM_ADDR_ENABLE = 13'h0028;
localparam BRAM_ADDR_RESET = 13'h002C;
localparam BRAM_ADDR_SPI_STATE_START = 13'h0100;
localparam BRAM_ADDR_SPI_TX_START = 13'h0180;
localparam BRAM_ADDR_SPI_RX_START = 13'h0200;
localparam BRAM_ADDR_SPI_ERR_START = 13'h0280;
localparam BRAM_ADDR_DDS_PHASE_INC_START = 13'h0400;
localparam BRAM_ADDR_DDS_PHASE_OFF_START = 13'h0480;
localparam BRAM_ADDR_CHIP_0_CNV_CMD_LTH = 13'h0500;
localparam BRAM_ADDR_CHIP_1_CNV_CMD_LTH = 13'h0504;
localparam BRAM_ADDR_CHIP_2_CNV_CMD_LTH = 13'h0508;
localparam BRAM_ADDR_CHIP_3_CNV_CMD_LTH = 13'h050C;
localparam BRAM_ADDR_STIM_TRIM_P_MASK = 13'h1F00;
localparam BRAM_ADDR_STIM_TRIM_P_START = 13'h0600;
localparam BRAM_ADDR_STIM_TRIM_N_MASK = 13'h1F00;
localparam BRAM_ADDR_STIM_TRIM_N_START = 13'h0700;
localparam BRAM_ADDR_CHIP_0_STIM_CH_0_3_TRIM_P = 13'h0600;
localparam BRAM_ADDR_CHIP_1_STIM_CH_0_3_TRIM_P = 13'h0610;
localparam BRAM_ADDR_CHIP_2_STIM_CH_0_3_TRIM_P = 13'h0620;
localparam BRAM_ADDR_CHIP_3_STIM_CH_0_3_TRIM_P = 13'h0630;
localparam BRAM_ADDR_CHIP_0_STIM_CH_0_3_TRIM_N = 13'h0700;
localparam BRAM_ADDR_CHIP_1_STIM_CH_0_3_TRIM_N = 13'h0710;
localparam BRAM_ADDR_CHIP_2_STIM_CH_0_3_TRIM_N = 13'h0720;
localparam BRAM_ADDR_CHIP_3_STIM_CH_0_3_TRIM_N = 13'h0730;
localparam BRAM_ADDR_CHIP_0_CNV_CMD_START = 13'h1000;
localparam BRAM_ADDR_CHIP_1_CNV_CMD_START = 13'h1040;
localparam BRAM_ADDR_CHIP_2_CNV_CMD_START = 13'h1080;
localparam BRAM_ADDR_CHIP_3_CNV_CMD_START = 13'h10C0;
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
reg clk ;
reg rst_n ;
reg [13-1:0] bram_addr ;
wire bram_clk ;
reg [32-1:0] bram_din ;
wire [32-1:0] bram_dout ;
reg bram_en ;
reg bram_rst ;
reg [ 4-1:0] bram_we ;
wire [32-1:0] update_period ;
wire [ 8-1:0] cnv_divisor ;
wire enable_timer ;
wire enable_record ;
wire enable_stim ;
wire dds_aclken ;
wire dss_aresetn ;
wire [ 8*CHIPSET_QTY-1:0] cnv_cmd_lth_array ;
wire [32*16*CHIPSET_QTY-1:0] cnv_cmd_array_array ;
wire [ 8*16*CHIPSET_QTY-1:0] stim_trim_p_array_array ;
wire [ 8*16*CHIPSET_QTY-1:0] stim_trim_n_array_array ;
wire phase_enable ;
wire [32*16-1:0] phase_inc_array ;
wire [32*16-1:0] phase_off_array ;
wire [ 1*CHIPSET_QTY-1:0] monitor_data_en_array ;
wire [32*CHIPSET_QTY-1:0] monitor_data_array ;
wire [ 1*CHIPSET_QTY-1:0] spi_cmd_valid_array ;
wire [32*CHIPSET_QTY-1:0] spi_cmd_data_array ;
wire [ 1*CHIPSET_QTY-1:0] spi_cmd_ready_array ;
wire [ 1*CHIPSET_QTY-1:0] spi_res_en_array ;
wire [32*CHIPSET_QTY-1:0] spi_res_array ;
wire [ 8-1:0] cnv_cmd_lth[0:CHIPSET_QTY-1] ;
wire [32-1:0] cnv_cmd_array[0:CHIPSET_QTY-1][0:15];
wire [ 8-1:0] stim_trim_p_array[0:CHIPSET_QTY-1][0:15];
wire [ 8-1:0] stim_trim_n_array[0:CHIPSET_QTY-1][0:15];
wire [32-1:0] phase_inc[0:15] ;
wire [32-1:0] phase_off[0:15] ;
wire spi_cmd_valid[0:CHIPSET_QTY-1] ;
wire [32-1:0] spi_cmd_data[0:CHIPSET_QTY-1] ;
reg spi_cmd_ready[0:CHIPSET_QTY-1] ;
reg monitor_data_en[0:CHIPSET_QTY-1] ;
reg [32-1:0] monitor_data[0:CHIPSET_QTY-1] ;
reg spi_res_en[0:CHIPSET_QTY-1] ;
reg [32-1:0] spi_res[0:CHIPSET_QTY-1] ;
reg [32-1:0] trim_val;
reg [32-1:0] rd_data;
integer m, n;
//*****************************************************************************
// Instantiation
//*****************************************************************************
transmit_config#
(
.VERSION ( 32'h10000002 ),
.CHIPSET_QTY ( CHIPSET_QTY )
)
DUT
(
.clk ( clk ),
.rst_n ( rst_n ),
.bram_addr ( bram_addr ),
.bram_clk ( bram_clk ),
.bram_din ( bram_din ),
.bram_dout ( bram_dout ),
.bram_en ( bram_en ),
.bram_rst ( bram_rst ),
.bram_we ( bram_we ),
.update_period ( update_period ),
.cnv_divisor ( cnv_divisor ),
.enable_timer ( enable_timer ),
.enable_record ( enable_record ),
.enable_stim ( enable_stim ),
.dds_aclken ( dds_aclken ),
.dss_aresetn ( dss_aresetn ),
.cnv_cmd_lth_array ( cnv_cmd_lth_array ),
.cnv_cmd_array_array ( cnv_cmd_array_array ),
.stim_trim_p_array_array( stim_trim_p_array_array),
.stim_trim_n_array_array( stim_trim_n_array_array),
.phase_enable ( phase_enable ),
.phase_inc_array ( phase_inc_array ),
.phase_off_array ( phase_off_array ),
.monitor_data_en_array ( monitor_data_en_array ),
.monitor_data_array ( monitor_data_array ),
.spi_cmd_valid_array ( spi_cmd_valid_array ),
.spi_cmd_data_array ( spi_cmd_data_array ),
.spi_cmd_ready_array ( spi_cmd_ready_array ),
.spi_res_en_array ( spi_res_en_array ),
.spi_res_array ( spi_res_array )
);
//*****************************************************************************
// Wire assignment
//*****************************************************************************
always #( T_CLK/2.0 ) clk = !clk;
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n )
spi_cmd_ready[3] <= 1'b0;
else if ( spi_cmd_valid[3] && (!spi_cmd_ready[3]) )
spi_cmd_ready[3] <= 1'b1;
else
spi_cmd_ready[3] <= 1'b0;
end
initial begin
Initial();
#0 rst_n = 0;
#100 rst_n = 1;
read_bram(BRAM_ADDR_TEST_RO_DATA, rd_data);
//update period
write_bram(BRAM_ADDR_UPDATE_PERIOD, 4500);
write_bram(BRAM_ADDR_UPDATE_PERIOD, 999);
//conver divisor
write_bram(BRAM_ADDR_CONVER_DIVISOR, 0);
write_bram(BRAM_ADDR_CONVER_DIVISOR, 2);
//enable
write_bram(BRAM_ADDR_ENABLE, 32'h1);
write_bram(BRAM_ADDR_ENABLE, 32'h2);
write_bram(BRAM_ADDR_ENABLE, 32'h4);
write_bram(BRAM_ADDR_ENABLE, 32'h8);
write_bram(BRAM_ADDR_ENABLE, 32'hF);
//reset
write_bram(BRAM_ADDR_RESET, 32'h1);
write_bram(BRAM_ADDR_RESET, 32'h0);
//cmd
#200
write_bram(BRAM_ADDR_CHIP_0_CNV_CMD_LTH, 1);
write_bram(BRAM_ADDR_CHIP_0_CNV_CMD_START+8'h0, {2'b00, 4'b0010, 4'b0000, 6'd0, 16'd0});
write_bram(BRAM_ADDR_CHIP_1_CNV_CMD_LTH, 2);
write_bram(BRAM_ADDR_CHIP_1_CNV_CMD_START+8'h0, {2'b00, 4'b0010, 4'b0000, 6'd1, 16'd0});
write_bram(BRAM_ADDR_CHIP_1_CNV_CMD_START+8'h4, {2'b00, 4'b0010, 4'b0000, 6'd2, 16'd0});
write_bram(BRAM_ADDR_CHIP_2_CNV_CMD_LTH, 3);
write_bram(BRAM_ADDR_CHIP_2_CNV_CMD_START+8'h0, {2'b00, 4'b0010, 4'b0000, 6'd3, 16'd0});
write_bram(BRAM_ADDR_CHIP_2_CNV_CMD_START+8'h4, {2'b00, 4'b0010, 4'b0000, 6'd4, 16'd0});
write_bram(BRAM_ADDR_CHIP_2_CNV_CMD_START+8'h8, {2'b00, 4'b0010, 4'b0000, 6'd5, 16'd0});
write_bram(BRAM_ADDR_CHIP_3_CNV_CMD_LTH, 4);
write_bram(BRAM_ADDR_CHIP_3_CNV_CMD_START+8'h0, {2'b00, 4'b0010, 4'b0000, 6'd6, 16'd0});
write_bram(BRAM_ADDR_CHIP_3_CNV_CMD_START+8'h4, {2'b00, 4'b0010, 4'b0000, 6'd7, 16'd0});
write_bram(BRAM_ADDR_CHIP_3_CNV_CMD_START+8'h8, {2'b00, 4'b0010, 4'b0000, 6'd8, 16'd0});
write_bram(BRAM_ADDR_CHIP_3_CNV_CMD_START+8'hC, {2'b00, 4'b0010, 4'b0000, 6'd9, 16'd0});
//stim_trim
#200
for (m=0;m<CHIPSET_QTY;m=m+1) begin
for (n=0;n<4;n=n+1) begin
trim_val[ 7: 0] = 4*n+1;
trim_val[15: 8] = 4*n+2;
trim_val[23:16] = 4*n+3;
trim_val[31:24] = 4*n+4;
@ ( posedge clk )write_bram(BRAM_ADDR_CHIP_0_STIM_CH_0_3_TRIM_P+8'h10*m+8'h4*n, trim_val);
end
end
for (m=0;m<CHIPSET_QTY;m=m+1) begin
for (n=0;n<4;n=n+1) begin
trim_val[ 7: 0] = 4*n+1;
trim_val[15: 8] = 4*n+2;
trim_val[23:16] = 4*n+3;
trim_val[31:24] = 4*n+4;
@ ( posedge clk )write_bram(BRAM_ADDR_CHIP_0_STIM_CH_0_3_TRIM_N+8'h10*m+8'h4*n, trim_val);
end
end
//dds
#200
for (n=0;n<16;n=n+1) begin
write_bram(BRAM_ADDR_DDS_PHASE_INC_START+8'h4*n, 32'h000029F0+n);
// write_bram(BRAM_ADDR_DDS_PHASE_OFF_START+8'h4*n, 32'h00100000*n);
end
//read state
#200
read_bram(BRAM_ADDR_SPI_STATE_START+8'h0, rd_data);
read_bram(BRAM_ADDR_SPI_STATE_START+8'h4, rd_data);
read_bram(BRAM_ADDR_SPI_STATE_START+8'h8, rd_data);
read_bram(BRAM_ADDR_SPI_STATE_START+8'hC, rd_data);
//write: tx
#200
write_bram(BRAM_ADDR_SPI_TX_START+8'h0, {8'hC0, 8'h01, 16'h0});
write_bram(BRAM_ADDR_SPI_TX_START+8'h4, {8'hC0, 8'h02, 16'h0});
write_bram(BRAM_ADDR_SPI_TX_START+8'h8, {8'hC0, 8'h03, 16'h0});
write_bram(BRAM_ADDR_SPI_TX_START+8'hC, {8'hC0, 8'h04, 16'h0});
//read: rx
#200
read_bram(BRAM_ADDR_SPI_RX_START+8'h0, rd_data);
read_bram(BRAM_ADDR_SPI_RX_START+8'h4, rd_data);
read_bram(BRAM_ADDR_SPI_RX_START+8'h8, rd_data);
read_bram(BRAM_ADDR_SPI_RX_START+8'hC, rd_data);
//read monitor
#200
read_bram(BRAM_ADDR_SPI_ERR_START+8'h0, rd_data);
read_bram(BRAM_ADDR_SPI_ERR_START+8'h4, rd_data);
read_bram(BRAM_ADDR_SPI_ERR_START+8'h8, rd_data);
read_bram(BRAM_ADDR_SPI_ERR_START+8'hC, rd_data);
//generate res
#200
for (m=0;m<CHIPSET_QTY;m=m+1) begin
@ ( posedge clk );
spi_res_en[m] <= 1'b1;
spi_res[m] <= 32'h4600+m;
@ ( posedge clk );
spi_res_en[m] <= 1'b0;
end
//generate monitor
#200
for (m=0;m<CHIPSET_QTY;m=m+1) begin
@ ( posedge clk );
monitor_data_en[m] <= 1'b1;
monitor_data[m] <= 32'h700+m;
@ ( posedge clk );
monitor_data_en[m] <= 1'b0;
end
//read state
#200
read_bram(BRAM_ADDR_SPI_STATE_START+8'h0, rd_data);
read_bram(BRAM_ADDR_SPI_STATE_START+8'h4, rd_data);
read_bram(BRAM_ADDR_SPI_STATE_START+8'h8, rd_data);
read_bram(BRAM_ADDR_SPI_STATE_START+8'hC, rd_data);
//read: rx
#200
read_bram(BRAM_ADDR_SPI_RX_START+8'h0, rd_data);
read_bram(BRAM_ADDR_SPI_RX_START+8'h4, rd_data);
read_bram(BRAM_ADDR_SPI_RX_START+8'h8, rd_data);
read_bram(BRAM_ADDR_SPI_RX_START+8'hC, rd_data);
//read monitor
#200
read_bram(BRAM_ADDR_SPI_ERR_START+8'h0, rd_data);
read_bram(BRAM_ADDR_SPI_ERR_START+8'h4, rd_data);
read_bram(BRAM_ADDR_SPI_ERR_START+8'h8, rd_data);
read_bram(BRAM_ADDR_SPI_ERR_START+8'hC, rd_data);
//read state
#100
read_bram(BRAM_ADDR_SPI_STATE_START+8'h0, rd_data);
read_bram(BRAM_ADDR_SPI_STATE_START+8'h4, rd_data);
read_bram(BRAM_ADDR_SPI_STATE_START+8'h8, rd_data);
read_bram(BRAM_ADDR_SPI_STATE_START+8'hC, rd_data);
end
//*****************************************************************************
// Task
//*****************************************************************************
task Initial;
begin
clk <= 1'b0 ;
rst_n <= 1'b0 ;
bram_addr <= 0 ;
bram_din <= 0 ;
bram_en <= 0 ;
bram_rst <= 0 ;
bram_we <= 0 ;
for (n=0;n<CHIPSET_QTY;n=n+1) begin
spi_cmd_ready[n] <= 1'b1;
monitor_data_en[n] <= 1'b0;
monitor_data[n] <= 0;
spi_res_en[n] <= 1'b0;
spi_res[n] <= 0;
end
trim_val <= 0;
end
endtask
task write_bram;
input [12:0] addr;
input [31:0] data;
begin
@ ( posedge clk );
bram_addr <= addr;
bram_din <= data;
bram_en <= 1;
bram_we <= 4'hF ;
@ ( posedge clk );
bram_en <= 0;
bram_we <= 4'h0;
end
endtask
task read_bram;
input [12:0] addr;
output [31:0] data;
begin
@ ( posedge clk );
bram_addr <= addr;
bram_en <= 1;
bram_we <= 4'h0 ;
@ ( posedge clk );
bram_en <= 0;
@ ( posedge clk );
data <= bram_dout;
end
endtask
//*****************************************************************************
// Continuous assignments
//*****************************************************************************
genvar i, j;
generate
for(i=0;i<CHIPSET_QTY;i=i+1) begin : pack_cmd_lth
assign monitor_data_en_array[i] = monitor_data_en[i];
assign monitor_data_array[32*i+31 : 32*i] = monitor_data[i];
assign spi_cmd_ready_array[i] = spi_cmd_ready[i];
assign spi_res_en_array[i] = spi_res_en[i];
assign spi_res_array[32*i+31 : 32*i] = spi_res[i];
end
endgenerate
generate
for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack
assign cnv_cmd_lth[i] = cnv_cmd_lth_array[8*i+7 : 8*i];
assign spi_cmd_valid[i] = spi_cmd_valid_array[i];
assign spi_cmd_data[i] = spi_cmd_data_array[32*i+31 : 32*i];
end
endgenerate
generate
for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack_array_array
for(j=0;j<16;j=j+1) begin : ssss
assign cnv_cmd_array[i][j] = cnv_cmd_array_array[32*16*i+32*j+31 : 32*16*i+32*j];
assign stim_trim_p_array[i][j] = stim_trim_p_array_array[8*16*i+8*j+7 : 8*16*i+8*j];
assign stim_trim_n_array[i][j] = stim_trim_n_array_array[8*16*i+8*j+7 : 8*16*i+8*j];
end
end
endgenerate
generate
for(i=0;i<16;i=i+1) begin : unpack_cmd_lth
assign phase_inc[i] = phase_inc_array[32*i+31 : 32*i];
assign phase_off[i] = phase_off_array[32*i+31 : 32*i];
end
endgenerate
endmodule