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chenmin
2024-10-28 13:14:49 +08:00
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c64_pro.srcs/sources_1/rtl/rhs2116/trans_distribute.v
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`timescale 1 ns / 1 ps
module trans_distribute#
(
parameter CHIPSET_QTY = 4,
parameter CMD_CNV = 2'b00,
parameter CMD_EXTEND = 2'b01,
parameter CMD_WRITE = 2'b10,
parameter CMD_READ = 2'b11
)
(
input clk ,
input rst_n ,
input trans_round ,
input [32-1:0] s_axi_rx_tdata ,
input s_axi_rx_tlast ,
output s_axi_rx_tready ,
input s_axi_rx_tvalid ,
output reg [16-1:0] record_ch_qty ,
output reg dds_aclken ,
output reg dds_aresetn ,
input m_axi_tx_aresetn ,
output [32*CHIPSET_QTY-1:0] m_axi_tx_tdata_array ,
output [ 1*CHIPSET_QTY-1:0] m_axi_tx_tlast_array ,
input [ 1*CHIPSET_QTY-1:0] m_axi_tx_tready_array ,
output [ 1*CHIPSET_QTY-1:0] m_axi_tx_tvalid_array
);
//*****************************************************************************
// localparam definition
//*****************************************************************************
localparam IDLE = 4'h0 ;
localparam TX_ST = 4'h1 ;
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
reg [ 4-1:0] cstate ;
reg [ 4-1:0] nstate ;
reg recv ;
reg [32-1:0] s_axi_rx_tdata_r ;
reg [ 4-1:0] chipset ;
reg is_end ;
wire [32-1:0] s_axi_tx_tdata ;
wire s_axi_tx_tready[0:CHIPSET_QTY-1] ;
wire s_axi_tx_tvalid[0:CHIPSET_QTY-1] ;
wire [32-1:0] m_axi_tx_tdata[0:CHIPSET_QTY-1] ;
wire m_axi_tx_tlast[0:CHIPSET_QTY-1] ;
wire m_axi_tx_tready[0:CHIPSET_QTY-1] ;
wire m_axi_tx_tvalid[0:CHIPSET_QTY-1] ;
genvar i;
//*****************************************************************************
// Instantiation
//*****************************************************************************
generate
for(i=0;i<CHIPSET_QTY;i=i+1) begin : output_fifo
axis_data_fifo_w32_d32 u_axis_data_fifo_if_recv
(
.s_axis_aclk ( clk ),
.s_axis_aresetn ( m_axi_tx_aresetn ),
.s_axis_tvalid ( s_axi_tx_tvalid[i] ),
.s_axis_tready ( s_axi_tx_tready[i] ),
.s_axis_tdata ( s_axi_tx_tdata ),
.s_axis_tlast ( 1'b0 ),
.m_axis_tvalid ( m_axi_tx_tvalid[i] ),
.m_axis_tready ( m_axi_tx_tready[i] ),
.m_axis_tdata ( m_axi_tx_tdata[i] ),
.m_axis_tlast ( m_axi_tx_tlast[i] )
);
end
endgenerate
//*****************************************************************************
always@( posedge clk or negedge rst_n ) begin
if( !rst_n ) cstate <= IDLE;
else cstate <= nstate;
end
always@( * ) begin
case ( cstate )
IDLE:
if ( trans_round )
nstate <= TX_ST;
else
nstate <= IDLE;
TX_ST:
if ( is_end || (~s_axi_rx_tvalid) )
nstate <= IDLE;
else
nstate <= TX_ST;
default:
nstate <= IDLE;
endcase
end
always@( posedge clk or negedge rst_n ) begin
if( !rst_n )
recv <= 1'b0;
else if ( cstate == TX_ST && nstate == TX_ST )
recv <= 1'b1;
else
recv <= 1'b0;
end
always@( posedge clk or negedge rst_n ) begin
if( !rst_n ) begin
s_axi_rx_tdata_r <= 0;
chipset <= 0;
is_end <= 1'b0;
end else if ( s_axi_rx_tvalid && s_axi_rx_tready ) begin
s_axi_rx_tdata_r <= s_axi_rx_tdata;
chipset <= (s_axi_rx_tdata[31:30] == CMD_CNV)? s_axi_rx_tdata[25:22]:s_axi_rx_tdata[27:24];
is_end <= (s_axi_rx_tdata[31:30]==CMD_EXTEND && s_axi_rx_tdata[23:20]==4'hF)? 1'b1:1'b0;
end else begin
s_axi_rx_tdata_r <= 0;
is_end <= 1'b0;
end
end
always@( posedge clk or negedge rst_n ) begin
if( !rst_n )
dds_aclken <= 1'b0;
else if ( s_axi_rx_tvalid && s_axi_rx_tready && s_axi_rx_tdata[31:30]==CMD_EXTEND && s_axi_rx_tdata[23:20]==4'hF )
dds_aclken <= s_axi_rx_tdata[0];
end
always@( posedge clk or negedge rst_n ) begin
if( !rst_n )
dds_aresetn <= 1'b1;
else if ( s_axi_rx_tvalid && s_axi_rx_tready && s_axi_rx_tdata[31:30]==CMD_EXTEND && s_axi_rx_tdata[23:20]==4'hF && s_axi_rx_tdata[1] )
dds_aresetn <= 1'b0;
else
dds_aresetn <= 1'b1;
end
always@( posedge clk or negedge rst_n ) begin
if( !rst_n )
record_ch_qty <= 0;
else if ( trans_round )
record_ch_qty <= 0;
else if ( s_axi_rx_tvalid && s_axi_rx_tready && s_axi_rx_tdata[31:30] == CMD_CNV )
record_ch_qty <= record_ch_qty + 1'b1;
end
//*****************************************************************************
// Wire assignment
//*****************************************************************************
assign s_axi_rx_tready = (cstate == TX_ST && nstate == TX_ST)? 1'b1:1'b0;
assign s_axi_tx_tdata = (s_axi_rx_tdata_r[31:30] == CMD_CNV)?
{s_axi_rx_tdata_r[31:26], 4'h0, s_axi_rx_tdata_r[21:0]}:
{s_axi_rx_tdata_r[31:28], 4'h0, s_axi_rx_tdata_r[23:0]};
generate
for(i=0;i<CHIPSET_QTY;i=i+1) begin : hub
assign s_axi_tx_tvalid[i] = (recv && chipset == i && (~is_end))? 1'b1 : 1'b0;
end
endgenerate
generate
for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack
assign m_axi_tx_tready[i] = m_axi_tx_tready_array[i];
end
endgenerate
generate
for(i=0;i<CHIPSET_QTY;i=i+1) begin : pack
assign m_axi_tx_tdata_array[32*i+31 : 32*i] = m_axi_tx_tdata[i];
assign m_axi_tx_tlast_array[i] = m_axi_tx_tlast[i];
assign m_axi_tx_tvalid_array[i] = m_axi_tx_tvalid[i];
end
endgenerate
endmodule