上传PL工程

c64_pro.srcs/sources_1/rtl/led_ctrl.v

@@ -0,0 +1,79 @@
+`timescale 1 ns / 1 ps
+
+module led_ctrl#
+	(
+		parameter	CLK_PERIOD			= 10
+	)
+	(
+		input						clk			,
+		input						rst_n		,
+		
+		input		[3-1:0]			cmd			,
+		output	reg					led
+	);
+	
+	//*****************************************************************************
+	// Internal register and wire declarations
+	//*****************************************************************************
+	wire					st_off			;
+	wire					st_on			;
+	wire					st_blink		;
+	wire					st_breath		;
+	
+	wire					led_blink		;
+	wire					led_breath		;
+	
+	//*****************************************************************************
+	// Instantiation
+	//*****************************************************************************
+	pwm_gen#
+		(
+			.DATA_WIDTH		( 28			)
+		)
+	u_pwm_gen_blink
+		(
+			.clk			( clk			),
+			.rst_n			( rst_n			),
+			
+			.enable			( st_blink		),
+			.period			( 28'hBEBC200	),
+			.duty			( 28'h5F5E100	),
+			.pwm			( led_blink		)
+		);
+		
+	breath_gen#
+		(
+			.CLK_PERIOD		( CLK_PERIOD	)
+		)
+	u_breath_gen
+		(
+			.clk			( clk			),
+			.rst_n			( rst_n			),
+			
+			.enable			( st_breath		),
+			.pwm			( led_breath	)
+		);
+
+	//*****************************************************************************
+	always @ ( * ) begin
+		if (st_off)
+			led <= 1'b0;
+		else if (st_on)
+			led <= 1'b1;
+		else if (st_blink)
+			led <= led_blink;
+		else if (st_breath)
+			led <= led_breath;
+		else
+			led <= 1'b0;
+	end
+	
+	//*****************************************************************************
+	// Wire assignment
+	//*****************************************************************************
+	assign st_off	= (cmd == 3'b000)? 1'b1:1'b0;
+	assign st_on	= (cmd == 3'b001)? 1'b1:1'b0;
+	assign st_blink	= (cmd == 3'b010)? 1'b1:1'b0;
+	assign st_breath= (cmd == 3'b011)? 1'b1:1'b0;
+	
+endmodule