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chenmin
2024-10-28 13:14:49 +08:00
parent d9ea3b1c85
commit 25cdd3c44c
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c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v
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`timescale 1 ns / 1 ps
module eeg_upload#
(
parameter CLK_PERIOD = 10 ,
parameter CHIPSET_QTY = 4 ,
parameter CH_OF_CHIPSET = 16 ,
parameter TIME_OUT_MS = 5
)
(
input clk ,
input rst_n ,
input trans_round ,
input [32*CHIPSET_QTY-1:0] cnv_res_tdata_array ,
input [ CHIPSET_QTY-1:0] cnv_res_tlast_array ,
output [ CHIPSET_QTY-1:0] cnv_res_tready_array ,
input [ CHIPSET_QTY-1:0] cnv_res_tvalid_array ,
output reg [31:0] axi_str_rxd_tdata ,
output reg axi_str_rxd_tlast ,
input axi_str_rxd_tready ,
output reg axi_str_rxd_tvalid
);
//*****************************************************************************
// localparam definition
//*****************************************************************************
localparam IDLE = 4'd0 ;
localparam READY_ST = 4'd1 ;
localparam SCAN_ST = 4'd2 ;
localparam CLKS = 20 ;
localparam TIME_OUT_CLKS = (TIME_OUT_MS*1000000)/CLK_PERIOD;
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
reg [ 4-1:0] cstate ;
reg [ 4-1:0] nstate ;
wire [32-1:0] cnv_res_tdata[0:CHIPSET_QTY-1] ;
wire cnv_res_tlast[0:CHIPSET_QTY-1] ;
reg cnv_res_tready[0:CHIPSET_QTY-1] ;
wire cnv_res_tvalid[0:CHIPSET_QTY-1] ;
reg [32-1:0] cnv_res_tdata_r[0:CHIPSET_QTY-1] ;
reg cnv_res_tvalid_r[0:CHIPSET_QTY-1] ;
reg [ 8-1:0] scan_cnt ;
reg round_end ;
genvar i;
//*****************************************************************************
generate
for(i=0;i<CHIPSET_QTY;i=i+1) begin : rx_data
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n ) begin
cnv_res_tdata_r[i] <= 0;
cnv_res_tvalid_r[i] <= 1'b0;
end else if ( cnv_res_tready[i] && cnv_res_tvalid[i] ) begin
cnv_res_tdata_r[i] <= cnv_res_tdata[i];
cnv_res_tvalid_r[i] <= cnv_res_tvalid[i];
end
end
end
endgenerate
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n )
round_end <= 1'b0;
else if ( cnv_res_tready[0] && cnv_res_tvalid[0] && cnv_res_tlast[0] )
round_end <= 1'b1;
else if ( cstate == IDLE )
round_end <= 1'b0;
end
always@( posedge clk or negedge rst_n ) begin
if( !rst_n ) cstate <= IDLE;
else cstate <= nstate;
end
always@( * ) begin
case ( cstate )
IDLE:
if ( trans_round )
nstate <= READY_ST;
else
nstate <= IDLE;
READY_ST:
if ( cnv_res_tvalid_array )
nstate <= SCAN_ST;
else
nstate <= READY_ST;
SCAN_ST:
if ( scan_cnt == CHIPSET_QTY-1 )
nstate <= round_end? IDLE:READY_ST;
else
nstate <= SCAN_ST;
default:
nstate <= IDLE;
endcase
end
generate
for(i=0;i<CHIPSET_QTY;i=i+1) begin : tready
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n )
cnv_res_tready[i] <= 1'b0;
else if ( cstate == IDLE || (cstate == READY_ST && nstate == READY_ST) )
cnv_res_tready[i] <= 1'b1;
else
cnv_res_tready[i] <= 1'b0;
end
end
endgenerate
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n )
scan_cnt <= 0;
else if ( cstate == READY_ST )
scan_cnt <= 0;
else if ( cstate == SCAN_ST )
scan_cnt <= scan_cnt + 1'b1;
end
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n ) begin
axi_str_rxd_tvalid <= 1'b0;
axi_str_rxd_tdata <= 0;
end else if ( cstate == SCAN_ST ) begin
axi_str_rxd_tvalid <= cnv_res_tvalid_r[scan_cnt];
axi_str_rxd_tdata <= cnv_res_tdata_r[scan_cnt];
end else begin
axi_str_rxd_tvalid <= 1'b0;
end
end
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n )
axi_str_rxd_tlast <= 1'b0;
else if ( cstate == SCAN_ST && (scan_cnt == CHIPSET_QTY-1) && round_end )
axi_str_rxd_tlast <= 1'b1;
else
axi_str_rxd_tlast <= 1'b0;
end
//*****************************************************************************
// Wire assignment
//*****************************************************************************
generate
for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack_res
assign cnv_res_tdata[i][31:24] = cnv_res_tdata_array[32*i+31 : 32*i+24] + CH_OF_CHIPSET*i;
assign cnv_res_tdata[i][23: 0] = cnv_res_tdata_array[32*i+23 : 32*i+ 0];
assign cnv_res_tlast[i] = cnv_res_tlast_array[i];
assign cnv_res_tvalid[i] = cnv_res_tvalid_array[i];
end
endgenerate
generate
for(i=0;i<CHIPSET_QTY;i=i+1) begin : pack_res
assign cnv_res_tready_array[i] = cnv_res_tready[i];
end
endgenerate
endmodule