上传PL工程

c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v

@@ -0,0 +1,154 @@
+ `timescale 1ns/1ps
+
+module ads1299_mod#
+	(
+		parameter	DATA_WIDTH		=  8		,
+		parameter	WIRE_DELAY		= 11
+	)
+	(
+		input						cs			,
+		input						sclk		,
+		input						mosi		,
+		output						miso		,
+		output	reg					drdy		,
+		input						start
+	);
+	
+	//*****************************************************************************
+	// localparam definition
+	//*****************************************************************************
+	localparam	T_CLK 				= 31250		;	//ns
+
+	localparam	RDATAC				= 8'h08		;
+	localparam	SDATAC				= 8'h11		;
+	
+	//*****************************************************************************
+	// Internal register and wire declarations
+	//*****************************************************************************
+	reg								clk			;
+	reg								rst_n		;
+	
+	reg	[ 8 - 1:0]					serial_in	;
+	reg	[ 8 - 1:0]					rx_cnt		;
+	reg	[ 8 - 1:0]					rx_data		;
+	
+	reg	[ 8 - 1:0]					tx_cnt		;
+	reg	[ 8 - 1:0]					reg_data	;
+	reg	[ 8 - 1:0]					cnv_data	;
+	
+	reg	[ 8 - 1:0]					start_t_cnt	;
+	reg								cnv_en		;
+
+	reg	[ 8 - 1:0]					r_cnt		;
+	
+	//*****************************************************************************
+	always #( T_CLK/2.0 )  clk = !clk;
+	
+	initial begin
+		Initial();
+		
+		#100 rst_n = 1;
+
+		while(1) begin
+			@ ( posedge cnv_en );
+			while ( cnv_en ) begin
+				@ ( posedge clk );
+				drdy <= cnv_en? 1'b0:1'b1;
+				@ ( negedge sclk );
+				drdy <= 1'b1;
+			end
+		end
+		
+	end
+
+	initial begin
+		clk		<= 1'b0	;
+		rst_n	<= 1'b0	;
+
+		drdy	<= 1'b1;
+	end
+	
+	//RX
+	always @ ( negedge sclk or negedge rst_n or posedge cs ) begin
+		if( !rst_n || cs )
+			rx_cnt <= 0;
+		else if ( rx_cnt != DATA_WIDTH )
+			rx_cnt <= rx_cnt + 1'b1;
+		else
+			rx_cnt <= 1;
+	end
+	
+	always @ ( negedge sclk or negedge rst_n or negedge cs ) begin
+		if( !rst_n || cs )
+			serial_in <= 0;
+		else
+			serial_in <= {serial_in[6:0], mosi};
+	end
+	
+	always @ ( rx_cnt ) begin
+		if( rx_cnt == 8 )
+			rx_data <= serial_in;
+	end
+	
+	//data
+	always@( posedge clk or negedge rst_n ) begin
+		if ( !rst_n )
+			start_t_cnt <= 0;
+		else if ( start ) begin
+			if ( start_t_cnt != 3 )
+				start_t_cnt <= start_t_cnt + 1'b1;
+		end else
+			start_t_cnt <= 0;
+	end
+	
+	always@( posedge clk or negedge rst_n ) begin
+		if ( !rst_n )
+			cnv_en <= 1'b0;
+		else if ( start_t_cnt == 3 )
+			cnv_en <= 1'b1;
+		else
+			cnv_en <= 1'b0;
+	end
+	
+	always@( posedge sclk or negedge rst_n or posedge cs ) begin
+		if ( !rst_n )
+			r_cnt <= 0;
+		else if ( cs )
+			r_cnt <= 0;
+		else
+			r_cnt <= r_cnt + 1'b1;
+	end
+	
+	always@( posedge sclk or negedge rst_n  ) begin
+		if ( !rst_n ) begin
+			cnv_data <= 0;
+		end else if ( cnv_en && r_cnt[2:0] == 3'd0 && !cs ) begin
+			cnv_data <= cnv_data + 1'b1;
+		end
+	end
+	
+	always @ ( negedge cs or negedge rst_n or tx_cnt ) begin
+		if ( !rst_n )
+			reg_data <= 8'h55;
+		else if ( tx_cnt == 7 )
+			reg_data <= reg_data + 1'b1;
+	end
+	
+	//TX
+	always @ ( posedge sclk or negedge rst_n or posedge cs ) begin
+		if( !rst_n || cs )
+			tx_cnt <= DATA_WIDTH;
+		else if ( tx_cnt != 0 )
+			tx_cnt <= tx_cnt - 1'b1;
+		else
+			tx_cnt <= DATA_WIDTH-1;
+	end
+	
+	//*****************************************************************************
+	// Wire assignment
+	//*****************************************************************************
+	assign #17 miso = (tx_cnt == DATA_WIDTH)? 1'b0:( cnv_en? cnv_data[tx_cnt]:reg_data[tx_cnt] );
+
+endmodule
+
+