上传PL工程

c64_pro.srcs/sources_1/rtl/accel/accel_config.v

@@ -0,0 +1,83 @@
+`timescale 1 ns / 1 ps
+
+module accel_config#
+	(
+		parameter	CHANNLE_QTY			= 64	,
+		parameter	PRE_MSG_LEN			= 24
+	)
+	(
+		input							clk					,
+		input							rst_n				,
+		
+		input		[13-1:0]			bram_addr			,
+		input							bram_clk			,
+		input		[32-1:0]			bram_din			,
+		output	reg	[32-1:0]			bram_dout			,
+		input							bram_en				,
+		input							bram_rst			,
+		input		[ 4-1:0]			bram_we				,
+
+		output		[32-1:0]			t_tdata				,
+		input							t_tready			,
+		output							t_tvalid			,
+
+		input		[32-1:0]			r_tdata				,
+		input							r_tvalid			,
+
+		output							stream_enable
+	);
+	
+	//*****************************************************************************
+	// localparam definition
+	//*****************************************************************************
+	localparam 	BRAM_ADDR_TEST_RO				= 13'h0000;
+	localparam 	BRAM_ADDR_TEST_RW				= 13'h0004;
+	
+	//*****************************************************************************
+	// Internal register and wire declarations
+	//*****************************************************************************
+	reg		[32-1:0]		test_data						;
+	
+	wire					bram_wr_valid					;
+	wire					bram_rd_valid					;
+
+	reg		[ 8-1:0]		pre_message[0:PRE_MSG_LEN-1]	;
+	reg		[ 8-1:0]		ch_mapping2pc[0:CHANNLE_QTY-1]	;
+	reg		[ 8-1:0]		upload_ch[0:CHANNLE_QTY/8-1]	;
+
+	integer	n;
+	
+	genvar i;
+	
+	//*****************************************************************************
+	// Procedural blocks
+	//*****************************************************************************
+
+	//write bram/Set config
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n )
+			test_data <= 0;
+		else if ( bram_wr_valid && ( bram_addr  == BRAM_ADDR_TEST_RW ) )
+			test_data <= bram_din;
+	end
+	
+	//read bram/Get config
+	always @ ( posedge clk or negedge rst_n ) begin
+		if( !rst_n ) begin
+			bram_dout <= 0;
+		end else if ( bram_rd_valid ) begin
+			
+			if ( bram_addr  == BRAM_ADDR_TEST_RO )
+				bram_dout <= 32'h12345678;
+			
+		end
+	end
+	
+	//*****************************************************************************
+	// Continuous assignments
+	//*****************************************************************************
+	assign t_tdata = 0;
+	assign t_tvalid = 1'b0;
+	assign stream_enable = 1'b0;
+	
+endmodule