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chenmin
2024-10-28 13:14:49 +08:00
parent d9ea3b1c85
commit 25cdd3c44c
3437 changed files with 10334573 additions and 0 deletions
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c64_pro.srcs/sources_1/rtl/.VSCodeCounter/2024-03-26_15-29-43/details.md
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# Details
Date : 2024-03-26 15:29:43
Directory d:\\projects\\vivadoPrj\\c64_pro\\c64_pro.srcs\\sources_1\\rtl
Total : 55 files, 8710 codes, 1239 comments, 1945 blanks, all 11894 lines
[Summary](results.md) / Details / [Diff Summary](diff.md) / [Diff Details](diff-details.md)
## Files
| filename | language | code | comment | blank | total |
| :--- | :--- | ---: | ---: | ---: | ---: |
| [accel/accel_top.v](/accel/accel_top.v) | Verilog | 117 | 13 | 36 | 166 |
| [accel/lis2dw12.v](/accel/lis2dw12.v) | Verilog | 197 | 10 | 31 | 238 |
| [c64pro_top.v](/c64pro_top.v) | Verilog | 364 | 44 | 78 | 486 |
| [eeg/ads1299_arrange.v](/eeg/ads1299_arrange.v) | Verilog | 195 | 16 | 31 | 242 |
| [eeg/ads1299_if.v](/eeg/ads1299_if.v) | Verilog | 149 | 18 | 27 | 194 |
| [eeg/ads1299_mod.v](/eeg/ads1299_mod.v) | Verilog | 113 | 13 | 29 | 155 |
| [eeg/ads1299_spi - backup.v](/eeg/ads1299_spi%20-%20backup.v) | Verilog | 186 | 12 | 29 | 227 |
| [eeg/ads1299_spi.v](/eeg/ads1299_spi.v) | Verilog | 218 | 10 | 35 | 263 |
| [eeg/ads1299_spi_tb.v](/eeg/ads1299_spi_tb.v) | Verilog | 79 | 16 | 21 | 116 |
| [eeg/eeg_config.v](/eeg/eeg_config.v) | Verilog | 118 | 16 | 32 | 166 |
| [eeg/eeg_top.v](/eeg/eeg_top.v) | Verilog | 204 | 21 | 52 | 277 |
| [eeg/eeg_top_tb.v](/eeg/eeg_top_tb.v) | Verilog | 158 | 88 | 40 | 286 |
| [eeg/eeg_upload.v](/eeg/eeg_upload.v) | Verilog | 147 | 13 | 29 | 189 |
| [emg/emg_config.v](/emg/emg_config.v) | Verilog | 81 | 14 | 25 | 120 |
| [emg/emg_top.v](/emg/emg_top.v) | Verilog | 44 | 17 | 17 | 78 |
| [led_ctrl.v](/led_ctrl.v) | Verilog | 58 | 10 | 12 | 80 |
| [led_ctrl_tb.v](/led_ctrl_tb.v) | Verilog | 34 | 19 | 17 | 70 |
| [pl_top.v](/pl_top.v) | Verilog | 320 | 35 | 70 | 425 |
| [pl_top_tb.v](/pl_top_tb.v) | Verilog | 505 | 77 | 116 | 698 |
| [rhs2116/cnv_res_collect.v](/rhs2116/cnv_res_collect.v) | Verilog | 180 | 14 | 30 | 224 |
| [rhs2116/cnv_res_collect_tb.v](/rhs2116/cnv_res_collect_tb.v) | Verilog | 119 | 20 | 33 | 172 |
| [rhs2116/dds_stim_16ch_tb.v](/rhs2116/dds_stim_16ch_tb.v) | Verilog | 74 | 16 | 21 | 111 |
| [rhs2116/dds_stim_16ch_tb.vhd](/rhs2116/dds_stim_16ch_tb.vhd) | VHDL | 307 | 135 | 49 | 491 |
| [rhs2116/rhs2116_mod.v](/rhs2116/rhs2116_mod.v) | Verilog | 84 | 7 | 19 | 110 |
| [rhs2116/rhs2116_top.v](/rhs2116/rhs2116_top.v) | Verilog | 337 | 27 | 86 | 450 |
| [rhs2116/rhs2116_top_tb.v](/rhs2116/rhs2116_top_tb.v) | Verilog | 367 | 26 | 83 | 476 |
| [rhs2116/sine_gen.v](/rhs2116/sine_gen.v) | Verilog | 154 | 22 | 31 | 207 |
| [rhs2116/sine_gen_tb.v](/rhs2116/sine_gen_tb.v) | Verilog | 129 | 18 | 42 | 189 |
| [rhs2116/stim_event_collect.v](/rhs2116/stim_event_collect.v) | Verilog | 74 | 10 | 14 | 98 |
| [rhs2116/stim_monitor.v](/rhs2116/stim_monitor.v) | Verilog | 105 | 13 | 14 | 132 |
| [rhs2116/trans_arrange.v](/rhs2116/trans_arrange.v) | Verilog | 174 | 18 | 31 | 223 |
| [rhs2116/trans_arrange_tb.v](/rhs2116/trans_arrange_tb.v) | Verilog | 268 | 19 | 62 | 349 |
| [rhs2116/trans_distribute.v](/rhs2116/trans_distribute.v) | Verilog | 120 | 13 | 26 | 159 |
| [rhs2116/trans_distribute_tb.v](/rhs2116/trans_distribute_tb.v) | Verilog | 114 | 16 | 24 | 154 |
| [rhs2116/trans_timer.v](/rhs2116/trans_timer.v) | Verilog | 60 | 10 | 15 | 85 |
| [rhs2116/trans_timer_tb.v](/rhs2116/trans_timer_tb.v) | Verilog | 55 | 15 | 19 | 89 |
| [rhs2116/transmit_config.v](/rhs2116/transmit_config.v) | Verilog | 351 | 82 | 74 | 507 |
| [rhs2116/transmit_config_tb.v](/rhs2116/transmit_config_tb.v) | Verilog | 321 | 36 | 101 | 458 |
| [rhs2116/transmit_if.v](/rhs2116/transmit_if.v) | Verilog | 268 | 25 | 46 | 339 |
| [rhs2116/transmit_if_tb.v](/rhs2116/transmit_if_tb.v) | Verilog | 172 | 39 | 58 | 269 |
| [switch/adg1414_if.v](/switch/adg1414_if.v) | Verilog | 136 | 13 | 25 | 174 |
| [switch/adg1414_if_tb.v](/switch/adg1414_if_tb.v) | Verilog | 56 | 15 | 17 | 88 |
| [switch/channel_switch.v](/switch/channel_switch.v) | Verilog | 169 | 25 | 30 | 224 |
| [switch/channel_switch_tb.v](/switch/channel_switch_tb.v) | Verilog | 52 | 16 | 17 | 85 |
| [trigger/trigger_detection.v](/trigger/trigger_detection.v) | Verilog | 21 | 1 | 7 | 29 |
| [trigger/trigger_top.v](/trigger/trigger_top.v) | Verilog | 137 | 15 | 32 | 184 |
| [trigger/trigger_top_tb.v](/trigger/trigger_top_tb.v) | Verilog | 45 | 15 | 16 | 76 |
| [upload/upload_config.v](/upload/upload_config.v) | Verilog | 96 | 14 | 29 | 139 |
| [upload/upload_sort.v](/upload/upload_sort.v) | Verilog | 141 | 12 | 27 | 180 |
| [upload/upload_top.v](/upload/upload_top.v) | Verilog | 254 | 15 | 45 | 314 |
| [utils/breath_gen.v](/utils/breath_gen.v) | Verilog | 123 | 13 | 25 | 161 |
| [utils/debouncing.v](/utils/debouncing.v) | Verilog | 93 | 10 | 15 | 118 |
| [utils/pwm_gen.v](/utils/pwm_gen.v) | Verilog | 40 | 4 | 9 | 53 |
| [utils/spi_full_duplex_master.v](/utils/spi_full_duplex_master.v) | Verilog | 148 | 12 | 25 | 185 |
| [utils/spi_full_duplex_master_tb.v](/utils/spi_full_duplex_master_tb.v) | Verilog | 79 | 16 | 21 | 116 |
[Summary](results.md) / Details / [Diff Summary](diff.md) / [Diff Details](diff-details.md)
c64_pro.srcs/sources_1/rtl/.VSCodeCounter/2024-03-26_15-29-43/diff-details.md
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# Diff Details
Date : 2024-03-26 15:29:43
Directory d:\\projects\\vivadoPrj\\c64_pro\\c64_pro.srcs\\sources_1\\rtl
Total : 0 files, 0 codes, 0 comments, 0 blanks, all 0 lines
[Summary](results.md) / [Details](details.md) / [Diff Summary](diff.md) / Diff Details
## Files
| filename | language | code | comment | blank | total |
| :--- | :--- | ---: | ---: | ---: | ---: |
[Summary](results.md) / [Details](details.md) / [Diff Summary](diff.md) / Diff Details
c64_pro.srcs/sources_1/rtl/.VSCodeCounter/2024-03-26_15-29-43/diff.csv
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c64_pro.srcs/sources_1/rtl/.VSCodeCounter/2024-03-26_15-29-43/diff.md
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# Diff Summary
Date : 2024-03-26 15:29:43
Directory d:\\projects\\vivadoPrj\\c64_pro\\c64_pro.srcs\\sources_1\\rtl
Total : 0 files, 0 codes, 0 comments, 0 blanks, all 0 lines
[Summary](results.md) / [Details](details.md) / Diff Summary / [Diff Details](diff-details.md)
## Languages
| language | files | code | comment | blank | total |
| :--- | ---: | ---: | ---: | ---: | ---: |
## Directories
| path | files | code | comment | blank | total |
| :--- | ---: | ---: | ---: | ---: | ---: |
[Summary](results.md) / [Details](details.md) / Diff Summary / [Diff Details](diff-details.md)
c64_pro.srcs/sources_1/rtl/.VSCodeCounter/2024-03-26_15-29-43/diff.txt
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Date : 2024-03-26 15:29:43
Directory : d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl
Total : 0 files, 0 codes, 0 comments, 0 blanks, all 0 lines
Languages
+----------+------------+------------+------------+------------+------------+
| language | files | code | comment | blank | total |
+----------+------------+------------+------------+------------+------------+
+----------+------------+------------+------------+------------+------------+
Directories
+------+------------+------------+------------+------------+------------+
| path | files | code | comment | blank | total |
+------+------------+------------+------------+------------+------------+
+------+------------+------------+------------+------------+------------+
Files
+----------+----------+------------+------------+------------+------------+
| filename | language | code | comment | blank | total |
+----------+----------+------------+------------+------------+------------+
| Total | | 0 | 0 | 0 | 0 |
+----------+----------+------------+------------+------------+------------+
c64_pro.srcs/sources_1/rtl/.VSCodeCounter/2024-03-26_15-29-43/results.csv
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"filename", "language", "Verilog", "VHDL", "comment", "blank", "total"
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\accel\accel_top.v", "Verilog", 117, 0, 13, 36, 166
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\accel\lis2dw12.v", "Verilog", 197, 0, 10, 31, 238
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\c64pro_top.v", "Verilog", 364, 0, 44, 78, 486
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_arrange.v", "Verilog", 195, 0, 16, 31, 242
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_if.v", "Verilog", 149, 0, 18, 27, 194
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_mod.v", "Verilog", 113, 0, 13, 29, 155
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi - backup.v", "Verilog", 186, 0, 12, 29, 227
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi.v", "Verilog", 218, 0, 10, 35, 263
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi_tb.v", "Verilog", 79, 0, 16, 21, 116
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_config.v", "Verilog", 118, 0, 16, 32, 166
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_top.v", "Verilog", 204, 0, 21, 52, 277
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_top_tb.v", "Verilog", 158, 0, 88, 40, 286
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_upload.v", "Verilog", 147, 0, 13, 29, 189
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\emg\emg_config.v", "Verilog", 81, 0, 14, 25, 120
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\emg\emg_top.v", "Verilog", 44, 0, 17, 17, 78
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\led_ctrl.v", "Verilog", 58, 0, 10, 12, 80
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\led_ctrl_tb.v", "Verilog", 34, 0, 19, 17, 70
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\pl_top.v", "Verilog", 320, 0, 35, 70, 425
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\pl_top_tb.v", "Verilog", 505, 0, 77, 116, 698
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\cnv_res_collect.v", "Verilog", 180, 0, 14, 30, 224
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\cnv_res_collect_tb.v", "Verilog", 119, 0, 20, 33, 172
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\dds_stim_16ch_tb.v", "Verilog", 74, 0, 16, 21, 111
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\dds_stim_16ch_tb.vhd", "VHDL", 0, 307, 135, 49, 491
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_mod.v", "Verilog", 84, 0, 7, 19, 110
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_top.v", "Verilog", 337, 0, 27, 86, 450
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_top_tb.v", "Verilog", 367, 0, 26, 83, 476
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\sine_gen.v", "Verilog", 154, 0, 22, 31, 207
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\sine_gen_tb.v", "Verilog", 129, 0, 18, 42, 189
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\stim_event_collect.v", "Verilog", 74, 0, 10, 14, 98
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\stim_monitor.v", "Verilog", 105, 0, 13, 14, 132
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_arrange.v", "Verilog", 174, 0, 18, 31, 223
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_arrange_tb.v", "Verilog", 268, 0, 19, 62, 349
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_distribute.v", "Verilog", 120, 0, 13, 26, 159
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_distribute_tb.v", "Verilog", 114, 0, 16, 24, 154
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_timer.v", "Verilog", 60, 0, 10, 15, 85
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_timer_tb.v", "Verilog", 55, 0, 15, 19, 89
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_config.v", "Verilog", 351, 0, 82, 74, 507
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_config_tb.v", "Verilog", 321, 0, 36, 101, 458
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_if.v", "Verilog", 268, 0, 25, 46, 339
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_if_tb.v", "Verilog", 172, 0, 39, 58, 269
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\adg1414_if.v", "Verilog", 136, 0, 13, 25, 174
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\adg1414_if_tb.v", "Verilog", 56, 0, 15, 17, 88
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\channel_switch.v", "Verilog", 169, 0, 25, 30, 224
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\channel_switch_tb.v", "Verilog", 52, 0, 16, 17, 85
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_detection.v", "Verilog", 21, 0, 1, 7, 29
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_top.v", "Verilog", 137, 0, 15, 32, 184
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_top_tb.v", "Verilog", 45, 0, 15, 16, 76
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_config.v", "Verilog", 96, 0, 14, 29, 139
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_sort.v", "Verilog", 141, 0, 12, 27, 180
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_top.v", "Verilog", 254, 0, 15, 45, 314
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\breath_gen.v", "Verilog", 123, 0, 13, 25, 161
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\debouncing.v", "Verilog", 93, 0, 10, 15, 118
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\pwm_gen.v", "Verilog", 40, 0, 4, 9, 53
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\spi_full_duplex_master.v", "Verilog", 148, 0, 12, 25, 185
"d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\spi_full_duplex_master_tb.v", "Verilog", 79, 0, 16, 21, 116
"Total", "-", 8403, 307, 1239, 1945, 11894
1 filename language Verilog VHDL comment blank total
2 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\accel\accel_top.v Verilog 117 0 13 36 166
3 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\accel\lis2dw12.v Verilog 197 0 10 31 238
4 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\c64pro_top.v Verilog 364 0 44 78 486
5 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_arrange.v Verilog 195 0 16 31 242
6 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_if.v Verilog 149 0 18 27 194
7 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_mod.v Verilog 113 0 13 29 155
8 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi - backup.v Verilog 186 0 12 29 227
9 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi.v Verilog 218 0 10 35 263
10 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi_tb.v Verilog 79 0 16 21 116
11 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_config.v Verilog 118 0 16 32 166
12 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_top.v Verilog 204 0 21 52 277
13 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_top_tb.v Verilog 158 0 88 40 286
14 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_upload.v Verilog 147 0 13 29 189
15 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\emg\emg_config.v Verilog 81 0 14 25 120
16 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\emg\emg_top.v Verilog 44 0 17 17 78
17 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\led_ctrl.v Verilog 58 0 10 12 80
18 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\led_ctrl_tb.v Verilog 34 0 19 17 70
19 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\pl_top.v Verilog 320 0 35 70 425
20 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\pl_top_tb.v Verilog 505 0 77 116 698
21 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\cnv_res_collect.v Verilog 180 0 14 30 224
22 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\cnv_res_collect_tb.v Verilog 119 0 20 33 172
23 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\dds_stim_16ch_tb.v Verilog 74 0 16 21 111
24 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\dds_stim_16ch_tb.vhd VHDL 0 307 135 49 491
25 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_mod.v Verilog 84 0 7 19 110
26 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_top.v Verilog 337 0 27 86 450
27 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_top_tb.v Verilog 367 0 26 83 476
28 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\sine_gen.v Verilog 154 0 22 31 207
29 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\sine_gen_tb.v Verilog 129 0 18 42 189
30 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\stim_event_collect.v Verilog 74 0 10 14 98
31 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\stim_monitor.v Verilog 105 0 13 14 132
32 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_arrange.v Verilog 174 0 18 31 223
33 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_arrange_tb.v Verilog 268 0 19 62 349
34 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_distribute.v Verilog 120 0 13 26 159
35 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_distribute_tb.v Verilog 114 0 16 24 154
36 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_timer.v Verilog 60 0 10 15 85
37 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_timer_tb.v Verilog 55 0 15 19 89
38 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_config.v Verilog 351 0 82 74 507
39 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_config_tb.v Verilog 321 0 36 101 458
40 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_if.v Verilog 268 0 25 46 339
41 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_if_tb.v Verilog 172 0 39 58 269
42 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\adg1414_if.v Verilog 136 0 13 25 174
43 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\adg1414_if_tb.v Verilog 56 0 15 17 88
44 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\channel_switch.v Verilog 169 0 25 30 224
45 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\channel_switch_tb.v Verilog 52 0 16 17 85
46 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_detection.v Verilog 21 0 1 7 29
47 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_top.v Verilog 137 0 15 32 184
48 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_top_tb.v Verilog 45 0 15 16 76
49 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_config.v Verilog 96 0 14 29 139
50 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_sort.v Verilog 141 0 12 27 180
51 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_top.v Verilog 254 0 15 45 314
52 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\breath_gen.v Verilog 123 0 13 25 161
53 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\debouncing.v Verilog 93 0 10 15 118
54 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\pwm_gen.v Verilog 40 0 4 9 53
55 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\spi_full_duplex_master.v Verilog 148 0 12 25 185
56 d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\spi_full_duplex_master_tb.v Verilog 79 0 16 21 116
57 Total - 8403 307 1239 1945 11894
c64_pro.srcs/sources_1/rtl/.VSCodeCounter/2024-03-26_15-29-43/results.json
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c64_pro.srcs/sources_1/rtl/.VSCodeCounter/2024-03-26_15-29-43/results.md
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# Summary
Date : 2024-03-26 15:29:43
Directory d:\\projects\\vivadoPrj\\c64_pro\\c64_pro.srcs\\sources_1\\rtl
Total : 55 files, 8710 codes, 1239 comments, 1945 blanks, all 11894 lines
Summary / [Details](details.md) / [Diff Summary](diff.md) / [Diff Details](diff-details.md)
## Languages
| language | files | code | comment | blank | total |
| :--- | ---: | ---: | ---: | ---: | ---: |
| Verilog | 54 | 8,403 | 1,104 | 1,896 | 11,403 |
| VHDL | 1 | 307 | 135 | 49 | 491 |
## Directories
| path | files | code | comment | blank | total |
| :--- | ---: | ---: | ---: | ---: | ---: |
| . | 55 | 8,710 | 1,239 | 1,945 | 11,894 |
| . (Files) | 5 | 1,281 | 185 | 293 | 1,759 |
| accel | 2 | 314 | 23 | 67 | 404 |
| eeg | 10 | 1,567 | 223 | 325 | 2,115 |
| emg | 2 | 125 | 31 | 42 | 198 |
| rhs2116 | 21 | 3,833 | 581 | 878 | 5,292 |
| switch | 4 | 413 | 69 | 89 | 571 |
| trigger | 3 | 203 | 31 | 55 | 289 |
| upload | 3 | 491 | 41 | 101 | 633 |
| utils | 5 | 483 | 55 | 95 | 633 |
Summary / [Details](details.md) / [Diff Summary](diff.md) / [Diff Details](diff-details.md)
c64_pro.srcs/sources_1/rtl/.VSCodeCounter/2024-03-26_15-29-43/results.txt
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Date : 2024-03-26 15:29:43
Directory : d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl
Total : 55 files, 8710 codes, 1239 comments, 1945 blanks, all 11894 lines
Languages
+----------+------------+------------+------------+------------+------------+
| language | files | code | comment | blank | total |
+----------+------------+------------+------------+------------+------------+
| Verilog | 54 | 8,403 | 1,104 | 1,896 | 11,403 |
| VHDL | 1 | 307 | 135 | 49 | 491 |
+----------+------------+------------+------------+------------+------------+
Directories
+--------------------------------------------------------------------------------------------+------------+------------+------------+------------+------------+
| path | files | code | comment | blank | total |
+--------------------------------------------------------------------------------------------+------------+------------+------------+------------+------------+
| . | 55 | 8,710 | 1,239 | 1,945 | 11,894 |
| . (Files) | 5 | 1,281 | 185 | 293 | 1,759 |
| accel | 2 | 314 | 23 | 67 | 404 |
| eeg | 10 | 1,567 | 223 | 325 | 2,115 |
| emg | 2 | 125 | 31 | 42 | 198 |
| rhs2116 | 21 | 3,833 | 581 | 878 | 5,292 |
| switch | 4 | 413 | 69 | 89 | 571 |
| trigger | 3 | 203 | 31 | 55 | 289 |
| upload | 3 | 491 | 41 | 101 | 633 |
| utils | 5 | 483 | 55 | 95 | 633 |
+--------------------------------------------------------------------------------------------+------------+------------+------------+------------+------------+
Files
+--------------------------------------------------------------------------------------------+----------+------------+------------+------------+------------+
| filename | language | code | comment | blank | total |
+--------------------------------------------------------------------------------------------+----------+------------+------------+------------+------------+
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\accel\accel_top.v | Verilog | 117 | 13 | 36 | 166 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\accel\lis2dw12.v | Verilog | 197 | 10 | 31 | 238 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\c64pro_top.v | Verilog | 364 | 44 | 78 | 486 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_arrange.v | Verilog | 195 | 16 | 31 | 242 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_if.v | Verilog | 149 | 18 | 27 | 194 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_mod.v | Verilog | 113 | 13 | 29 | 155 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi - backup.v | Verilog | 186 | 12 | 29 | 227 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi.v | Verilog | 218 | 10 | 35 | 263 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi_tb.v | Verilog | 79 | 16 | 21 | 116 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_config.v | Verilog | 118 | 16 | 32 | 166 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_top.v | Verilog | 204 | 21 | 52 | 277 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_top_tb.v | Verilog | 158 | 88 | 40 | 286 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_upload.v | Verilog | 147 | 13 | 29 | 189 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\emg\emg_config.v | Verilog | 81 | 14 | 25 | 120 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\emg\emg_top.v | Verilog | 44 | 17 | 17 | 78 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\led_ctrl.v | Verilog | 58 | 10 | 12 | 80 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\led_ctrl_tb.v | Verilog | 34 | 19 | 17 | 70 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\pl_top.v | Verilog | 320 | 35 | 70 | 425 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\pl_top_tb.v | Verilog | 505 | 77 | 116 | 698 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\cnv_res_collect.v | Verilog | 180 | 14 | 30 | 224 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\cnv_res_collect_tb.v | Verilog | 119 | 20 | 33 | 172 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\dds_stim_16ch_tb.v | Verilog | 74 | 16 | 21 | 111 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\dds_stim_16ch_tb.vhd | VHDL | 307 | 135 | 49 | 491 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_mod.v | Verilog | 84 | 7 | 19 | 110 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_top.v | Verilog | 337 | 27 | 86 | 450 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_top_tb.v | Verilog | 367 | 26 | 83 | 476 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\sine_gen.v | Verilog | 154 | 22 | 31 | 207 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\sine_gen_tb.v | Verilog | 129 | 18 | 42 | 189 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\stim_event_collect.v | Verilog | 74 | 10 | 14 | 98 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\stim_monitor.v | Verilog | 105 | 13 | 14 | 132 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_arrange.v | Verilog | 174 | 18 | 31 | 223 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_arrange_tb.v | Verilog | 268 | 19 | 62 | 349 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_distribute.v | Verilog | 120 | 13 | 26 | 159 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_distribute_tb.v | Verilog | 114 | 16 | 24 | 154 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_timer.v | Verilog | 60 | 10 | 15 | 85 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_timer_tb.v | Verilog | 55 | 15 | 19 | 89 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_config.v | Verilog | 351 | 82 | 74 | 507 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_config_tb.v | Verilog | 321 | 36 | 101 | 458 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_if.v | Verilog | 268 | 25 | 46 | 339 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_if_tb.v | Verilog | 172 | 39 | 58 | 269 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\adg1414_if.v | Verilog | 136 | 13 | 25 | 174 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\adg1414_if_tb.v | Verilog | 56 | 15 | 17 | 88 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\channel_switch.v | Verilog | 169 | 25 | 30 | 224 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\channel_switch_tb.v | Verilog | 52 | 16 | 17 | 85 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_detection.v | Verilog | 21 | 1 | 7 | 29 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_top.v | Verilog | 137 | 15 | 32 | 184 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_top_tb.v | Verilog | 45 | 15 | 16 | 76 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_config.v | Verilog | 96 | 14 | 29 | 139 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_sort.v | Verilog | 141 | 12 | 27 | 180 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_top.v | Verilog | 254 | 15 | 45 | 314 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\breath_gen.v | Verilog | 123 | 13 | 25 | 161 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\debouncing.v | Verilog | 93 | 10 | 15 | 118 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\pwm_gen.v | Verilog | 40 | 4 | 9 | 53 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\spi_full_duplex_master.v | Verilog | 148 | 12 | 25 | 185 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\spi_full_duplex_master_tb.v | Verilog | 79 | 16 | 21 | 116 |
| Total | | 8,710 | 1,239 | 1,945 | 11,894 |
+--------------------------------------------------------------------------------------------+----------+------------+------------+------------+------------+